1 // SPDX-License-Identifier: GPL-2.0+
4 * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
8 * Designware ethernet IP driver for U-Boot
20 #include <dm/device_compat.h>
21 #include <dm/devres.h>
22 #include <linux/compiler.h>
23 #include <linux/err.h>
24 #include <linux/kernel.h>
26 #include <power/regulator.h>
27 #include "designware.h"
29 static int dw_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
32 struct dw_eth_dev *priv = dev_get_priv((struct udevice *)bus->priv);
33 struct eth_mac_regs *mac_p = priv->mac_regs_p;
35 struct eth_mac_regs *mac_p = bus->priv;
39 int timeout = CONFIG_MDIO_TIMEOUT;
41 miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) |
42 ((reg << MIIREGSHIFT) & MII_REGMSK);
44 writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr);
47 while (get_timer(start) < timeout) {
48 if (!(readl(&mac_p->miiaddr) & MII_BUSY))
49 return readl(&mac_p->miidata);
56 static int dw_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
60 struct dw_eth_dev *priv = dev_get_priv((struct udevice *)bus->priv);
61 struct eth_mac_regs *mac_p = priv->mac_regs_p;
63 struct eth_mac_regs *mac_p = bus->priv;
67 int ret = -ETIMEDOUT, timeout = CONFIG_MDIO_TIMEOUT;
69 writel(val, &mac_p->miidata);
70 miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) |
71 ((reg << MIIREGSHIFT) & MII_REGMSK) | MII_WRITE;
73 writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr);
76 while (get_timer(start) < timeout) {
77 if (!(readl(&mac_p->miiaddr) & MII_BUSY)) {
87 #if defined(CONFIG_DM_ETH) && CONFIG_IS_ENABLED(DM_GPIO)
88 static int dw_mdio_reset(struct mii_dev *bus)
90 struct udevice *dev = bus->priv;
91 struct dw_eth_dev *priv = dev_get_priv(dev);
92 struct dw_eth_pdata *pdata = dev_get_platdata(dev);
95 if (!dm_gpio_is_valid(&priv->reset_gpio))
99 ret = dm_gpio_set_value(&priv->reset_gpio, 0);
103 udelay(pdata->reset_delays[0]);
105 ret = dm_gpio_set_value(&priv->reset_gpio, 1);
109 udelay(pdata->reset_delays[1]);
111 ret = dm_gpio_set_value(&priv->reset_gpio, 0);
115 udelay(pdata->reset_delays[2]);
121 static int dw_mdio_init(const char *name, void *priv)
123 struct mii_dev *bus = mdio_alloc();
126 printf("Failed to allocate MDIO bus\n");
130 bus->read = dw_mdio_read;
131 bus->write = dw_mdio_write;
132 snprintf(bus->name, sizeof(bus->name), "%s", name);
133 #if defined(CONFIG_DM_ETH) && CONFIG_IS_ENABLED(DM_GPIO)
134 bus->reset = dw_mdio_reset;
139 return mdio_register(bus);
142 static void tx_descs_init(struct dw_eth_dev *priv)
144 struct eth_dma_regs *dma_p = priv->dma_regs_p;
145 struct dmamacdescr *desc_table_p = &priv->tx_mac_descrtable[0];
146 char *txbuffs = &priv->txbuffs[0];
147 struct dmamacdescr *desc_p;
150 for (idx = 0; idx < CONFIG_TX_DESCR_NUM; idx++) {
151 desc_p = &desc_table_p[idx];
152 desc_p->dmamac_addr = (ulong)&txbuffs[idx * CONFIG_ETH_BUFSIZE];
153 desc_p->dmamac_next = (ulong)&desc_table_p[idx + 1];
155 #if defined(CONFIG_DW_ALTDESCRIPTOR)
156 desc_p->txrx_status &= ~(DESC_TXSTS_TXINT | DESC_TXSTS_TXLAST |
157 DESC_TXSTS_TXFIRST | DESC_TXSTS_TXCRCDIS |
158 DESC_TXSTS_TXCHECKINSCTRL |
159 DESC_TXSTS_TXRINGEND | DESC_TXSTS_TXPADDIS);
161 desc_p->txrx_status |= DESC_TXSTS_TXCHAIN;
162 desc_p->dmamac_cntl = 0;
163 desc_p->txrx_status &= ~(DESC_TXSTS_MSK | DESC_TXSTS_OWNBYDMA);
165 desc_p->dmamac_cntl = DESC_TXCTRL_TXCHAIN;
166 desc_p->txrx_status = 0;
170 /* Correcting the last pointer of the chain */
171 desc_p->dmamac_next = (ulong)&desc_table_p[0];
173 /* Flush all Tx buffer descriptors at once */
174 flush_dcache_range((ulong)priv->tx_mac_descrtable,
175 (ulong)priv->tx_mac_descrtable +
176 sizeof(priv->tx_mac_descrtable));
178 writel((ulong)&desc_table_p[0], &dma_p->txdesclistaddr);
179 priv->tx_currdescnum = 0;
182 static void rx_descs_init(struct dw_eth_dev *priv)
184 struct eth_dma_regs *dma_p = priv->dma_regs_p;
185 struct dmamacdescr *desc_table_p = &priv->rx_mac_descrtable[0];
186 char *rxbuffs = &priv->rxbuffs[0];
187 struct dmamacdescr *desc_p;
190 /* Before passing buffers to GMAC we need to make sure zeros
191 * written there right after "priv" structure allocation were
193 * Otherwise there's a chance to get some of them flushed in RAM when
194 * GMAC is already pushing data to RAM via DMA. This way incoming from
195 * GMAC data will be corrupted. */
196 flush_dcache_range((ulong)rxbuffs, (ulong)rxbuffs + RX_TOTAL_BUFSIZE);
198 for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) {
199 desc_p = &desc_table_p[idx];
200 desc_p->dmamac_addr = (ulong)&rxbuffs[idx * CONFIG_ETH_BUFSIZE];
201 desc_p->dmamac_next = (ulong)&desc_table_p[idx + 1];
203 desc_p->dmamac_cntl =
204 (MAC_MAX_FRAME_SZ & DESC_RXCTRL_SIZE1MASK) |
207 desc_p->txrx_status = DESC_RXSTS_OWNBYDMA;
210 /* Correcting the last pointer of the chain */
211 desc_p->dmamac_next = (ulong)&desc_table_p[0];
213 /* Flush all Rx buffer descriptors at once */
214 flush_dcache_range((ulong)priv->rx_mac_descrtable,
215 (ulong)priv->rx_mac_descrtable +
216 sizeof(priv->rx_mac_descrtable));
218 writel((ulong)&desc_table_p[0], &dma_p->rxdesclistaddr);
219 priv->rx_currdescnum = 0;
222 static int _dw_write_hwaddr(struct dw_eth_dev *priv, u8 *mac_id)
224 struct eth_mac_regs *mac_p = priv->mac_regs_p;
225 u32 macid_lo, macid_hi;
227 macid_lo = mac_id[0] + (mac_id[1] << 8) + (mac_id[2] << 16) +
229 macid_hi = mac_id[4] + (mac_id[5] << 8);
231 writel(macid_hi, &mac_p->macaddr0hi);
232 writel(macid_lo, &mac_p->macaddr0lo);
237 static int dw_adjust_link(struct dw_eth_dev *priv, struct eth_mac_regs *mac_p,
238 struct phy_device *phydev)
240 u32 conf = readl(&mac_p->conf) | FRAMEBURSTENABLE | DISABLERXOWN;
243 printf("%s: No link.\n", phydev->dev->name);
247 if (phydev->speed != 1000)
248 conf |= MII_PORTSELECT;
250 conf &= ~MII_PORTSELECT;
252 if (phydev->speed == 100)
256 conf |= FULLDPLXMODE;
258 writel(conf, &mac_p->conf);
260 printf("Speed: %d, %s duplex%s\n", phydev->speed,
261 (phydev->duplex) ? "full" : "half",
262 (phydev->port == PORT_FIBRE) ? ", fiber mode" : "");
267 static void _dw_eth_halt(struct dw_eth_dev *priv)
269 struct eth_mac_regs *mac_p = priv->mac_regs_p;
270 struct eth_dma_regs *dma_p = priv->dma_regs_p;
272 writel(readl(&mac_p->conf) & ~(RXENABLE | TXENABLE), &mac_p->conf);
273 writel(readl(&dma_p->opmode) & ~(RXSTART | TXSTART), &dma_p->opmode);
275 phy_shutdown(priv->phydev);
278 int designware_eth_init(struct dw_eth_dev *priv, u8 *enetaddr)
280 struct eth_mac_regs *mac_p = priv->mac_regs_p;
281 struct eth_dma_regs *dma_p = priv->dma_regs_p;
285 writel(readl(&dma_p->busmode) | DMAMAC_SRST, &dma_p->busmode);
288 * When a MII PHY is used, we must set the PS bit for the DMA
291 if (priv->phydev->interface == PHY_INTERFACE_MODE_MII)
292 writel(readl(&mac_p->conf) | MII_PORTSELECT, &mac_p->conf);
294 writel(readl(&mac_p->conf) & ~MII_PORTSELECT, &mac_p->conf);
296 start = get_timer(0);
297 while (readl(&dma_p->busmode) & DMAMAC_SRST) {
298 if (get_timer(start) >= CONFIG_MACRESET_TIMEOUT) {
299 printf("DMA reset timeout\n");
307 * Soft reset above clears HW address registers.
308 * So we have to set it here once again.
310 _dw_write_hwaddr(priv, enetaddr);
315 writel(FIXEDBURST | PRIORXTX_41 | DMA_PBL, &dma_p->busmode);
317 #ifndef CONFIG_DW_MAC_FORCE_THRESHOLD_MODE
318 writel(readl(&dma_p->opmode) | FLUSHTXFIFO | STOREFORWARD,
321 writel(readl(&dma_p->opmode) | FLUSHTXFIFO,
325 writel(readl(&dma_p->opmode) | RXSTART | TXSTART, &dma_p->opmode);
327 #ifdef CONFIG_DW_AXI_BURST_LEN
328 writel((CONFIG_DW_AXI_BURST_LEN & 0x1FF >> 1), &dma_p->axibus);
331 /* Start up the PHY */
332 ret = phy_startup(priv->phydev);
334 printf("Could not initialize PHY %s\n",
335 priv->phydev->dev->name);
339 ret = dw_adjust_link(priv, mac_p, priv->phydev);
346 int designware_eth_enable(struct dw_eth_dev *priv)
348 struct eth_mac_regs *mac_p = priv->mac_regs_p;
350 if (!priv->phydev->link)
353 writel(readl(&mac_p->conf) | RXENABLE | TXENABLE, &mac_p->conf);
360 static int _dw_eth_send(struct dw_eth_dev *priv, void *packet, int length)
362 struct eth_dma_regs *dma_p = priv->dma_regs_p;
363 u32 desc_num = priv->tx_currdescnum;
364 struct dmamacdescr *desc_p = &priv->tx_mac_descrtable[desc_num];
365 ulong desc_start = (ulong)desc_p;
366 ulong desc_end = desc_start +
367 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
368 ulong data_start = desc_p->dmamac_addr;
369 ulong data_end = data_start + roundup(length, ARCH_DMA_MINALIGN);
371 * Strictly we only need to invalidate the "txrx_status" field
372 * for the following check, but on some platforms we cannot
373 * invalidate only 4 bytes, so we flush the entire descriptor,
374 * which is 16 bytes in total. This is safe because the
375 * individual descriptors in the array are each aligned to
376 * ARCH_DMA_MINALIGN and padded appropriately.
378 invalidate_dcache_range(desc_start, desc_end);
380 /* Check if the descriptor is owned by CPU */
381 if (desc_p->txrx_status & DESC_TXSTS_OWNBYDMA) {
382 printf("CPU not owner of tx frame\n");
386 memcpy((void *)data_start, packet, length);
387 if (length < ETH_ZLEN) {
388 memset(&((char *)data_start)[length], 0, ETH_ZLEN - length);
392 /* Flush data to be sent */
393 flush_dcache_range(data_start, data_end);
395 #if defined(CONFIG_DW_ALTDESCRIPTOR)
396 desc_p->txrx_status |= DESC_TXSTS_TXFIRST | DESC_TXSTS_TXLAST;
397 desc_p->dmamac_cntl = (desc_p->dmamac_cntl & ~DESC_TXCTRL_SIZE1MASK) |
398 ((length << DESC_TXCTRL_SIZE1SHFT) &
399 DESC_TXCTRL_SIZE1MASK);
401 desc_p->txrx_status &= ~(DESC_TXSTS_MSK);
402 desc_p->txrx_status |= DESC_TXSTS_OWNBYDMA;
404 desc_p->dmamac_cntl = (desc_p->dmamac_cntl & ~DESC_TXCTRL_SIZE1MASK) |
405 ((length << DESC_TXCTRL_SIZE1SHFT) &
406 DESC_TXCTRL_SIZE1MASK) | DESC_TXCTRL_TXLAST |
409 desc_p->txrx_status = DESC_TXSTS_OWNBYDMA;
412 /* Flush modified buffer descriptor */
413 flush_dcache_range(desc_start, desc_end);
415 /* Test the wrap-around condition. */
416 if (++desc_num >= CONFIG_TX_DESCR_NUM)
419 priv->tx_currdescnum = desc_num;
421 /* Start the transmission */
422 writel(POLL_DATA, &dma_p->txpolldemand);
427 static int _dw_eth_recv(struct dw_eth_dev *priv, uchar **packetp)
429 u32 status, desc_num = priv->rx_currdescnum;
430 struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num];
431 int length = -EAGAIN;
432 ulong desc_start = (ulong)desc_p;
433 ulong desc_end = desc_start +
434 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
435 ulong data_start = desc_p->dmamac_addr;
438 /* Invalidate entire buffer descriptor */
439 invalidate_dcache_range(desc_start, desc_end);
441 status = desc_p->txrx_status;
443 /* Check if the owner is the CPU */
444 if (!(status & DESC_RXSTS_OWNBYDMA)) {
446 length = (status & DESC_RXSTS_FRMLENMSK) >>
447 DESC_RXSTS_FRMLENSHFT;
449 /* Invalidate received data */
450 data_end = data_start + roundup(length, ARCH_DMA_MINALIGN);
451 invalidate_dcache_range(data_start, data_end);
452 *packetp = (uchar *)(ulong)desc_p->dmamac_addr;
458 static int _dw_free_pkt(struct dw_eth_dev *priv)
460 u32 desc_num = priv->rx_currdescnum;
461 struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num];
462 ulong desc_start = (ulong)desc_p;
463 ulong desc_end = desc_start +
464 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
467 * Make the current descriptor valid again and go to
470 desc_p->txrx_status |= DESC_RXSTS_OWNBYDMA;
472 /* Flush only status field - others weren't changed */
473 flush_dcache_range(desc_start, desc_end);
475 /* Test the wrap-around condition. */
476 if (++desc_num >= CONFIG_RX_DESCR_NUM)
478 priv->rx_currdescnum = desc_num;
483 static int dw_phy_init(struct dw_eth_dev *priv, void *dev)
485 struct phy_device *phydev;
486 int phy_addr = -1, ret;
488 #ifdef CONFIG_PHY_ADDR
489 phy_addr = CONFIG_PHY_ADDR;
492 phydev = phy_connect(priv->bus, phy_addr, dev, priv->interface);
496 phydev->supported &= PHY_GBIT_FEATURES;
497 if (priv->max_speed) {
498 ret = phy_set_supported(phydev, priv->max_speed);
502 phydev->advertising = phydev->supported;
504 priv->phydev = phydev;
510 #ifndef CONFIG_DM_ETH
511 static int dw_eth_init(struct eth_device *dev, bd_t *bis)
515 ret = designware_eth_init(dev->priv, dev->enetaddr);
517 ret = designware_eth_enable(dev->priv);
522 static int dw_eth_send(struct eth_device *dev, void *packet, int length)
524 return _dw_eth_send(dev->priv, packet, length);
527 static int dw_eth_recv(struct eth_device *dev)
532 length = _dw_eth_recv(dev->priv, &packet);
533 if (length == -EAGAIN)
535 net_process_received_packet(packet, length);
537 _dw_free_pkt(dev->priv);
542 static void dw_eth_halt(struct eth_device *dev)
544 return _dw_eth_halt(dev->priv);
547 static int dw_write_hwaddr(struct eth_device *dev)
549 return _dw_write_hwaddr(dev->priv, dev->enetaddr);
552 int designware_initialize(ulong base_addr, u32 interface)
554 struct eth_device *dev;
555 struct dw_eth_dev *priv;
557 dev = (struct eth_device *) malloc(sizeof(struct eth_device));
562 * Since the priv structure contains the descriptors which need a strict
563 * buswidth alignment, memalign is used to allocate memory
565 priv = (struct dw_eth_dev *) memalign(ARCH_DMA_MINALIGN,
566 sizeof(struct dw_eth_dev));
572 if ((phys_addr_t)priv + sizeof(*priv) > (1ULL << 32)) {
573 printf("designware: buffers are outside DMA memory\n");
577 memset(dev, 0, sizeof(struct eth_device));
578 memset(priv, 0, sizeof(struct dw_eth_dev));
580 sprintf(dev->name, "dwmac.%lx", base_addr);
581 dev->iobase = (int)base_addr;
585 priv->mac_regs_p = (struct eth_mac_regs *)base_addr;
586 priv->dma_regs_p = (struct eth_dma_regs *)(base_addr +
589 dev->init = dw_eth_init;
590 dev->send = dw_eth_send;
591 dev->recv = dw_eth_recv;
592 dev->halt = dw_eth_halt;
593 dev->write_hwaddr = dw_write_hwaddr;
597 priv->interface = interface;
599 dw_mdio_init(dev->name, priv->mac_regs_p);
600 priv->bus = miiphy_get_dev_by_name(dev->name);
602 return dw_phy_init(priv, dev);
607 static int designware_eth_start(struct udevice *dev)
609 struct eth_pdata *pdata = dev_get_platdata(dev);
610 struct dw_eth_dev *priv = dev_get_priv(dev);
613 ret = designware_eth_init(priv, pdata->enetaddr);
616 ret = designware_eth_enable(priv);
623 int designware_eth_send(struct udevice *dev, void *packet, int length)
625 struct dw_eth_dev *priv = dev_get_priv(dev);
627 return _dw_eth_send(priv, packet, length);
630 int designware_eth_recv(struct udevice *dev, int flags, uchar **packetp)
632 struct dw_eth_dev *priv = dev_get_priv(dev);
634 return _dw_eth_recv(priv, packetp);
637 int designware_eth_free_pkt(struct udevice *dev, uchar *packet, int length)
639 struct dw_eth_dev *priv = dev_get_priv(dev);
641 return _dw_free_pkt(priv);
644 void designware_eth_stop(struct udevice *dev)
646 struct dw_eth_dev *priv = dev_get_priv(dev);
648 return _dw_eth_halt(priv);
651 int designware_eth_write_hwaddr(struct udevice *dev)
653 struct eth_pdata *pdata = dev_get_platdata(dev);
654 struct dw_eth_dev *priv = dev_get_priv(dev);
656 return _dw_write_hwaddr(priv, pdata->enetaddr);
659 static int designware_eth_bind(struct udevice *dev)
662 static int num_cards;
665 /* Create a unique device name for PCI type devices */
666 if (device_is_on_pci_bus(dev)) {
667 sprintf(name, "eth_designware#%u", num_cards++);
668 device_set_name(dev, name);
675 int designware_eth_probe(struct udevice *dev)
677 struct eth_pdata *pdata = dev_get_platdata(dev);
678 struct dw_eth_dev *priv = dev_get_priv(dev);
679 u32 iobase = pdata->iobase;
682 struct reset_ctl_bulk reset_bulk;
686 priv->clock_count = 0;
687 clock_nb = dev_count_phandle_with_args(dev, "clocks", "#clock-cells");
689 priv->clocks = devm_kcalloc(dev, clock_nb, sizeof(struct clk),
694 for (i = 0; i < clock_nb; i++) {
695 err = clk_get_by_index(dev, i, &priv->clocks[i]);
699 err = clk_enable(&priv->clocks[i]);
700 if (err && err != -ENOSYS && err != -ENOTSUPP) {
701 pr_err("failed to enable clock %d\n", i);
702 clk_free(&priv->clocks[i]);
707 } else if (clock_nb != -ENOENT) {
708 pr_err("failed to get clock phandle(%d)\n", clock_nb);
713 #if defined(CONFIG_DM_REGULATOR)
714 struct udevice *phy_supply;
716 ret = device_get_supply_regulator(dev, "phy-supply",
719 debug("%s: No phy supply\n", dev->name);
721 ret = regulator_set_enable(phy_supply, true);
723 puts("Error enabling phy supply\n");
729 ret = reset_get_bulk(dev, &reset_bulk);
731 dev_warn(dev, "Can't get reset: %d\n", ret);
733 reset_deassert_bulk(&reset_bulk);
737 * If we are on PCI bus, either directly attached to a PCI root port,
738 * or via a PCI bridge, fill in platdata before we probe the hardware.
740 if (device_is_on_pci_bus(dev)) {
741 dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0, &iobase);
742 iobase &= PCI_BASE_ADDRESS_MEM_MASK;
743 iobase = dm_pci_mem_to_phys(dev, iobase);
745 pdata->iobase = iobase;
746 pdata->phy_interface = PHY_INTERFACE_MODE_RMII;
750 debug("%s, iobase=%x, priv=%p\n", __func__, iobase, priv);
752 priv->mac_regs_p = (struct eth_mac_regs *)ioaddr;
753 priv->dma_regs_p = (struct eth_dma_regs *)(ioaddr + DW_DMA_BASE_OFFSET);
754 priv->interface = pdata->phy_interface;
755 priv->max_speed = pdata->max_speed;
757 ret = dw_mdio_init(dev->name, dev);
762 priv->bus = miiphy_get_dev_by_name(dev->name);
764 ret = dw_phy_init(priv, dev);
765 debug("%s, ret=%d\n", __func__, ret);
769 /* continue here for cleanup if no PHY found */
771 mdio_unregister(priv->bus);
772 mdio_free(priv->bus);
777 ret = clk_release_all(priv->clocks, priv->clock_count);
779 pr_err("failed to disable all clocks\n");
785 static int designware_eth_remove(struct udevice *dev)
787 struct dw_eth_dev *priv = dev_get_priv(dev);
790 mdio_unregister(priv->bus);
791 mdio_free(priv->bus);
794 return clk_release_all(priv->clocks, priv->clock_count);
800 const struct eth_ops designware_eth_ops = {
801 .start = designware_eth_start,
802 .send = designware_eth_send,
803 .recv = designware_eth_recv,
804 .free_pkt = designware_eth_free_pkt,
805 .stop = designware_eth_stop,
806 .write_hwaddr = designware_eth_write_hwaddr,
809 int designware_eth_ofdata_to_platdata(struct udevice *dev)
811 struct dw_eth_pdata *dw_pdata = dev_get_platdata(dev);
812 #if CONFIG_IS_ENABLED(DM_GPIO)
813 struct dw_eth_dev *priv = dev_get_priv(dev);
815 struct eth_pdata *pdata = &dw_pdata->eth_pdata;
816 const char *phy_mode;
817 #if CONFIG_IS_ENABLED(DM_GPIO)
818 int reset_flags = GPIOD_IS_OUT;
822 pdata->iobase = dev_read_addr(dev);
823 pdata->phy_interface = -1;
824 phy_mode = dev_read_string(dev, "phy-mode");
826 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
827 if (pdata->phy_interface == -1) {
828 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
832 pdata->max_speed = dev_read_u32_default(dev, "max-speed", 0);
834 #if CONFIG_IS_ENABLED(DM_GPIO)
835 if (dev_read_bool(dev, "snps,reset-active-low"))
836 reset_flags |= GPIOD_ACTIVE_LOW;
838 ret = gpio_request_by_name(dev, "snps,reset-gpio", 0,
839 &priv->reset_gpio, reset_flags);
841 ret = dev_read_u32_array(dev, "snps,reset-delays-us",
842 dw_pdata->reset_delays, 3);
843 } else if (ret == -ENOENT) {
851 static const struct udevice_id designware_eth_ids[] = {
852 { .compatible = "allwinner,sun7i-a20-gmac" },
853 { .compatible = "amlogic,meson6-dwmac" },
854 { .compatible = "amlogic,meson-gx-dwmac" },
855 { .compatible = "amlogic,meson-gxbb-dwmac" },
856 { .compatible = "amlogic,meson-axg-dwmac" },
857 { .compatible = "st,stm32-dwmac" },
858 { .compatible = "snps,arc-dwmac-3.70a" },
862 U_BOOT_DRIVER(eth_designware) = {
863 .name = "eth_designware",
865 .of_match = designware_eth_ids,
866 .ofdata_to_platdata = designware_eth_ofdata_to_platdata,
867 .bind = designware_eth_bind,
868 .probe = designware_eth_probe,
869 .remove = designware_eth_remove,
870 .ops = &designware_eth_ops,
871 .priv_auto_alloc_size = sizeof(struct dw_eth_dev),
872 .platdata_auto_alloc_size = sizeof(struct dw_eth_pdata),
873 .flags = DM_FLAG_ALLOC_PRIV_DMA,
876 static struct pci_device_id supported[] = {
877 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_EMAC) },
881 U_BOOT_PCI_DEVICE(eth_designware, supported);