3 * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
5 * SPDX-License-Identifier: GPL-2.0+
9 * Designware ethernet IP driver for u-boot
15 #include <linux/compiler.h>
16 #include <linux/err.h>
18 #include "designware.h"
20 #if !defined(CONFIG_PHYLIB)
21 # error "DesignWare Ether MAC requires PHYLIB - missing CONFIG_PHYLIB"
24 static int dw_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
26 struct eth_mac_regs *mac_p = bus->priv;
29 int timeout = CONFIG_MDIO_TIMEOUT;
31 miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) |
32 ((reg << MIIREGSHIFT) & MII_REGMSK);
34 writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr);
37 while (get_timer(start) < timeout) {
38 if (!(readl(&mac_p->miiaddr) & MII_BUSY))
39 return readl(&mac_p->miidata);
46 static int dw_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
49 struct eth_mac_regs *mac_p = bus->priv;
52 int ret = -1, timeout = CONFIG_MDIO_TIMEOUT;
54 writel(val, &mac_p->miidata);
55 miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) |
56 ((reg << MIIREGSHIFT) & MII_REGMSK) | MII_WRITE;
58 writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr);
61 while (get_timer(start) < timeout) {
62 if (!(readl(&mac_p->miiaddr) & MII_BUSY)) {
72 static int dw_mdio_init(char *name, struct eth_mac_regs *mac_regs_p)
74 struct mii_dev *bus = mdio_alloc();
77 printf("Failed to allocate MDIO bus\n");
81 bus->read = dw_mdio_read;
82 bus->write = dw_mdio_write;
83 sprintf(bus->name, name);
85 bus->priv = (void *)mac_regs_p;
87 return mdio_register(bus);
90 static void tx_descs_init(struct eth_device *dev)
92 struct dw_eth_dev *priv = dev->priv;
93 struct eth_dma_regs *dma_p = priv->dma_regs_p;
94 struct dmamacdescr *desc_table_p = &priv->tx_mac_descrtable[0];
95 char *txbuffs = &priv->txbuffs[0];
96 struct dmamacdescr *desc_p;
99 for (idx = 0; idx < CONFIG_TX_DESCR_NUM; idx++) {
100 desc_p = &desc_table_p[idx];
101 desc_p->dmamac_addr = &txbuffs[idx * CONFIG_ETH_BUFSIZE];
102 desc_p->dmamac_next = &desc_table_p[idx + 1];
104 #if defined(CONFIG_DW_ALTDESCRIPTOR)
105 desc_p->txrx_status &= ~(DESC_TXSTS_TXINT | DESC_TXSTS_TXLAST |
106 DESC_TXSTS_TXFIRST | DESC_TXSTS_TXCRCDIS | \
107 DESC_TXSTS_TXCHECKINSCTRL | \
108 DESC_TXSTS_TXRINGEND | DESC_TXSTS_TXPADDIS);
110 desc_p->txrx_status |= DESC_TXSTS_TXCHAIN;
111 desc_p->dmamac_cntl = 0;
112 desc_p->txrx_status &= ~(DESC_TXSTS_MSK | DESC_TXSTS_OWNBYDMA);
114 desc_p->dmamac_cntl = DESC_TXCTRL_TXCHAIN;
115 desc_p->txrx_status = 0;
119 /* Correcting the last pointer of the chain */
120 desc_p->dmamac_next = &desc_table_p[0];
122 /* Flush all Tx buffer descriptors at once */
123 flush_dcache_range((unsigned int)priv->tx_mac_descrtable,
124 (unsigned int)priv->tx_mac_descrtable +
125 sizeof(priv->tx_mac_descrtable));
127 writel((ulong)&desc_table_p[0], &dma_p->txdesclistaddr);
128 priv->tx_currdescnum = 0;
131 static void rx_descs_init(struct eth_device *dev)
133 struct dw_eth_dev *priv = dev->priv;
134 struct eth_dma_regs *dma_p = priv->dma_regs_p;
135 struct dmamacdescr *desc_table_p = &priv->rx_mac_descrtable[0];
136 char *rxbuffs = &priv->rxbuffs[0];
137 struct dmamacdescr *desc_p;
140 /* Before passing buffers to GMAC we need to make sure zeros
141 * written there right after "priv" structure allocation were
143 * Otherwise there's a chance to get some of them flushed in RAM when
144 * GMAC is already pushing data to RAM via DMA. This way incoming from
145 * GMAC data will be corrupted. */
146 flush_dcache_range((unsigned int)rxbuffs, (unsigned int)rxbuffs +
149 for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) {
150 desc_p = &desc_table_p[idx];
151 desc_p->dmamac_addr = &rxbuffs[idx * CONFIG_ETH_BUFSIZE];
152 desc_p->dmamac_next = &desc_table_p[idx + 1];
154 desc_p->dmamac_cntl =
155 (MAC_MAX_FRAME_SZ & DESC_RXCTRL_SIZE1MASK) | \
158 desc_p->txrx_status = DESC_RXSTS_OWNBYDMA;
161 /* Correcting the last pointer of the chain */
162 desc_p->dmamac_next = &desc_table_p[0];
164 /* Flush all Rx buffer descriptors at once */
165 flush_dcache_range((unsigned int)priv->rx_mac_descrtable,
166 (unsigned int)priv->rx_mac_descrtable +
167 sizeof(priv->rx_mac_descrtable));
169 writel((ulong)&desc_table_p[0], &dma_p->rxdesclistaddr);
170 priv->rx_currdescnum = 0;
173 static int dw_write_hwaddr(struct eth_device *dev)
175 struct dw_eth_dev *priv = dev->priv;
176 struct eth_mac_regs *mac_p = priv->mac_regs_p;
177 u32 macid_lo, macid_hi;
178 u8 *mac_id = &dev->enetaddr[0];
180 macid_lo = mac_id[0] + (mac_id[1] << 8) + (mac_id[2] << 16) +
182 macid_hi = mac_id[4] + (mac_id[5] << 8);
184 writel(macid_hi, &mac_p->macaddr0hi);
185 writel(macid_lo, &mac_p->macaddr0lo);
190 static void dw_adjust_link(struct eth_mac_regs *mac_p,
191 struct phy_device *phydev)
193 u32 conf = readl(&mac_p->conf) | FRAMEBURSTENABLE | DISABLERXOWN;
196 printf("%s: No link.\n", phydev->dev->name);
200 if (phydev->speed != 1000)
201 conf |= MII_PORTSELECT;
203 if (phydev->speed == 100)
207 conf |= FULLDPLXMODE;
209 writel(conf, &mac_p->conf);
211 printf("Speed: %d, %s duplex%s\n", phydev->speed,
212 (phydev->duplex) ? "full" : "half",
213 (phydev->port == PORT_FIBRE) ? ", fiber mode" : "");
216 static void dw_eth_halt(struct eth_device *dev)
218 struct dw_eth_dev *priv = dev->priv;
219 struct eth_mac_regs *mac_p = priv->mac_regs_p;
220 struct eth_dma_regs *dma_p = priv->dma_regs_p;
222 writel(readl(&mac_p->conf) & ~(RXENABLE | TXENABLE), &mac_p->conf);
223 writel(readl(&dma_p->opmode) & ~(RXSTART | TXSTART), &dma_p->opmode);
225 phy_shutdown(priv->phydev);
228 static int dw_eth_init(struct eth_device *dev, bd_t *bis)
230 struct dw_eth_dev *priv = dev->priv;
231 struct eth_mac_regs *mac_p = priv->mac_regs_p;
232 struct eth_dma_regs *dma_p = priv->dma_regs_p;
235 writel(readl(&dma_p->busmode) | DMAMAC_SRST, &dma_p->busmode);
237 start = get_timer(0);
238 while (readl(&dma_p->busmode) & DMAMAC_SRST) {
239 if (get_timer(start) >= CONFIG_MACRESET_TIMEOUT)
245 /* Soft reset above clears HW address registers.
246 * So we have to set it here once again */
247 dw_write_hwaddr(dev);
252 writel(FIXEDBURST | PRIORXTX_41 | DMA_PBL, &dma_p->busmode);
254 writel(readl(&dma_p->opmode) | FLUSHTXFIFO | STOREFORWARD,
257 writel(readl(&dma_p->opmode) | RXSTART | TXSTART, &dma_p->opmode);
259 /* Start up the PHY */
260 if (phy_startup(priv->phydev)) {
261 printf("Could not initialize PHY %s\n",
262 priv->phydev->dev->name);
266 dw_adjust_link(mac_p, priv->phydev);
268 if (!priv->phydev->link)
271 writel(readl(&mac_p->conf) | RXENABLE | TXENABLE, &mac_p->conf);
276 static int dw_eth_send(struct eth_device *dev, void *packet, int length)
278 struct dw_eth_dev *priv = dev->priv;
279 struct eth_dma_regs *dma_p = priv->dma_regs_p;
280 u32 desc_num = priv->tx_currdescnum;
281 struct dmamacdescr *desc_p = &priv->tx_mac_descrtable[desc_num];
284 * Strictly we only need to invalidate the "txrx_status" field
285 * for the following check, but on some platforms we cannot
286 * invalidate only 4 bytes, so roundup to
287 * ARCH_DMA_MINALIGN. This is safe because the individual
288 * descriptors in the array are each aligned to
291 invalidate_dcache_range(
292 (unsigned long)desc_p,
293 (unsigned long)desc_p +
294 roundup(sizeof(desc_p->txrx_status), ARCH_DMA_MINALIGN));
296 /* Check if the descriptor is owned by CPU */
297 if (desc_p->txrx_status & DESC_TXSTS_OWNBYDMA) {
298 printf("CPU not owner of tx frame\n");
302 memcpy((void *)desc_p->dmamac_addr, packet, length);
304 /* Flush data to be sent */
305 flush_dcache_range((unsigned long)desc_p->dmamac_addr,
306 (unsigned long)desc_p->dmamac_addr + length);
308 #if defined(CONFIG_DW_ALTDESCRIPTOR)
309 desc_p->txrx_status |= DESC_TXSTS_TXFIRST | DESC_TXSTS_TXLAST;
310 desc_p->dmamac_cntl |= (length << DESC_TXCTRL_SIZE1SHFT) & \
311 DESC_TXCTRL_SIZE1MASK;
313 desc_p->txrx_status &= ~(DESC_TXSTS_MSK);
314 desc_p->txrx_status |= DESC_TXSTS_OWNBYDMA;
316 desc_p->dmamac_cntl |= ((length << DESC_TXCTRL_SIZE1SHFT) & \
317 DESC_TXCTRL_SIZE1MASK) | DESC_TXCTRL_TXLAST | \
320 desc_p->txrx_status = DESC_TXSTS_OWNBYDMA;
323 /* Flush modified buffer descriptor */
324 flush_dcache_range((unsigned long)desc_p,
325 (unsigned long)desc_p + sizeof(struct dmamacdescr));
327 /* Test the wrap-around condition. */
328 if (++desc_num >= CONFIG_TX_DESCR_NUM)
331 priv->tx_currdescnum = desc_num;
333 /* Start the transmission */
334 writel(POLL_DATA, &dma_p->txpolldemand);
339 static int dw_eth_recv(struct eth_device *dev)
341 struct dw_eth_dev *priv = dev->priv;
342 u32 status, desc_num = priv->rx_currdescnum;
343 struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num];
346 /* Invalidate entire buffer descriptor */
347 invalidate_dcache_range((unsigned long)desc_p,
348 (unsigned long)desc_p +
349 sizeof(struct dmamacdescr));
351 status = desc_p->txrx_status;
353 /* Check if the owner is the CPU */
354 if (!(status & DESC_RXSTS_OWNBYDMA)) {
356 length = (status & DESC_RXSTS_FRMLENMSK) >> \
357 DESC_RXSTS_FRMLENSHFT;
359 /* Invalidate received data */
360 invalidate_dcache_range((unsigned long)desc_p->dmamac_addr,
361 (unsigned long)desc_p->dmamac_addr +
362 roundup(length, ARCH_DMA_MINALIGN));
364 NetReceive(desc_p->dmamac_addr, length);
367 * Make the current descriptor valid again and go to
370 desc_p->txrx_status |= DESC_RXSTS_OWNBYDMA;
372 /* Flush only status field - others weren't changed */
373 flush_dcache_range((unsigned long)&desc_p->txrx_status,
374 (unsigned long)&desc_p->txrx_status +
375 sizeof(desc_p->txrx_status));
377 /* Test the wrap-around condition. */
378 if (++desc_num >= CONFIG_RX_DESCR_NUM)
382 priv->rx_currdescnum = desc_num;
387 static int dw_phy_init(struct eth_device *dev)
389 struct dw_eth_dev *priv = dev->priv;
390 struct phy_device *phydev;
391 int mask = 0xffffffff;
393 #ifdef CONFIG_PHY_ADDR
394 mask = 1 << CONFIG_PHY_ADDR;
397 phydev = phy_find_by_mask(priv->bus, mask, priv->interface);
401 phy_connect_dev(phydev, dev);
403 phydev->supported &= PHY_GBIT_FEATURES;
404 phydev->advertising = phydev->supported;
406 priv->phydev = phydev;
412 int designware_initialize(ulong base_addr, u32 interface)
414 struct eth_device *dev;
415 struct dw_eth_dev *priv;
417 dev = (struct eth_device *) malloc(sizeof(struct eth_device));
422 * Since the priv structure contains the descriptors which need a strict
423 * buswidth alignment, memalign is used to allocate memory
425 priv = (struct dw_eth_dev *) memalign(ARCH_DMA_MINALIGN,
426 sizeof(struct dw_eth_dev));
432 memset(dev, 0, sizeof(struct eth_device));
433 memset(priv, 0, sizeof(struct dw_eth_dev));
435 sprintf(dev->name, "dwmac.%lx", base_addr);
436 dev->iobase = (int)base_addr;
440 priv->mac_regs_p = (struct eth_mac_regs *)base_addr;
441 priv->dma_regs_p = (struct eth_dma_regs *)(base_addr +
444 dev->init = dw_eth_init;
445 dev->send = dw_eth_send;
446 dev->recv = dw_eth_recv;
447 dev->halt = dw_eth_halt;
448 dev->write_hwaddr = dw_write_hwaddr;
452 priv->interface = interface;
454 dw_mdio_init(dev->name, priv->mac_regs_p);
455 priv->bus = miiphy_get_dev_by_name(dev->name);
457 return dw_phy_init(dev);