3 * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
5 * SPDX-License-Identifier: GPL-2.0+
9 * Designware ethernet IP driver for U-Boot
19 #include <linux/compiler.h>
20 #include <linux/err.h>
21 #include <linux/kernel.h>
23 #include <power/regulator.h>
24 #include "designware.h"
26 DECLARE_GLOBAL_DATA_PTR;
28 static int dw_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
31 struct dw_eth_dev *priv = dev_get_priv((struct udevice *)bus->priv);
32 struct eth_mac_regs *mac_p = priv->mac_regs_p;
34 struct eth_mac_regs *mac_p = bus->priv;
38 int timeout = CONFIG_MDIO_TIMEOUT;
40 miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) |
41 ((reg << MIIREGSHIFT) & MII_REGMSK);
43 writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr);
46 while (get_timer(start) < timeout) {
47 if (!(readl(&mac_p->miiaddr) & MII_BUSY))
48 return readl(&mac_p->miidata);
55 static int dw_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
59 struct dw_eth_dev *priv = dev_get_priv((struct udevice *)bus->priv);
60 struct eth_mac_regs *mac_p = priv->mac_regs_p;
62 struct eth_mac_regs *mac_p = bus->priv;
66 int ret = -ETIMEDOUT, timeout = CONFIG_MDIO_TIMEOUT;
68 writel(val, &mac_p->miidata);
69 miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) |
70 ((reg << MIIREGSHIFT) & MII_REGMSK) | MII_WRITE;
72 writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr);
75 while (get_timer(start) < timeout) {
76 if (!(readl(&mac_p->miiaddr) & MII_BUSY)) {
86 #if defined(CONFIG_DM_ETH) && defined(CONFIG_DM_GPIO)
87 static int dw_mdio_reset(struct mii_dev *bus)
89 struct udevice *dev = bus->priv;
90 struct dw_eth_dev *priv = dev_get_priv(dev);
91 struct dw_eth_pdata *pdata = dev_get_platdata(dev);
94 if (!dm_gpio_is_valid(&priv->reset_gpio))
98 ret = dm_gpio_set_value(&priv->reset_gpio, 0);
102 udelay(pdata->reset_delays[0]);
104 ret = dm_gpio_set_value(&priv->reset_gpio, 1);
108 udelay(pdata->reset_delays[1]);
110 ret = dm_gpio_set_value(&priv->reset_gpio, 0);
114 udelay(pdata->reset_delays[2]);
120 static int dw_mdio_init(const char *name, void *priv)
122 struct mii_dev *bus = mdio_alloc();
125 printf("Failed to allocate MDIO bus\n");
129 bus->read = dw_mdio_read;
130 bus->write = dw_mdio_write;
131 snprintf(bus->name, sizeof(bus->name), "%s", name);
132 #if defined(CONFIG_DM_ETH) && defined(CONFIG_DM_GPIO)
133 bus->reset = dw_mdio_reset;
138 return mdio_register(bus);
141 static void tx_descs_init(struct dw_eth_dev *priv)
143 struct eth_dma_regs *dma_p = priv->dma_regs_p;
144 struct dmamacdescr *desc_table_p = &priv->tx_mac_descrtable[0];
145 char *txbuffs = &priv->txbuffs[0];
146 struct dmamacdescr *desc_p;
149 for (idx = 0; idx < CONFIG_TX_DESCR_NUM; idx++) {
150 desc_p = &desc_table_p[idx];
151 desc_p->dmamac_addr = (ulong)&txbuffs[idx * CONFIG_ETH_BUFSIZE];
152 desc_p->dmamac_next = (ulong)&desc_table_p[idx + 1];
154 #if defined(CONFIG_DW_ALTDESCRIPTOR)
155 desc_p->txrx_status &= ~(DESC_TXSTS_TXINT | DESC_TXSTS_TXLAST |
156 DESC_TXSTS_TXFIRST | DESC_TXSTS_TXCRCDIS |
157 DESC_TXSTS_TXCHECKINSCTRL |
158 DESC_TXSTS_TXRINGEND | DESC_TXSTS_TXPADDIS);
160 desc_p->txrx_status |= DESC_TXSTS_TXCHAIN;
161 desc_p->dmamac_cntl = 0;
162 desc_p->txrx_status &= ~(DESC_TXSTS_MSK | DESC_TXSTS_OWNBYDMA);
164 desc_p->dmamac_cntl = DESC_TXCTRL_TXCHAIN;
165 desc_p->txrx_status = 0;
169 /* Correcting the last pointer of the chain */
170 desc_p->dmamac_next = (ulong)&desc_table_p[0];
172 /* Flush all Tx buffer descriptors at once */
173 flush_dcache_range((ulong)priv->tx_mac_descrtable,
174 (ulong)priv->tx_mac_descrtable +
175 sizeof(priv->tx_mac_descrtable));
177 writel((ulong)&desc_table_p[0], &dma_p->txdesclistaddr);
178 priv->tx_currdescnum = 0;
181 static void rx_descs_init(struct dw_eth_dev *priv)
183 struct eth_dma_regs *dma_p = priv->dma_regs_p;
184 struct dmamacdescr *desc_table_p = &priv->rx_mac_descrtable[0];
185 char *rxbuffs = &priv->rxbuffs[0];
186 struct dmamacdescr *desc_p;
189 /* Before passing buffers to GMAC we need to make sure zeros
190 * written there right after "priv" structure allocation were
192 * Otherwise there's a chance to get some of them flushed in RAM when
193 * GMAC is already pushing data to RAM via DMA. This way incoming from
194 * GMAC data will be corrupted. */
195 flush_dcache_range((ulong)rxbuffs, (ulong)rxbuffs + RX_TOTAL_BUFSIZE);
197 for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) {
198 desc_p = &desc_table_p[idx];
199 desc_p->dmamac_addr = (ulong)&rxbuffs[idx * CONFIG_ETH_BUFSIZE];
200 desc_p->dmamac_next = (ulong)&desc_table_p[idx + 1];
202 desc_p->dmamac_cntl =
203 (MAC_MAX_FRAME_SZ & DESC_RXCTRL_SIZE1MASK) |
206 desc_p->txrx_status = DESC_RXSTS_OWNBYDMA;
209 /* Correcting the last pointer of the chain */
210 desc_p->dmamac_next = (ulong)&desc_table_p[0];
212 /* Flush all Rx buffer descriptors at once */
213 flush_dcache_range((ulong)priv->rx_mac_descrtable,
214 (ulong)priv->rx_mac_descrtable +
215 sizeof(priv->rx_mac_descrtable));
217 writel((ulong)&desc_table_p[0], &dma_p->rxdesclistaddr);
218 priv->rx_currdescnum = 0;
221 static int _dw_write_hwaddr(struct dw_eth_dev *priv, u8 *mac_id)
223 struct eth_mac_regs *mac_p = priv->mac_regs_p;
224 u32 macid_lo, macid_hi;
226 macid_lo = mac_id[0] + (mac_id[1] << 8) + (mac_id[2] << 16) +
228 macid_hi = mac_id[4] + (mac_id[5] << 8);
230 writel(macid_hi, &mac_p->macaddr0hi);
231 writel(macid_lo, &mac_p->macaddr0lo);
236 static int dw_adjust_link(struct dw_eth_dev *priv, struct eth_mac_regs *mac_p,
237 struct phy_device *phydev)
239 u32 conf = readl(&mac_p->conf) | FRAMEBURSTENABLE | DISABLERXOWN;
242 printf("%s: No link.\n", phydev->dev->name);
246 if (phydev->speed != 1000)
247 conf |= MII_PORTSELECT;
249 conf &= ~MII_PORTSELECT;
251 if (phydev->speed == 100)
255 conf |= FULLDPLXMODE;
257 writel(conf, &mac_p->conf);
259 printf("Speed: %d, %s duplex%s\n", phydev->speed,
260 (phydev->duplex) ? "full" : "half",
261 (phydev->port == PORT_FIBRE) ? ", fiber mode" : "");
266 static void _dw_eth_halt(struct dw_eth_dev *priv)
268 struct eth_mac_regs *mac_p = priv->mac_regs_p;
269 struct eth_dma_regs *dma_p = priv->dma_regs_p;
271 writel(readl(&mac_p->conf) & ~(RXENABLE | TXENABLE), &mac_p->conf);
272 writel(readl(&dma_p->opmode) & ~(RXSTART | TXSTART), &dma_p->opmode);
274 phy_shutdown(priv->phydev);
277 int designware_eth_init(struct dw_eth_dev *priv, u8 *enetaddr)
279 struct eth_mac_regs *mac_p = priv->mac_regs_p;
280 struct eth_dma_regs *dma_p = priv->dma_regs_p;
284 writel(readl(&dma_p->busmode) | DMAMAC_SRST, &dma_p->busmode);
286 start = get_timer(0);
287 while (readl(&dma_p->busmode) & DMAMAC_SRST) {
288 if (get_timer(start) >= CONFIG_MACRESET_TIMEOUT) {
289 printf("DMA reset timeout\n");
297 * Soft reset above clears HW address registers.
298 * So we have to set it here once again.
300 _dw_write_hwaddr(priv, enetaddr);
305 writel(FIXEDBURST | PRIORXTX_41 | DMA_PBL, &dma_p->busmode);
307 #ifndef CONFIG_DW_MAC_FORCE_THRESHOLD_MODE
308 writel(readl(&dma_p->opmode) | FLUSHTXFIFO | STOREFORWARD,
311 writel(readl(&dma_p->opmode) | FLUSHTXFIFO,
315 writel(readl(&dma_p->opmode) | RXSTART | TXSTART, &dma_p->opmode);
317 #ifdef CONFIG_DW_AXI_BURST_LEN
318 writel((CONFIG_DW_AXI_BURST_LEN & 0x1FF >> 1), &dma_p->axibus);
321 /* Start up the PHY */
322 ret = phy_startup(priv->phydev);
324 printf("Could not initialize PHY %s\n",
325 priv->phydev->dev->name);
329 ret = dw_adjust_link(priv, mac_p, priv->phydev);
336 int designware_eth_enable(struct dw_eth_dev *priv)
338 struct eth_mac_regs *mac_p = priv->mac_regs_p;
340 if (!priv->phydev->link)
343 writel(readl(&mac_p->conf) | RXENABLE | TXENABLE, &mac_p->conf);
350 static int _dw_eth_send(struct dw_eth_dev *priv, void *packet, int length)
352 struct eth_dma_regs *dma_p = priv->dma_regs_p;
353 u32 desc_num = priv->tx_currdescnum;
354 struct dmamacdescr *desc_p = &priv->tx_mac_descrtable[desc_num];
355 ulong desc_start = (ulong)desc_p;
356 ulong desc_end = desc_start +
357 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
358 ulong data_start = desc_p->dmamac_addr;
359 ulong data_end = data_start + roundup(length, ARCH_DMA_MINALIGN);
361 * Strictly we only need to invalidate the "txrx_status" field
362 * for the following check, but on some platforms we cannot
363 * invalidate only 4 bytes, so we flush the entire descriptor,
364 * which is 16 bytes in total. This is safe because the
365 * individual descriptors in the array are each aligned to
366 * ARCH_DMA_MINALIGN and padded appropriately.
368 invalidate_dcache_range(desc_start, desc_end);
370 /* Check if the descriptor is owned by CPU */
371 if (desc_p->txrx_status & DESC_TXSTS_OWNBYDMA) {
372 printf("CPU not owner of tx frame\n");
376 length = max(length, ETH_ZLEN);
378 memcpy((void *)data_start, packet, length);
380 /* Flush data to be sent */
381 flush_dcache_range(data_start, data_end);
383 #if defined(CONFIG_DW_ALTDESCRIPTOR)
384 desc_p->txrx_status |= DESC_TXSTS_TXFIRST | DESC_TXSTS_TXLAST;
385 desc_p->dmamac_cntl |= (length << DESC_TXCTRL_SIZE1SHFT) &
386 DESC_TXCTRL_SIZE1MASK;
388 desc_p->txrx_status &= ~(DESC_TXSTS_MSK);
389 desc_p->txrx_status |= DESC_TXSTS_OWNBYDMA;
391 desc_p->dmamac_cntl |= ((length << DESC_TXCTRL_SIZE1SHFT) &
392 DESC_TXCTRL_SIZE1MASK) | DESC_TXCTRL_TXLAST |
395 desc_p->txrx_status = DESC_TXSTS_OWNBYDMA;
398 /* Flush modified buffer descriptor */
399 flush_dcache_range(desc_start, desc_end);
401 /* Test the wrap-around condition. */
402 if (++desc_num >= CONFIG_TX_DESCR_NUM)
405 priv->tx_currdescnum = desc_num;
407 /* Start the transmission */
408 writel(POLL_DATA, &dma_p->txpolldemand);
413 static int _dw_eth_recv(struct dw_eth_dev *priv, uchar **packetp)
415 u32 status, desc_num = priv->rx_currdescnum;
416 struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num];
417 int length = -EAGAIN;
418 ulong desc_start = (ulong)desc_p;
419 ulong desc_end = desc_start +
420 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
421 ulong data_start = desc_p->dmamac_addr;
424 /* Invalidate entire buffer descriptor */
425 invalidate_dcache_range(desc_start, desc_end);
427 status = desc_p->txrx_status;
429 /* Check if the owner is the CPU */
430 if (!(status & DESC_RXSTS_OWNBYDMA)) {
432 length = (status & DESC_RXSTS_FRMLENMSK) >>
433 DESC_RXSTS_FRMLENSHFT;
435 /* Invalidate received data */
436 data_end = data_start + roundup(length, ARCH_DMA_MINALIGN);
437 invalidate_dcache_range(data_start, data_end);
438 *packetp = (uchar *)(ulong)desc_p->dmamac_addr;
444 static int _dw_free_pkt(struct dw_eth_dev *priv)
446 u32 desc_num = priv->rx_currdescnum;
447 struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num];
448 ulong desc_start = (ulong)desc_p;
449 ulong desc_end = desc_start +
450 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
453 * Make the current descriptor valid again and go to
456 desc_p->txrx_status |= DESC_RXSTS_OWNBYDMA;
458 /* Flush only status field - others weren't changed */
459 flush_dcache_range(desc_start, desc_end);
461 /* Test the wrap-around condition. */
462 if (++desc_num >= CONFIG_RX_DESCR_NUM)
464 priv->rx_currdescnum = desc_num;
469 static int dw_phy_init(struct dw_eth_dev *priv, void *dev)
471 struct phy_device *phydev;
472 int mask = 0xffffffff, ret;
474 #ifdef CONFIG_PHY_ADDR
475 mask = 1 << CONFIG_PHY_ADDR;
478 phydev = phy_find_by_mask(priv->bus, mask, priv->interface);
482 phy_connect_dev(phydev, dev);
484 phydev->supported &= PHY_GBIT_FEATURES;
485 if (priv->max_speed) {
486 ret = phy_set_supported(phydev, priv->max_speed);
490 phydev->advertising = phydev->supported;
492 priv->phydev = phydev;
498 #ifndef CONFIG_DM_ETH
499 static int dw_eth_init(struct eth_device *dev, bd_t *bis)
503 ret = designware_eth_init(dev->priv, dev->enetaddr);
505 ret = designware_eth_enable(dev->priv);
510 static int dw_eth_send(struct eth_device *dev, void *packet, int length)
512 return _dw_eth_send(dev->priv, packet, length);
515 static int dw_eth_recv(struct eth_device *dev)
520 length = _dw_eth_recv(dev->priv, &packet);
521 if (length == -EAGAIN)
523 net_process_received_packet(packet, length);
525 _dw_free_pkt(dev->priv);
530 static void dw_eth_halt(struct eth_device *dev)
532 return _dw_eth_halt(dev->priv);
535 static int dw_write_hwaddr(struct eth_device *dev)
537 return _dw_write_hwaddr(dev->priv, dev->enetaddr);
540 int designware_initialize(ulong base_addr, u32 interface)
542 struct eth_device *dev;
543 struct dw_eth_dev *priv;
545 dev = (struct eth_device *) malloc(sizeof(struct eth_device));
550 * Since the priv structure contains the descriptors which need a strict
551 * buswidth alignment, memalign is used to allocate memory
553 priv = (struct dw_eth_dev *) memalign(ARCH_DMA_MINALIGN,
554 sizeof(struct dw_eth_dev));
560 if ((phys_addr_t)priv + sizeof(*priv) > (1ULL << 32)) {
561 printf("designware: buffers are outside DMA memory\n");
565 memset(dev, 0, sizeof(struct eth_device));
566 memset(priv, 0, sizeof(struct dw_eth_dev));
568 sprintf(dev->name, "dwmac.%lx", base_addr);
569 dev->iobase = (int)base_addr;
573 priv->mac_regs_p = (struct eth_mac_regs *)base_addr;
574 priv->dma_regs_p = (struct eth_dma_regs *)(base_addr +
577 dev->init = dw_eth_init;
578 dev->send = dw_eth_send;
579 dev->recv = dw_eth_recv;
580 dev->halt = dw_eth_halt;
581 dev->write_hwaddr = dw_write_hwaddr;
585 priv->interface = interface;
587 dw_mdio_init(dev->name, priv->mac_regs_p);
588 priv->bus = miiphy_get_dev_by_name(dev->name);
590 return dw_phy_init(priv, dev);
595 static int designware_eth_start(struct udevice *dev)
597 struct eth_pdata *pdata = dev_get_platdata(dev);
598 struct dw_eth_dev *priv = dev_get_priv(dev);
601 ret = designware_eth_init(priv, pdata->enetaddr);
604 ret = designware_eth_enable(priv);
611 int designware_eth_send(struct udevice *dev, void *packet, int length)
613 struct dw_eth_dev *priv = dev_get_priv(dev);
615 return _dw_eth_send(priv, packet, length);
618 int designware_eth_recv(struct udevice *dev, int flags, uchar **packetp)
620 struct dw_eth_dev *priv = dev_get_priv(dev);
622 return _dw_eth_recv(priv, packetp);
625 int designware_eth_free_pkt(struct udevice *dev, uchar *packet, int length)
627 struct dw_eth_dev *priv = dev_get_priv(dev);
629 return _dw_free_pkt(priv);
632 void designware_eth_stop(struct udevice *dev)
634 struct dw_eth_dev *priv = dev_get_priv(dev);
636 return _dw_eth_halt(priv);
639 int designware_eth_write_hwaddr(struct udevice *dev)
641 struct eth_pdata *pdata = dev_get_platdata(dev);
642 struct dw_eth_dev *priv = dev_get_priv(dev);
644 return _dw_write_hwaddr(priv, pdata->enetaddr);
647 static int designware_eth_bind(struct udevice *dev)
650 static int num_cards;
653 /* Create a unique device name for PCI type devices */
654 if (device_is_on_pci_bus(dev)) {
655 sprintf(name, "eth_designware#%u", num_cards++);
656 device_set_name(dev, name);
663 int designware_eth_probe(struct udevice *dev)
665 struct eth_pdata *pdata = dev_get_platdata(dev);
666 struct dw_eth_dev *priv = dev_get_priv(dev);
667 u32 iobase = pdata->iobase;
671 int i, err, clock_nb;
673 priv->clock_count = 0;
674 clock_nb = dev_count_phandle_with_args(dev, "clocks", "#clock-cells");
676 priv->clocks = devm_kcalloc(dev, clock_nb, sizeof(struct clk),
681 for (i = 0; i < clock_nb; i++) {
682 err = clk_get_by_index(dev, i, &priv->clocks[i]);
686 err = clk_enable(&priv->clocks[i]);
688 pr_err("failed to enable clock %d\n", i);
689 clk_free(&priv->clocks[i]);
694 } else if (clock_nb != -ENOENT) {
695 pr_err("failed to get clock phandle(%d)\n", clock_nb);
700 #if defined(CONFIG_DM_REGULATOR)
701 struct udevice *phy_supply;
703 ret = device_get_supply_regulator(dev, "phy-supply",
706 debug("%s: No phy supply\n", dev->name);
708 ret = regulator_set_enable(phy_supply, true);
710 puts("Error enabling phy supply\n");
718 * If we are on PCI bus, either directly attached to a PCI root port,
719 * or via a PCI bridge, fill in platdata before we probe the hardware.
721 if (device_is_on_pci_bus(dev)) {
722 dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0, &iobase);
723 iobase &= PCI_BASE_ADDRESS_MEM_MASK;
724 iobase = dm_pci_mem_to_phys(dev, iobase);
726 pdata->iobase = iobase;
727 pdata->phy_interface = PHY_INTERFACE_MODE_RMII;
731 debug("%s, iobase=%x, priv=%p\n", __func__, iobase, priv);
733 priv->mac_regs_p = (struct eth_mac_regs *)ioaddr;
734 priv->dma_regs_p = (struct eth_dma_regs *)(ioaddr + DW_DMA_BASE_OFFSET);
735 priv->interface = pdata->phy_interface;
736 priv->max_speed = pdata->max_speed;
738 dw_mdio_init(dev->name, dev);
739 priv->bus = miiphy_get_dev_by_name(dev->name);
741 ret = dw_phy_init(priv, dev);
742 debug("%s, ret=%d\n", __func__, ret);
748 ret = clk_release_all(priv->clocks, priv->clock_count);
750 pr_err("failed to disable all clocks\n");
756 static int designware_eth_remove(struct udevice *dev)
758 struct dw_eth_dev *priv = dev_get_priv(dev);
761 mdio_unregister(priv->bus);
762 mdio_free(priv->bus);
765 return clk_release_all(priv->clocks, priv->clock_count);
771 const struct eth_ops designware_eth_ops = {
772 .start = designware_eth_start,
773 .send = designware_eth_send,
774 .recv = designware_eth_recv,
775 .free_pkt = designware_eth_free_pkt,
776 .stop = designware_eth_stop,
777 .write_hwaddr = designware_eth_write_hwaddr,
780 int designware_eth_ofdata_to_platdata(struct udevice *dev)
782 struct dw_eth_pdata *dw_pdata = dev_get_platdata(dev);
783 #ifdef CONFIG_DM_GPIO
784 struct dw_eth_dev *priv = dev_get_priv(dev);
786 struct eth_pdata *pdata = &dw_pdata->eth_pdata;
787 const char *phy_mode;
788 #ifdef CONFIG_DM_GPIO
789 int reset_flags = GPIOD_IS_OUT;
793 pdata->iobase = dev_read_addr(dev);
794 pdata->phy_interface = -1;
795 phy_mode = dev_read_string(dev, "phy-mode");
797 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
798 if (pdata->phy_interface == -1) {
799 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
803 pdata->max_speed = dev_read_u32_default(dev, "max-speed", 0);
805 #ifdef CONFIG_DM_GPIO
806 if (dev_read_bool(dev, "snps,reset-active-low"))
807 reset_flags |= GPIOD_ACTIVE_LOW;
809 ret = gpio_request_by_name(dev, "snps,reset-gpio", 0,
810 &priv->reset_gpio, reset_flags);
812 ret = dev_read_u32_array(dev, "snps,reset-delays-us",
813 dw_pdata->reset_delays, 3);
814 } else if (ret == -ENOENT) {
822 static const struct udevice_id designware_eth_ids[] = {
823 { .compatible = "allwinner,sun7i-a20-gmac" },
824 { .compatible = "altr,socfpga-stmmac" },
825 { .compatible = "amlogic,meson6-dwmac" },
826 { .compatible = "amlogic,meson-gx-dwmac" },
827 { .compatible = "st,stm32-dwmac" },
831 U_BOOT_DRIVER(eth_designware) = {
832 .name = "eth_designware",
834 .of_match = designware_eth_ids,
835 .ofdata_to_platdata = designware_eth_ofdata_to_platdata,
836 .bind = designware_eth_bind,
837 .probe = designware_eth_probe,
838 .remove = designware_eth_remove,
839 .ops = &designware_eth_ops,
840 .priv_auto_alloc_size = sizeof(struct dw_eth_dev),
841 .platdata_auto_alloc_size = sizeof(struct dw_eth_pdata),
842 .flags = DM_FLAG_ALLOC_PRIV_DMA,
845 static struct pci_device_id supported[] = {
846 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_EMAC) },
850 U_BOOT_PCI_DEVICE(eth_designware, supported);