1 // SPDX-License-Identifier: GPL-2.0+
16 #define PCI_CFDA_PSM 0x43
18 #define CFRV_RN 0x000000f0 /* Revision Number */
20 #define WAKEUP 0x00 /* Power Saving Wakeup */
21 #define SLEEP 0x80 /* Power Saving Sleep Mode */
23 #define DC2114x_BRK 0x0020 /* CFRV break between DC21142 & DC21143 */
25 /* Ethernet chip registers. */
26 #define DE4X5_BMR 0x000 /* Bus Mode Register */
27 #define DE4X5_TPD 0x008 /* Transmit Poll Demand Reg */
28 #define DE4X5_RRBA 0x018 /* RX Ring Base Address Reg */
29 #define DE4X5_TRBA 0x020 /* TX Ring Base Address Reg */
30 #define DE4X5_STS 0x028 /* Status Register */
31 #define DE4X5_OMR 0x030 /* Operation Mode Register */
32 #define DE4X5_SICR 0x068 /* SIA Connectivity Register */
33 #define DE4X5_APROM 0x048 /* Ethernet Address PROM */
36 #define BMR_SWR 0x00000001 /* Software Reset */
37 #define STS_TS 0x00700000 /* Transmit Process State */
38 #define STS_RS 0x000e0000 /* Receive Process State */
39 #define OMR_ST 0x00002000 /* Start/Stop Transmission Command */
40 #define OMR_SR 0x00000002 /* Start/Stop Receive */
41 #define OMR_PS 0x00040000 /* Port Select */
42 #define OMR_SDP 0x02000000 /* SD Polarity - MUST BE ASSERTED */
43 #define OMR_PM 0x00000080 /* Pass All Multicast */
45 /* Descriptor bits. */
46 #define R_OWN 0x80000000 /* Own Bit */
47 #define RD_RER 0x02000000 /* Receive End Of Ring */
48 #define RD_LS 0x00000100 /* Last Descriptor */
49 #define RD_ES 0x00008000 /* Error Summary */
50 #define TD_TER 0x02000000 /* Transmit End Of Ring */
51 #define T_OWN 0x80000000 /* Own Bit */
52 #define TD_LS 0x40000000 /* Last Segment */
53 #define TD_FS 0x20000000 /* First Segment */
54 #define TD_ES 0x00008000 /* Error Summary */
55 #define TD_SET 0x08000000 /* Setup Packet */
57 /* The EEPROM commands include the alway-set leading bit. */
58 #define SROM_WRITE_CMD 5
59 #define SROM_READ_CMD 6
60 #define SROM_ERASE_CMD 7
62 #define SROM_HWADD 0x0014 /* Hardware Address offset in SROM */
63 #define SROM_RD 0x00004000 /* Read from Boot ROM */
64 #define EE_DATA_WRITE 0x04 /* EEPROM chip data in. */
65 #define EE_WRITE_0 0x4801
66 #define EE_WRITE_1 0x4805
67 #define EE_DATA_READ 0x08 /* EEPROM chip data out. */
68 #define SROM_SR 0x00000800 /* Select Serial ROM when set */
70 #define DT_IN 0x00000004 /* Serial Data In */
71 #define DT_CLK 0x00000002 /* Serial ROM Clock */
72 #define DT_CS 0x00000001 /* Serial ROM Chip Select */
76 #if defined(CONFIG_E500)
77 #define phys_to_bus(a) (a)
79 #define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a)
82 #define NUM_RX_DESC PKTBUFSRX
83 #define NUM_TX_DESC 1 /* Number of TX descriptors */
84 #define RX_BUFF_SZ PKTSIZE_ALIGN
86 #define TOUT_LOOP 1000000
88 #define SETUP_FRAME_LEN 192
97 /* RX and TX descriptor ring */
98 static struct de4x5_desc rx_ring[NUM_RX_DESC] __aligned(32);
99 static struct de4x5_desc tx_ring[NUM_TX_DESC] __aligned(32);
100 static int rx_new; /* RX descriptor ring pointer */
101 static int tx_new; /* TX descriptor ring pointer */
103 static char rx_ring_size;
104 static char tx_ring_size;
106 static u32 dc2114x_inl(struct eth_device *dev, u32 addr)
108 return le32_to_cpu(*(volatile u32 *)(addr + dev->iobase));
111 static void dc2114x_outl(struct eth_device *dev, u32 command, u32 addr)
113 *(volatile u32 *)(addr + dev->iobase) = cpu_to_le32(command);
116 static void reset_de4x5(struct eth_device *dev)
120 i = dc2114x_inl(dev, DE4X5_BMR);
122 dc2114x_outl(dev, i | BMR_SWR, DE4X5_BMR);
124 dc2114x_outl(dev, i, DE4X5_BMR);
127 for (i = 0; i < 5; i++) {
128 dc2114x_inl(dev, DE4X5_BMR);
135 static void start_de4x5(struct eth_device *dev)
139 omr = dc2114x_inl(dev, DE4X5_OMR);
140 omr |= OMR_ST | OMR_SR;
141 dc2114x_outl(dev, omr, DE4X5_OMR); /* Enable the TX and/or RX */
144 static void stop_de4x5(struct eth_device *dev)
148 omr = dc2114x_inl(dev, DE4X5_OMR);
149 omr &= ~(OMR_ST | OMR_SR);
150 dc2114x_outl(dev, omr, DE4X5_OMR); /* Disable the TX and/or RX */
153 /* SROM Read and write routines. */
154 static void sendto_srom(struct eth_device *dev, u_int command, u_long addr)
156 dc2114x_outl(dev, command, addr);
160 static int getfrom_srom(struct eth_device *dev, u_long addr)
162 u32 tmp = dc2114x_inl(dev, addr);
168 /* Note: this routine returns extra data bits for size detection. */
169 static int do_read_eeprom(struct eth_device *dev, u_long ioaddr, int location,
172 int read_cmd = location | (SROM_READ_CMD << addr_len);
173 unsigned int retval = 0;
176 sendto_srom(dev, SROM_RD | SROM_SR, ioaddr);
177 sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr);
180 printf(" EEPROM read at %d ", location);
183 /* Shift the read command bits out. */
184 for (i = 4 + addr_len; i >= 0; i--) {
185 short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
187 sendto_srom(dev, SROM_RD | SROM_SR | DT_CS | dataval,
190 sendto_srom(dev, SROM_RD | SROM_SR | DT_CS | dataval | DT_CLK,
194 printf("%X", getfrom_srom(dev, ioaddr) & 15);
196 retval = (retval << 1) |
197 !!(getfrom_srom(dev, ioaddr) & EE_DATA_READ);
200 sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr);
203 printf(" :%X:", getfrom_srom(dev, ioaddr) & 15);
206 for (i = 16; i > 0; i--) {
207 sendto_srom(dev, SROM_RD | SROM_SR | DT_CS | DT_CLK, ioaddr);
210 printf("%X", getfrom_srom(dev, ioaddr) & 15);
212 retval = (retval << 1) |
213 !!(getfrom_srom(dev, ioaddr) & EE_DATA_READ);
214 sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr);
218 /* Terminate the EEPROM access. */
219 sendto_srom(dev, SROM_RD | SROM_SR, ioaddr);
222 printf(" EEPROM value at %d is %5.5x.\n", location, retval);
229 * This executes a generic EEPROM command, typically a write or write
230 * enable. It returns the data output from the EEPROM, and thus may
231 * also be used for reads.
233 static int do_eeprom_cmd(struct eth_device *dev, u_long ioaddr, int cmd,
236 unsigned int retval = 0;
239 printf(" EEPROM op 0x%x: ", cmd);
242 sendto_srom(dev, SROM_RD | SROM_SR | DT_CS | DT_CLK, ioaddr);
244 /* Shift the command bits out. */
246 short dataval = (cmd & BIT(cmd_len)) ? EE_WRITE_1 : EE_WRITE_0;
248 sendto_srom(dev, dataval, ioaddr);
252 printf("%X", getfrom_srom(dev, ioaddr) & 15);
255 sendto_srom(dev, dataval | DT_CLK, ioaddr);
257 retval = (retval << 1) |
258 !!(getfrom_srom(dev, ioaddr) & EE_DATA_READ);
259 } while (--cmd_len >= 0);
261 sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr);
263 /* Terminate the EEPROM access. */
264 sendto_srom(dev, SROM_RD | SROM_SR, ioaddr);
267 printf(" EEPROM result is 0x%5.5x.\n", retval);
273 static int read_srom(struct eth_device *dev, u_long ioaddr, int index)
277 ee_addr_size = (do_read_eeprom(dev, ioaddr, 0xff, 8) & BIT(18)) ? 8 : 6;
279 return do_eeprom_cmd(dev, ioaddr, 0xffff |
280 (((SROM_READ_CMD << ee_addr_size) | index) << 16),
281 3 + ee_addr_size + 16);
285 static int write_srom(struct eth_device *dev, u_long ioaddr, int index,
288 unsigned short newval;
292 ee_addr_size = (do_read_eeprom(dev, ioaddr, 0xff, 8) & BIT(18)) ? 8 : 6;
294 udelay(10 * 1000); /* test-only */
297 printf("ee_addr_size=%d.\n", ee_addr_size);
298 printf("Writing new entry 0x%4.4x to offset %d.\n", new_value, index);
301 /* Enable programming modes. */
302 do_eeprom_cmd(dev, ioaddr, 0x4f << (ee_addr_size - 4),
305 /* Do the actual write. */
306 do_eeprom_cmd(dev, ioaddr, new_value |
307 (((SROM_WRITE_CMD << ee_addr_size) | index) << 16),
308 3 + ee_addr_size + 16);
310 /* Poll for write finished. */
311 sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr);
312 for (i = 0; i < 10000; i++) { /* Typical 2000 ticks */
313 if (getfrom_srom(dev, ioaddr) & EE_DATA_READ)
318 printf(" Write finished after %d ticks.\n", i);
321 /* Disable programming. */
322 do_eeprom_cmd(dev, ioaddr, (0x40 << (ee_addr_size - 4)),
325 /* And read the result. */
326 newval = do_eeprom_cmd(dev, ioaddr,
327 (((SROM_READ_CMD << ee_addr_size) | index) << 16)
328 | 0xffff, 3 + ee_addr_size + 16);
330 printf(" New value at offset %d is %4.4x.\n", index, newval);
336 static void update_srom(struct eth_device *dev, bd_t *bis)
338 static unsigned short eeprom[0x40] = {
339 0x140b, 0x6610, 0x0000, 0x0000, /* 00 */
340 0x0000, 0x0000, 0x0000, 0x0000, /* 04 */
341 0x00a3, 0x0103, 0x0000, 0x0000, /* 08 */
342 0x0000, 0x1f00, 0x0000, 0x0000, /* 0c */
343 0x0108, 0x038d, 0x0000, 0x0000, /* 10 */
344 0xe078, 0x0001, 0x0040, 0x0018, /* 14 */
345 0x0000, 0x0000, 0x0000, 0x0000, /* 18 */
346 0x0000, 0x0000, 0x0000, 0x0000, /* 1c */
347 0x0000, 0x0000, 0x0000, 0x0000, /* 20 */
348 0x0000, 0x0000, 0x0000, 0x0000, /* 24 */
349 0x0000, 0x0000, 0x0000, 0x0000, /* 28 */
350 0x0000, 0x0000, 0x0000, 0x0000, /* 2c */
351 0x0000, 0x0000, 0x0000, 0x0000, /* 30 */
352 0x0000, 0x0000, 0x0000, 0x0000, /* 34 */
353 0x0000, 0x0000, 0x0000, 0x0000, /* 38 */
354 0x0000, 0x0000, 0x0000, 0x4e07, /* 3c */
359 /* Ethernet Addr... */
360 if (!eth_env_get_enetaddr("ethaddr", enetaddr))
363 eeprom[0x0a] = (enetaddr[1] << 8) | enetaddr[0];
364 eeprom[0x0b] = (enetaddr[3] << 8) | enetaddr[2];
365 eeprom[0x0c] = (enetaddr[5] << 8) | enetaddr[4];
367 for (i = 0; i < 0x40; i++)
368 write_srom(dev, DE4X5_APROM, i, eeprom[i]);
370 #endif /* UPDATE_SROM */
372 static void send_setup_frame(struct eth_device *dev, bd_t *bis)
374 char setup_frame[SETUP_FRAME_LEN];
375 char *pa = &setup_frame[0];
378 memset(pa, 0xff, SETUP_FRAME_LEN);
380 for (i = 0; i < ETH_ALEN; i++) {
381 *(pa + (i & 1)) = dev->enetaddr[i];
386 for (i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) {
390 printf("%s: tx error buffer not ready\n", dev->name);
394 tx_ring[tx_new].buf = cpu_to_le32(phys_to_bus((u32)&setup_frame[0]));
395 tx_ring[tx_new].des1 = cpu_to_le32(TD_TER | TD_SET | SETUP_FRAME_LEN);
396 tx_ring[tx_new].status = cpu_to_le32(T_OWN);
398 dc2114x_outl(dev, POLL_DEMAND, DE4X5_TPD);
400 for (i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) {
404 printf("%s: tx buffer not ready\n", dev->name);
408 if (le32_to_cpu(tx_ring[tx_new].status) != 0x7FFFFFFF) {
409 printf("TX error status2 = 0x%08X\n",
410 le32_to_cpu(tx_ring[tx_new].status));
413 tx_new = (tx_new + 1) % NUM_TX_DESC;
416 static int dc21x4x_send(struct eth_device *dev, void *packet, int length)
422 printf("%s: bad packet size: %d\n", dev->name, length);
426 for (i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) {
430 printf("%s: tx error buffer not ready\n", dev->name);
434 tx_ring[tx_new].buf = cpu_to_le32(phys_to_bus((u32)packet));
435 tx_ring[tx_new].des1 = cpu_to_le32(TD_TER | TD_LS | TD_FS | length);
436 tx_ring[tx_new].status = cpu_to_le32(T_OWN);
438 dc2114x_outl(dev, POLL_DEMAND, DE4X5_TPD);
440 for (i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) {
444 printf(".%s: tx buffer not ready\n", dev->name);
448 if (le32_to_cpu(tx_ring[tx_new].status) & TD_ES) {
449 tx_ring[tx_new].status = 0x0;
456 tx_new = (tx_new + 1) % NUM_TX_DESC;
460 static int dc21x4x_recv(struct eth_device *dev)
466 status = le32_to_cpu(rx_ring[rx_new].status);
471 if (status & RD_LS) {
472 /* Valid frame status. */
473 if (status & RD_ES) {
474 /* There was an error. */
475 printf("RX error status = 0x%08X\n", status);
477 /* A valid frame received. */
478 length = (le32_to_cpu(rx_ring[rx_new].status)
481 /* Pass the packet up to the protocol layers */
482 net_process_received_packet
483 (net_rx_packets[rx_new], length - 4);
487 * Change buffer ownership for this frame,
488 * back to the adapter.
490 rx_ring[rx_new].status = cpu_to_le32(R_OWN);
493 /* Update entry information. */
494 rx_new = (rx_new + 1) % rx_ring_size;
500 static int dc21x4x_init(struct eth_device *dev, bd_t *bis)
503 int devbusfn = (int)dev->priv;
505 /* Ensure we're not sleeping. */
506 pci_write_config_byte(devbusfn, PCI_CFDA_PSM, WAKEUP);
510 if (dc2114x_inl(dev, DE4X5_STS) & (STS_TS | STS_RS)) {
511 printf("Error: Cannot reset ethernet controller.\n");
515 dc2114x_outl(dev, OMR_SDP | OMR_PS | OMR_PM, DE4X5_OMR);
517 for (i = 0; i < NUM_RX_DESC; i++) {
518 rx_ring[i].status = cpu_to_le32(R_OWN);
519 rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ);
521 cpu_to_le32(phys_to_bus((u32)net_rx_packets[i]));
525 for (i = 0; i < NUM_TX_DESC; i++) {
526 tx_ring[i].status = 0;
532 rx_ring_size = NUM_RX_DESC;
533 tx_ring_size = NUM_TX_DESC;
535 /* Write the end of list marker to the descriptor lists. */
536 rx_ring[rx_ring_size - 1].des1 |= cpu_to_le32(RD_RER);
537 tx_ring[tx_ring_size - 1].des1 |= cpu_to_le32(TD_TER);
539 /* Tell the adapter where the TX/RX rings are located. */
540 dc2114x_outl(dev, phys_to_bus((u32)&rx_ring), DE4X5_RRBA);
541 dc2114x_outl(dev, phys_to_bus((u32)&tx_ring), DE4X5_TRBA);
548 send_setup_frame(dev, bis);
553 static void dc21x4x_halt(struct eth_device *dev)
555 int devbusfn = (int)dev->priv;
558 dc2114x_outl(dev, 0, DE4X5_SICR);
560 pci_write_config_byte(devbusfn, PCI_CFDA_PSM, SLEEP);
563 static void read_hw_addr(struct eth_device *dev, bd_t *bis)
565 u_short tmp, *p = (u_short *)(&dev->enetaddr[0]);
568 for (i = 0; i < (ETH_ALEN >> 1); i++) {
569 tmp = read_srom(dev, DE4X5_APROM, (SROM_HWADD >> 1) + i);
570 *p = le16_to_cpu(tmp);
574 if (!j || j == 0x2fffd) {
575 memset(dev->enetaddr, 0, ETH_ALEN);
576 debug("Warning: can't read HW address from SROM.\n");
578 update_srom(dev, bis);
583 static struct pci_device_id supported[] = {
584 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_FAST },
585 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142 },
589 int dc21x4x_initialize(bd_t *bis)
591 struct eth_device *dev;
592 unsigned short status;
601 devbusfn = pci_find_devices(supported, idx++);
605 /* Get the chip configuration revision register. */
606 pci_read_config_dword(devbusfn, PCI_REVISION_ID, &cfrv);
608 if ((cfrv & CFRV_RN) < DC2114x_BRK) {
609 printf("Error: The chip is not DC21143.\n");
613 pci_read_config_word(devbusfn, PCI_COMMAND, &status);
614 status |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
615 pci_write_config_word(devbusfn, PCI_COMMAND, status);
617 pci_read_config_word(devbusfn, PCI_COMMAND, &status);
618 if (!(status & PCI_COMMAND_MEMORY)) {
619 printf("Error: Can not enable MEMORY access.\n");
623 if (!(status & PCI_COMMAND_MASTER)) {
624 printf("Error: Can not enable Bus Mastering.\n");
628 /* Check the latency timer for values >= 0x60. */
629 pci_read_config_byte(devbusfn, PCI_LATENCY_TIMER, &timer);
632 pci_write_config_byte(devbusfn, PCI_LATENCY_TIMER,
636 /* read BAR for memory space access */
637 pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1, &iobase);
638 iobase &= PCI_BASE_ADDRESS_MEM_MASK;
639 debug("dc21x4x: DEC 21142 PCI Device @0x%x\n", iobase);
641 dev = (struct eth_device *)malloc(sizeof(*dev));
643 printf("Can not allocalte memory of dc21x4x\n");
647 memset(dev, 0, sizeof(*dev));
649 sprintf(dev->name, "dc21x4x#%d", card_number);
651 dev->iobase = pci_mem_to_phys(devbusfn, iobase);
652 dev->priv = (void *)devbusfn;
653 dev->init = dc21x4x_init;
654 dev->halt = dc21x4x_halt;
655 dev->send = dc21x4x_send;
656 dev->recv = dc21x4x_recv;
658 /* Ensure we're not sleeping. */
659 pci_write_config_byte(devbusfn, PCI_CFDA_PSM, WAKEUP);
663 read_hw_addr(dev, bis);