1 // SPDX-License-Identifier: GPL-2.0+
17 #define PCI_CFDA_PSM 0x43
19 #define CFRV_RN 0x000000f0 /* Revision Number */
21 #define WAKEUP 0x00 /* Power Saving Wakeup */
22 #define SLEEP 0x80 /* Power Saving Sleep Mode */
24 #define DC2114x_BRK 0x0020 /* CFRV break between DC21142 & DC21143 */
26 /* Ethernet chip registers.
28 #define DE4X5_BMR 0x000 /* Bus Mode Register */
29 #define DE4X5_TPD 0x008 /* Transmit Poll Demand Reg */
30 #define DE4X5_RRBA 0x018 /* RX Ring Base Address Reg */
31 #define DE4X5_TRBA 0x020 /* TX Ring Base Address Reg */
32 #define DE4X5_STS 0x028 /* Status Register */
33 #define DE4X5_OMR 0x030 /* Operation Mode Register */
34 #define DE4X5_SICR 0x068 /* SIA Connectivity Register */
35 #define DE4X5_APROM 0x048 /* Ethernet Address PROM */
39 #define BMR_SWR 0x00000001 /* Software Reset */
40 #define STS_TS 0x00700000 /* Transmit Process State */
41 #define STS_RS 0x000e0000 /* Receive Process State */
42 #define OMR_ST 0x00002000 /* Start/Stop Transmission Command */
43 #define OMR_SR 0x00000002 /* Start/Stop Receive */
44 #define OMR_PS 0x00040000 /* Port Select */
45 #define OMR_SDP 0x02000000 /* SD Polarity - MUST BE ASSERTED */
46 #define OMR_PM 0x00000080 /* Pass All Multicast */
50 #define R_OWN 0x80000000 /* Own Bit */
51 #define RD_RER 0x02000000 /* Receive End Of Ring */
52 #define RD_LS 0x00000100 /* Last Descriptor */
53 #define RD_ES 0x00008000 /* Error Summary */
54 #define TD_TER 0x02000000 /* Transmit End Of Ring */
55 #define T_OWN 0x80000000 /* Own Bit */
56 #define TD_LS 0x40000000 /* Last Segment */
57 #define TD_FS 0x20000000 /* First Segment */
58 #define TD_ES 0x00008000 /* Error Summary */
59 #define TD_SET 0x08000000 /* Setup Packet */
61 /* The EEPROM commands include the alway-set leading bit. */
62 #define SROM_WRITE_CMD 5
63 #define SROM_READ_CMD 6
64 #define SROM_ERASE_CMD 7
66 #define SROM_HWADD 0x0014 /* Hardware Address offset in SROM */
67 #define SROM_RD 0x00004000 /* Read from Boot ROM */
68 #define EE_DATA_WRITE 0x04 /* EEPROM chip data in. */
69 #define EE_WRITE_0 0x4801
70 #define EE_WRITE_1 0x4805
71 #define EE_DATA_READ 0x08 /* EEPROM chip data out. */
72 #define SROM_SR 0x00000800 /* Select Serial ROM when set */
74 #define DT_IN 0x00000004 /* Serial Data In */
75 #define DT_CLK 0x00000002 /* Serial ROM Clock */
76 #define DT_CS 0x00000001 /* Serial ROM Chip Select */
80 #define RESET_DE4X5(dev) {\
82 i=INL(dev, DE4X5_BMR);\
84 OUTL(dev, i | BMR_SWR, DE4X5_BMR);\
86 OUTL(dev, i, DE4X5_BMR);\
88 for (i=0;i<5;i++) {INL(dev, DE4X5_BMR); udelay(10000);}\
92 #define START_DE4X5(dev) {\
94 omr = INL(dev, DE4X5_OMR);\
95 omr |= OMR_ST | OMR_SR;\
96 OUTL(dev, omr, DE4X5_OMR); /* Enable the TX and/or RX */\
99 #define STOP_DE4X5(dev) {\
101 omr = INL(dev, DE4X5_OMR);\
102 omr &= ~(OMR_ST|OMR_SR);\
103 OUTL(dev, omr, DE4X5_OMR); /* Disable the TX and/or RX */ \
106 #define NUM_RX_DESC PKTBUFSRX
107 #define NUM_TX_DESC 1 /* Number of TX descriptors */
108 #define RX_BUFF_SZ PKTSIZE_ALIGN
110 #define TOUT_LOOP 1000000
112 #define SETUP_FRAME_LEN 192
121 static struct de4x5_desc rx_ring[NUM_RX_DESC] __attribute__ ((aligned(32))); /* RX descriptor ring */
122 static struct de4x5_desc tx_ring[NUM_TX_DESC] __attribute__ ((aligned(32))); /* TX descriptor ring */
123 static int rx_new; /* RX descriptor ring pointer */
124 static int tx_new; /* TX descriptor ring pointer */
126 static char rxRingSize;
127 static char txRingSize;
129 static void sendto_srom(struct eth_device* dev, u_int command, u_long addr);
130 static int getfrom_srom(struct eth_device* dev, u_long addr);
131 static int do_eeprom_cmd(struct eth_device *dev, u_long ioaddr,int cmd,int cmd_len);
132 static int do_read_eeprom(struct eth_device *dev,u_long ioaddr,int location,int addr_len);
134 static int write_srom(struct eth_device *dev, u_long ioaddr, int index, int new_value);
135 static void update_srom(struct eth_device *dev, bd_t *bis);
137 static int read_srom(struct eth_device *dev, u_long ioaddr, int index);
138 static void read_hw_addr(struct eth_device* dev, bd_t * bis);
139 static void send_setup_frame(struct eth_device* dev, bd_t * bis);
141 static int dc21x4x_init(struct eth_device* dev, bd_t* bis);
142 static int dc21x4x_send(struct eth_device *dev, void *packet, int length);
143 static int dc21x4x_recv(struct eth_device* dev);
144 static void dc21x4x_halt(struct eth_device* dev);
146 #if defined(CONFIG_E500)
147 #define phys_to_bus(a) (a)
149 #define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a)
152 static int INL(struct eth_device* dev, u_long addr)
154 return le32_to_cpu(*(volatile u_long *)(addr + dev->iobase));
157 static void OUTL(struct eth_device* dev, int command, u_long addr)
159 *(volatile u_long *)(addr + dev->iobase) = cpu_to_le32(command);
162 static struct pci_device_id supported[] = {
163 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_FAST },
164 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142 },
168 int dc21x4x_initialize(bd_t *bis)
176 unsigned short status;
177 struct eth_device* dev;
180 devbusfn = pci_find_devices(supported, idx++);
181 if (devbusfn == -1) {
185 /* Get the chip configuration revision register. */
186 pci_read_config_dword(devbusfn, PCI_REVISION_ID, &cfrv);
188 if ((cfrv & CFRV_RN) < DC2114x_BRK ) {
189 printf("Error: The chip is not DC21143.\n");
193 pci_read_config_word(devbusfn, PCI_COMMAND, &status);
197 pci_write_config_word(devbusfn, PCI_COMMAND, status);
199 pci_read_config_word(devbusfn, PCI_COMMAND, &status);
200 if (!(status & PCI_COMMAND_MEMORY)) {
201 printf("Error: Can not enable MEMORY access.\n");
205 if (!(status & PCI_COMMAND_MASTER)) {
206 printf("Error: Can not enable Bus Mastering.\n");
210 /* Check the latency timer for values >= 0x60. */
211 pci_read_config_byte(devbusfn, PCI_LATENCY_TIMER, &timer);
214 pci_write_config_byte(devbusfn, PCI_LATENCY_TIMER, 0x60);
217 /* read BAR for memory space access */
218 pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1, &iobase);
219 iobase &= PCI_BASE_ADDRESS_MEM_MASK;
220 debug ("dc21x4x: DEC 21142 PCI Device @0x%x\n", iobase);
222 dev = (struct eth_device*) malloc(sizeof *dev);
225 printf("Can not allocalte memory of dc21x4x\n");
228 memset(dev, 0, sizeof(*dev));
230 sprintf(dev->name, "dc21x4x#%d", card_number);
232 dev->iobase = pci_mem_to_phys(devbusfn, iobase);
233 dev->priv = (void*) devbusfn;
234 dev->init = dc21x4x_init;
235 dev->halt = dc21x4x_halt;
236 dev->send = dc21x4x_send;
237 dev->recv = dc21x4x_recv;
239 /* Ensure we're not sleeping. */
240 pci_write_config_byte(devbusfn, PCI_CFDA_PSM, WAKEUP);
244 read_hw_addr(dev, bis);
254 static int dc21x4x_init(struct eth_device* dev, bd_t* bis)
257 int devbusfn = (int) dev->priv;
259 /* Ensure we're not sleeping. */
260 pci_write_config_byte(devbusfn, PCI_CFDA_PSM, WAKEUP);
264 if ((INL(dev, DE4X5_STS) & (STS_TS | STS_RS)) != 0) {
265 printf("Error: Cannot reset ethernet controller.\n");
269 OUTL(dev, OMR_SDP | OMR_PS | OMR_PM, DE4X5_OMR);
271 for (i = 0; i < NUM_RX_DESC; i++) {
272 rx_ring[i].status = cpu_to_le32(R_OWN);
273 rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ);
274 rx_ring[i].buf = cpu_to_le32(
275 phys_to_bus((u32)net_rx_packets[i]));
279 for (i=0; i < NUM_TX_DESC; i++) {
280 tx_ring[i].status = 0;
286 rxRingSize = NUM_RX_DESC;
287 txRingSize = NUM_TX_DESC;
289 /* Write the end of list marker to the descriptor lists. */
290 rx_ring[rxRingSize - 1].des1 |= cpu_to_le32(RD_RER);
291 tx_ring[txRingSize - 1].des1 |= cpu_to_le32(TD_TER);
293 /* Tell the adapter where the TX/RX rings are located. */
294 OUTL(dev, phys_to_bus((u32) &rx_ring), DE4X5_RRBA);
295 OUTL(dev, phys_to_bus((u32) &tx_ring), DE4X5_TRBA);
302 send_setup_frame(dev, bis);
307 static int dc21x4x_send(struct eth_device *dev, void *packet, int length)
313 printf("%s: bad packet size: %d\n", dev->name, length);
317 for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) {
318 if (i >= TOUT_LOOP) {
319 printf("%s: tx error buffer not ready\n", dev->name);
324 tx_ring[tx_new].buf = cpu_to_le32(phys_to_bus((u32) packet));
325 tx_ring[tx_new].des1 = cpu_to_le32(TD_TER | TD_LS | TD_FS | length);
326 tx_ring[tx_new].status = cpu_to_le32(T_OWN);
328 OUTL(dev, POLL_DEMAND, DE4X5_TPD);
330 for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) {
331 if (i >= TOUT_LOOP) {
332 printf(".%s: tx buffer not ready\n", dev->name);
337 if (le32_to_cpu(tx_ring[tx_new].status) & TD_ES) {
338 #if 0 /* test-only */
339 printf("TX error status = 0x%08X\n",
340 le32_to_cpu(tx_ring[tx_new].status));
342 tx_ring[tx_new].status = 0x0;
349 tx_new = (tx_new+1) % NUM_TX_DESC;
353 static int dc21x4x_recv(struct eth_device* dev)
359 status = (s32)le32_to_cpu(rx_ring[rx_new].status);
361 if (status & R_OWN) {
365 if (status & RD_LS) {
366 /* Valid frame status.
368 if (status & RD_ES) {
370 /* There was an error.
372 printf("RX error status = 0x%08X\n", status);
374 /* A valid frame received.
376 length = (le32_to_cpu(rx_ring[rx_new].status) >> 16);
378 /* Pass the packet up to the protocol
381 net_process_received_packet(
382 net_rx_packets[rx_new], length - 4);
385 /* Change buffer ownership for this frame, back
388 rx_ring[rx_new].status = cpu_to_le32(R_OWN);
391 /* Update entry information.
393 rx_new = (rx_new + 1) % rxRingSize;
399 static void dc21x4x_halt(struct eth_device* dev)
401 int devbusfn = (int) dev->priv;
404 OUTL(dev, 0, DE4X5_SICR);
406 pci_write_config_byte(devbusfn, PCI_CFDA_PSM, SLEEP);
409 static void send_setup_frame(struct eth_device* dev, bd_t *bis)
412 char setup_frame[SETUP_FRAME_LEN];
413 char *pa = &setup_frame[0];
415 memset(pa, 0xff, SETUP_FRAME_LEN);
417 for (i = 0; i < ETH_ALEN; i++) {
418 *(pa + (i & 1)) = dev->enetaddr[i];
424 for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) {
425 if (i >= TOUT_LOOP) {
426 printf("%s: tx error buffer not ready\n", dev->name);
431 tx_ring[tx_new].buf = cpu_to_le32(phys_to_bus((u32) &setup_frame[0]));
432 tx_ring[tx_new].des1 = cpu_to_le32(TD_TER | TD_SET| SETUP_FRAME_LEN);
433 tx_ring[tx_new].status = cpu_to_le32(T_OWN);
435 OUTL(dev, POLL_DEMAND, DE4X5_TPD);
437 for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) {
438 if (i >= TOUT_LOOP) {
439 printf("%s: tx buffer not ready\n", dev->name);
444 if (le32_to_cpu(tx_ring[tx_new].status) != 0x7FFFFFFF) {
445 printf("TX error status2 = 0x%08X\n", le32_to_cpu(tx_ring[tx_new].status));
447 tx_new = (tx_new+1) % NUM_TX_DESC;
453 /* SROM Read and write routines. */
455 sendto_srom(struct eth_device* dev, u_int command, u_long addr)
457 OUTL(dev, command, addr);
462 getfrom_srom(struct eth_device* dev, u_long addr)
466 tmp = INL(dev, addr);
472 /* Note: this routine returns extra data bits for size detection. */
473 static int do_read_eeprom(struct eth_device *dev, u_long ioaddr, int location, int addr_len)
477 int read_cmd = location | (SROM_READ_CMD << addr_len);
479 sendto_srom(dev, SROM_RD | SROM_SR, ioaddr);
480 sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr);
483 printf(" EEPROM read at %d ", location);
486 /* Shift the read command bits out. */
487 for (i = 4 + addr_len; i >= 0; i--) {
488 short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
489 sendto_srom(dev, SROM_RD | SROM_SR | DT_CS | dataval, ioaddr);
491 sendto_srom(dev, SROM_RD | SROM_SR | DT_CS | dataval | DT_CLK, ioaddr);
494 printf("%X", getfrom_srom(dev, ioaddr) & 15);
496 retval = (retval << 1) | ((getfrom_srom(dev, ioaddr) & EE_DATA_READ) ? 1 : 0);
499 sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr);
502 printf(" :%X:", getfrom_srom(dev, ioaddr) & 15);
505 for (i = 16; i > 0; i--) {
506 sendto_srom(dev, SROM_RD | SROM_SR | DT_CS | DT_CLK, ioaddr);
509 printf("%X", getfrom_srom(dev, ioaddr) & 15);
511 retval = (retval << 1) | ((getfrom_srom(dev, ioaddr) & EE_DATA_READ) ? 1 : 0);
512 sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr);
516 /* Terminate the EEPROM access. */
517 sendto_srom(dev, SROM_RD | SROM_SR, ioaddr);
520 printf(" EEPROM value at %d is %5.5x.\n", location, retval);
527 * This executes a generic EEPROM command, typically a write or write
528 * enable. It returns the data output from the EEPROM, and thus may
529 * also be used for reads.
531 static int do_eeprom_cmd(struct eth_device *dev, u_long ioaddr, int cmd, int cmd_len)
536 printf(" EEPROM op 0x%x: ", cmd);
539 sendto_srom(dev,SROM_RD | SROM_SR | DT_CS | DT_CLK, ioaddr);
541 /* Shift the command bits out. */
543 short dataval = (cmd & (1 << cmd_len)) ? EE_WRITE_1 : EE_WRITE_0;
544 sendto_srom(dev,dataval, ioaddr);
548 printf("%X", getfrom_srom(dev,ioaddr) & 15);
551 sendto_srom(dev,dataval | DT_CLK, ioaddr);
553 retval = (retval << 1) | ((getfrom_srom(dev,ioaddr) & EE_DATA_READ) ? 1 : 0);
554 } while (--cmd_len >= 0);
555 sendto_srom(dev,SROM_RD | SROM_SR | DT_CS, ioaddr);
557 /* Terminate the EEPROM access. */
558 sendto_srom(dev,SROM_RD | SROM_SR, ioaddr);
561 printf(" EEPROM result is 0x%5.5x.\n", retval);
567 static int read_srom(struct eth_device *dev, u_long ioaddr, int index)
569 int ee_addr_size = do_read_eeprom(dev, ioaddr, 0xff, 8) & 0x40000 ? 8 : 6;
571 return do_eeprom_cmd(dev, ioaddr,
572 (((SROM_READ_CMD << ee_addr_size) | index) << 16)
573 | 0xffff, 3 + ee_addr_size + 16);
577 static int write_srom(struct eth_device *dev, u_long ioaddr, int index, int new_value)
579 int ee_addr_size = do_read_eeprom(dev, ioaddr, 0xff, 8) & 0x40000 ? 8 : 6;
581 unsigned short newval;
583 udelay(10*1000); /* test-only */
586 printf("ee_addr_size=%d.\n", ee_addr_size);
587 printf("Writing new entry 0x%4.4x to offset %d.\n", new_value, index);
590 /* Enable programming modes. */
591 do_eeprom_cmd(dev, ioaddr, (0x4f << (ee_addr_size-4)), 3+ee_addr_size);
593 /* Do the actual write. */
594 do_eeprom_cmd(dev, ioaddr,
595 (((SROM_WRITE_CMD<<ee_addr_size)|index) << 16) | new_value,
596 3 + ee_addr_size + 16);
598 /* Poll for write finished. */
599 sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr);
600 for (i = 0; i < 10000; i++) /* Typical 2000 ticks */
601 if (getfrom_srom(dev, ioaddr) & EE_DATA_READ)
605 printf(" Write finished after %d ticks.\n", i);
608 /* Disable programming. */
609 do_eeprom_cmd(dev, ioaddr, (0x40 << (ee_addr_size-4)), 3 + ee_addr_size);
611 /* And read the result. */
612 newval = do_eeprom_cmd(dev, ioaddr,
613 (((SROM_READ_CMD<<ee_addr_size)|index) << 16)
614 | 0xffff, 3 + ee_addr_size + 16);
616 printf(" New value at offset %d is %4.4x.\n", index, newval);
622 static void read_hw_addr(struct eth_device *dev, bd_t *bis)
624 u_short tmp, *p = (u_short *)(&dev->enetaddr[0]);
627 for (i = 0; i < (ETH_ALEN >> 1); i++) {
628 tmp = read_srom(dev, DE4X5_APROM, ((SROM_HWADD >> 1) + i));
629 *p = le16_to_cpu(tmp);
633 if ((j == 0) || (j == 0x2fffd)) {
634 memset (dev->enetaddr, 0, ETH_ALEN);
635 debug ("Warning: can't read HW address from SROM.\n");
643 update_srom(dev, bis);
649 static void update_srom(struct eth_device *dev, bd_t *bis)
652 static unsigned short eeprom[0x40] = {
653 0x140b, 0x6610, 0x0000, 0x0000, /* 00 */
654 0x0000, 0x0000, 0x0000, 0x0000, /* 04 */
655 0x00a3, 0x0103, 0x0000, 0x0000, /* 08 */
656 0x0000, 0x1f00, 0x0000, 0x0000, /* 0c */
657 0x0108, 0x038d, 0x0000, 0x0000, /* 10 */
658 0xe078, 0x0001, 0x0040, 0x0018, /* 14 */
659 0x0000, 0x0000, 0x0000, 0x0000, /* 18 */
660 0x0000, 0x0000, 0x0000, 0x0000, /* 1c */
661 0x0000, 0x0000, 0x0000, 0x0000, /* 20 */
662 0x0000, 0x0000, 0x0000, 0x0000, /* 24 */
663 0x0000, 0x0000, 0x0000, 0x0000, /* 28 */
664 0x0000, 0x0000, 0x0000, 0x0000, /* 2c */
665 0x0000, 0x0000, 0x0000, 0x0000, /* 30 */
666 0x0000, 0x0000, 0x0000, 0x0000, /* 34 */
667 0x0000, 0x0000, 0x0000, 0x0000, /* 38 */
668 0x0000, 0x0000, 0x0000, 0x4e07, /* 3c */
672 /* Ethernet Addr... */
673 if (!eth_env_get_enetaddr("ethaddr", enetaddr))
675 eeprom[0x0a] = (enetaddr[1] << 8) | enetaddr[0];
676 eeprom[0x0b] = (enetaddr[3] << 8) | enetaddr[2];
677 eeprom[0x0c] = (enetaddr[5] << 8) | enetaddr[4];
679 for (i=0; i<0x40; i++) {
680 write_srom(dev, DE4X5_APROM, i, eeprom[i]);
683 #endif /* UPDATE_SROM */