1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2011 Ilya Yanok, Emcraft Systems
5 * Based on: mach-davinci/emac_defs.h
6 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
9 #ifndef _DAVINCI_EMAC_H_
10 #define _DAVINCI_EMAC_H_
11 /* Ethernet Min/Max packet size */
12 #define EMAC_MIN_ETHERNET_PKT_SIZE 60
13 #define EMAC_MAX_ETHERNET_PKT_SIZE 1518
14 /* Buffer size (should be aligned on 32 byte and cache line) */
15 #define EMAC_RXBUF_SIZE ALIGN(ALIGN(EMAC_MAX_ETHERNET_PKT_SIZE, 32),\
18 /* Number of RX packet buffers
19 * NOTE: Only 1 buffer supported as of now
21 #define EMAC_MAX_RX_BUFFERS 10
24 /***********************************************
25 ******** Internally used macros ***************
26 ***********************************************/
31 /* Each descriptor occupies 4 words, lets start RX desc's at 0 and
32 * reserve space for 64 descriptors max
34 #define EMAC_RX_DESC_BASE 0x0
35 #define EMAC_TX_DESC_BASE 0x1000
37 /* EMAC Teardown value */
38 #define EMAC_TEARDOWN_VALUE 0xfffffffc
40 /* MII Status Register */
41 #define MII_STATUS_REG 1
42 /* PHY Configuration register */
43 #define PHY_CONF_TXCLKEN (1 << 5)
45 /* Number of statistics registers */
46 #define EMAC_NUM_STATS 36
50 typedef volatile struct _emac_desc
52 u_int32_t next; /* Pointer to next descriptor
54 u_int8_t *buffer; /* Pointer to data buffer */
55 u_int32_t buff_off_len; /* Buffer Offset(MSW) and Length(LSW) */
56 u_int32_t pkt_flag_len; /* Packet Flags(MSW) and Length(LSW) */
59 /* CPPI bit positions */
60 #define EMAC_CPPI_SOP_BIT (0x80000000)
61 #define EMAC_CPPI_EOP_BIT (0x40000000)
62 #define EMAC_CPPI_OWNERSHIP_BIT (0x20000000)
63 #define EMAC_CPPI_EOQ_BIT (0x10000000)
64 #define EMAC_CPPI_TEARDOWN_COMPLETE_BIT (0x08000000)
65 #define EMAC_CPPI_PASS_CRC_BIT (0x04000000)
67 #define EMAC_CPPI_RX_ERROR_FRAME (0x03fc0000)
69 #define EMAC_MACCONTROL_MIIEN_ENABLE (0x20)
70 #define EMAC_MACCONTROL_FULLDUPLEX_ENABLE (0x1)
71 #define EMAC_MACCONTROL_GIGABIT_ENABLE (1 << 7)
72 #define EMAC_MACCONTROL_GIGFORCE (1 << 17)
73 #define EMAC_MACCONTROL_RMIISPEED_100 (1 << 15)
75 #define EMAC_MAC_ADDR_MATCH (1 << 19)
76 #define EMAC_MAC_ADDR_IS_VALID (1 << 20)
78 #define EMAC_RXMBPENABLE_RXCAFEN_ENABLE (0x200000)
79 #define EMAC_RXMBPENABLE_RXBROADEN (0x2000)
82 #define MDIO_CONTROL_IDLE (0x80000000)
83 #define MDIO_CONTROL_ENABLE (0x40000000)
84 #define MDIO_CONTROL_FAULT_ENABLE (0x40000)
85 #define MDIO_CONTROL_FAULT (0x80000)
86 #define MDIO_USERACCESS0_GO (0x80000000)
87 #define MDIO_USERACCESS0_WRITE_READ (0x0)
88 #define MDIO_USERACCESS0_WRITE_WRITE (0x40000000)
89 #define MDIO_USERACCESS0_ACK (0x20000000)
91 /* Ethernet MAC Registers Structure */
102 dv_reg TXINTSTATMASKED;
104 dv_reg TXINTMASKCLEAR;
108 dv_reg RXINTSTATMASKED;
110 dv_reg RXINTMASKCLEAR;
111 dv_reg MACINTSTATRAW;
112 dv_reg MACINTSTATMASKED;
113 dv_reg MACINTMASKSET;
114 dv_reg MACINTMASKCLEAR;
118 dv_reg RXUNICASTCLEAR;
120 dv_reg RXBUFFEROFFSET;
121 dv_reg RXFILTERLOWTHRESH;
123 dv_reg RX0FLOWTHRESH;
124 dv_reg RX1FLOWTHRESH;
125 dv_reg RX2FLOWTHRESH;
126 dv_reg RX3FLOWTHRESH;
127 dv_reg RX4FLOWTHRESH;
128 dv_reg RX5FLOWTHRESH;
129 dv_reg RX6FLOWTHRESH;
130 dv_reg RX7FLOWTHRESH;
131 dv_reg RX0FREEBUFFER;
132 dv_reg RX1FREEBUFFER;
133 dv_reg RX2FREEBUFFER;
134 dv_reg RX3FREEBUFFER;
135 dv_reg RX4FREEBUFFER;
136 dv_reg RX5FREEBUFFER;
137 dv_reg RX6FREEBUFFER;
138 dv_reg RX7FREEBUFFER;
156 dv_reg RXBCASTFRAMES;
157 dv_reg RXMCASTFRAMES;
158 dv_reg RXPAUSEFRAMES;
160 dv_reg RXALIGNCODEERRORS;
166 dv_reg RXQOSFILTERED;
169 dv_reg TXBCASTFRAMES;
170 dv_reg TXMCASTFRAMES;
171 dv_reg TXPAUSEFRAMES;
176 dv_reg TXEXCESSIVECOLL;
179 dv_reg TXCARRIERSENSE;
185 dv_reg FRAME512T1023;
188 dv_reg RXSOFOVERRUNS;
189 dv_reg RXMOFOVERRUNS;
190 dv_reg RXDMAOVERRUNS;
230 /* EMAC Wrapper Registers Structure */
232 #ifdef DAVINCI_EMAC_VERSION2
248 dv_reg c0rxthreshstat;
252 dv_reg c1rxthreshstat;
256 dv_reg c2rxthreshstat;
267 u_int8_t RSVD0[4100];
273 /* EMAC MDIO Registers Structure */
280 dv_reg LINKINTMASKED;
283 dv_reg USERINTMASKED;
284 dv_reg USERINTMASKSET;
285 dv_reg USERINTMASKCLEAR;
293 int davinci_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data);
294 int davinci_eth_phy_write(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data);
298 int (*init)(int phy_addr);
299 int (*is_phy_connected)(int phy_addr);
300 int (*get_link_speed)(int phy_addr);
301 int (*auto_negotiate)(int phy_addr);
304 #endif /* _DAVINCI_EMAC_H_ */