2 * Ethernet driver for TI TMS320DM644x (DaVinci) chips.
4 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
6 * Parts shamelessly stolen from TI's dm644x_emac.c. Original copyright
9 * ----------------------------------------------------------------------------
13 * TI DaVinci (DM644X) EMAC peripheral driver source for DV-EVM
15 * Copyright (C) 2005 Texas Instruments.
17 * ----------------------------------------------------------------------------
19 * This program is free software; you can redistribute it and/or modify
20 * it under the terms of the GNU General Public License as published by
21 * the Free Software Foundation; either version 2 of the License, or
22 * (at your option) any later version.
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
32 * ----------------------------------------------------------------------------
35 * ver. 1.0: Sep 2005, Anant Gole - Created EMAC version for uBoot.
36 * ver 1.1: Nov 2005, Anant Gole - Extended the RX logic for multiple descriptors
44 #include <asm/arch/emac_defs.h>
47 unsigned int emac_dbg = 0;
48 #define debug_emac(fmt,args...) if (emac_dbg) printf(fmt,##args)
50 #ifdef DAVINCI_EMAC_GIG_ENABLE
51 #define emac_gigabit_enable() davinci_eth_gigabit_enable()
53 #define emac_gigabit_enable() /* no gigabit to enable */
56 static void davinci_eth_mdio_enable(void);
58 static int gen_init_phy(int phy_addr);
59 static int gen_is_phy_connected(int phy_addr);
60 static int gen_get_link_speed(int phy_addr);
61 static int gen_auto_negotiate(int phy_addr);
63 void eth_mdio_enable(void)
65 davinci_eth_mdio_enable();
69 static volatile emac_regs *adap_emac = (emac_regs *)EMAC_BASE_ADDR;
70 static volatile ewrap_regs *adap_ewrap = (ewrap_regs *)EMAC_WRAPPER_BASE_ADDR;
71 static volatile mdio_regs *adap_mdio = (mdio_regs *)EMAC_MDIO_BASE_ADDR;
73 /* EMAC descriptors */
74 static volatile emac_desc *emac_rx_desc = (emac_desc *)(EMAC_WRAPPER_RAM_ADDR + EMAC_RX_DESC_BASE);
75 static volatile emac_desc *emac_tx_desc = (emac_desc *)(EMAC_WRAPPER_RAM_ADDR + EMAC_TX_DESC_BASE);
76 static volatile emac_desc *emac_rx_active_head = 0;
77 static volatile emac_desc *emac_rx_active_tail = 0;
78 static int emac_rx_queue_active = 0;
80 /* Receive packet buffers */
81 static unsigned char emac_rx_buffers[EMAC_MAX_RX_BUFFERS * (EMAC_MAX_ETHERNET_PKT_SIZE + EMAC_PKT_ALIGN)];
83 /* PHY address for a discovered PHY (0xff - not found) */
84 static volatile u_int8_t active_phy_addr = 0xff;
88 static int davinci_eth_set_mac_addr(struct eth_device *dev)
94 * Set MAC Addresses & Init multicast Hash to 0 (disable any multicast
96 * Using channel 0 only - other channels are disabled
98 writel(0, &adap_emac->MACINDEX);
99 mac_hi = (dev->enetaddr[3] << 24) |
100 (dev->enetaddr[2] << 16) |
101 (dev->enetaddr[1] << 8) |
103 mac_lo = (dev->enetaddr[5] << 8) |
106 writel(mac_hi, &adap_emac->MACADDRHI);
107 #if defined(DAVINCI_EMAC_VERSION2)
108 writel(mac_lo | EMAC_MAC_ADDR_IS_VALID | EMAC_MAC_ADDR_MATCH,
109 &adap_emac->MACADDRLO);
111 writel(mac_lo, &adap_emac->MACADDRLO);
114 writel(0, &adap_emac->MACHASH1);
115 writel(0, &adap_emac->MACHASH2);
117 /* Set source MAC address - REQUIRED */
118 writel(mac_hi, &adap_emac->MACSRCADDRHI);
119 writel(mac_lo, &adap_emac->MACSRCADDRLO);
125 static void davinci_eth_mdio_enable(void)
129 clkdiv = (EMAC_MDIO_BUS_FREQ / EMAC_MDIO_CLOCK_FREQ) - 1;
131 writel((clkdiv & 0xff) |
132 MDIO_CONTROL_ENABLE |
134 MDIO_CONTROL_FAULT_ENABLE,
135 &adap_mdio->CONTROL);
137 while (readl(&adap_mdio->CONTROL) & MDIO_CONTROL_IDLE)
142 * Tries to find an active connected PHY. Returns 1 if address if found.
143 * If no active PHY (or more than one PHY) found returns 0.
144 * Sets active_phy_addr variable.
146 static int davinci_eth_phy_detect(void)
148 u_int32_t phy_act_state;
151 active_phy_addr = 0xff;
153 phy_act_state = readl(&adap_mdio->ALIVE) & EMAC_MDIO_PHY_MASK;
154 if (phy_act_state == 0)
155 return(0); /* No active PHYs */
157 debug_emac("davinci_eth_phy_detect(), ALIVE = 0x%08x\n", phy_act_state);
159 for (i = 0; i < 32; i++) {
160 if (phy_act_state & (1 << i)) {
161 if (phy_act_state & ~(1 << i))
162 return(0); /* More than one PHY */
170 return(0); /* Just to make GCC happy */
174 /* Read a PHY register via MDIO inteface. Returns 1 on success, 0 otherwise */
175 int davinci_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data)
179 while (readl(&adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO)
182 writel(MDIO_USERACCESS0_GO |
183 MDIO_USERACCESS0_WRITE_READ |
184 ((reg_num & 0x1f) << 21) |
185 ((phy_addr & 0x1f) << 16),
186 &adap_mdio->USERACCESS0);
188 /* Wait for command to complete */
189 while ((tmp = readl(&adap_mdio->USERACCESS0)) & MDIO_USERACCESS0_GO)
192 if (tmp & MDIO_USERACCESS0_ACK) {
193 *data = tmp & 0xffff;
201 /* Write to a PHY register via MDIO inteface. Blocks until operation is complete. */
202 int davinci_eth_phy_write(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data)
205 while (readl(&adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO)
208 writel(MDIO_USERACCESS0_GO |
209 MDIO_USERACCESS0_WRITE_WRITE |
210 ((reg_num & 0x1f) << 21) |
211 ((phy_addr & 0x1f) << 16) |
213 &adap_mdio->USERACCESS0);
215 /* Wait for command to complete */
216 while (readl(&adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO)
222 /* PHY functions for a generic PHY */
223 static int gen_init_phy(int phy_addr)
227 if (gen_get_link_speed(phy_addr)) {
228 /* Try another time */
229 ret = gen_get_link_speed(phy_addr);
235 static int gen_is_phy_connected(int phy_addr)
239 return(davinci_eth_phy_read(phy_addr, MII_PHYSID1, &dummy));
242 static int gen_get_link_speed(int phy_addr)
246 if (davinci_eth_phy_read(phy_addr, MII_STATUS_REG, &tmp) &&
248 #if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \
249 defined(CONFIG_MACH_DAVINCI_DA850_EVM)
250 davinci_eth_phy_read(phy_addr, MII_LPA, &tmp);
252 /* Speed doesn't matter, there is no setting for it in EMAC. */
253 if (tmp & (LPA_100FULL | LPA_10FULL)) {
254 /* set EMAC for Full Duplex */
255 writel(EMAC_MACCONTROL_MIIEN_ENABLE |
256 EMAC_MACCONTROL_FULLDUPLEX_ENABLE,
257 &adap_emac->MACCONTROL);
259 /*set EMAC for Half Duplex */
260 writel(EMAC_MACCONTROL_MIIEN_ENABLE,
261 &adap_emac->MACCONTROL);
264 if (tmp & (LPA_100FULL | LPA_100HALF))
265 writel(readl(&adap_emac->MACCONTROL) |
266 EMAC_MACCONTROL_RMIISPEED_100,
267 &adap_emac->MACCONTROL);
269 writel(readl(&adap_emac->MACCONTROL) &
270 ~EMAC_MACCONTROL_RMIISPEED_100,
271 &adap_emac->MACCONTROL);
279 static int gen_auto_negotiate(int phy_addr)
283 unsigned long cntr = 0;
285 if (!davinci_eth_phy_read(phy_addr, MII_BMCR, &tmp))
288 val = tmp | BMCR_FULLDPLX | BMCR_ANENABLE |
290 davinci_eth_phy_write(phy_addr, MII_BMCR, val);
292 if (!davinci_eth_phy_read(phy_addr, MII_ADVERTISE, &val))
295 val |= (ADVERTISE_100FULL | ADVERTISE_100HALF | ADVERTISE_10FULL |
297 davinci_eth_phy_write(phy_addr, MII_ADVERTISE, val);
299 if (!davinci_eth_phy_read(phy_addr, MII_BMCR, &tmp))
302 /* Restart Auto_negotiation */
303 tmp |= BMCR_ANRESTART;
304 davinci_eth_phy_write(phy_addr, MII_BMCR, tmp);
306 /*check AutoNegotiate complete */
309 if (!davinci_eth_phy_read(phy_addr, MII_BMSR, &tmp))
312 if (tmp & BMSR_ANEGCOMPLETE)
316 } while (cntr < 200);
318 if (!davinci_eth_phy_read(phy_addr, MII_BMSR, &tmp))
321 if (!(tmp & BMSR_ANEGCOMPLETE))
324 return(gen_get_link_speed(phy_addr));
326 /* End of generic PHY functions */
329 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
330 static int davinci_mii_phy_read(const char *devname, unsigned char addr, unsigned char reg, unsigned short *value)
332 return(davinci_eth_phy_read(addr, reg, value) ? 0 : 1);
335 static int davinci_mii_phy_write(const char *devname, unsigned char addr, unsigned char reg, unsigned short value)
337 return(davinci_eth_phy_write(addr, reg, value) ? 0 : 1);
341 static void __attribute__((unused)) davinci_eth_gigabit_enable(void)
345 if (davinci_eth_phy_read(EMAC_MDIO_PHY_NUM, 0, &data)) {
346 if (data & (1 << 6)) { /* speed selection MSB */
348 * Check if link detected is giga-bit
349 * If Gigabit mode detected, enable gigbit in MAC
351 writel(readl(&adap_emac->MACCONTROL) |
352 EMAC_MACCONTROL_GIGFORCE |
353 EMAC_MACCONTROL_GIGABIT_ENABLE,
354 &adap_emac->MACCONTROL);
359 /* Eth device open */
360 static int davinci_eth_open(struct eth_device *dev, bd_t *bis)
363 u_int32_t clkdiv, cnt;
364 volatile emac_desc *rx_desc;
366 debug_emac("+ emac_open\n");
368 /* Reset EMAC module and disable interrupts in wrapper */
369 writel(1, &adap_emac->SOFTRESET);
370 while (readl(&adap_emac->SOFTRESET) != 0)
372 #if defined(DAVINCI_EMAC_VERSION2)
373 writel(1, &adap_ewrap->softrst);
374 while (readl(&adap_ewrap->softrst) != 0)
377 writel(0, &adap_ewrap->EWCTL);
378 for (cnt = 0; cnt < 5; cnt++) {
379 clkdiv = readl(&adap_ewrap->EWCTL);
383 #if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \
384 defined(CONFIG_MACH_DAVINCI_DA850_EVM)
385 adap_ewrap->c0rxen = adap_ewrap->c1rxen = adap_ewrap->c2rxen = 0;
386 adap_ewrap->c0txen = adap_ewrap->c1txen = adap_ewrap->c2txen = 0;
387 adap_ewrap->c0miscen = adap_ewrap->c1miscen = adap_ewrap->c2miscen = 0;
389 rx_desc = emac_rx_desc;
391 writel(1, &adap_emac->TXCONTROL);
392 writel(1, &adap_emac->RXCONTROL);
394 davinci_eth_set_mac_addr(dev);
396 /* Set DMA 8 TX / 8 RX Head pointers to 0 */
397 addr = &adap_emac->TX0HDP;
398 for(cnt = 0; cnt < 16; cnt++)
401 addr = &adap_emac->RX0HDP;
402 for(cnt = 0; cnt < 16; cnt++)
405 /* Clear Statistics (do this before setting MacControl register) */
406 addr = &adap_emac->RXGOODFRAMES;
407 for(cnt = 0; cnt < EMAC_NUM_STATS; cnt++)
410 /* No multicast addressing */
411 writel(0, &adap_emac->MACHASH1);
412 writel(0, &adap_emac->MACHASH2);
414 /* Create RX queue and set receive process in place */
415 emac_rx_active_head = emac_rx_desc;
416 for (cnt = 0; cnt < EMAC_MAX_RX_BUFFERS; cnt++) {
417 rx_desc->next = (u_int32_t)(rx_desc + 1);
418 rx_desc->buffer = &emac_rx_buffers[cnt * (EMAC_MAX_ETHERNET_PKT_SIZE + EMAC_PKT_ALIGN)];
419 rx_desc->buff_off_len = EMAC_MAX_ETHERNET_PKT_SIZE;
420 rx_desc->pkt_flag_len = EMAC_CPPI_OWNERSHIP_BIT;
424 /* Finalize the rx desc list */
427 emac_rx_active_tail = rx_desc;
428 emac_rx_queue_active = 1;
431 writel(EMAC_MAX_ETHERNET_PKT_SIZE, &adap_emac->RXMAXLEN);
432 writel(0, &adap_emac->RXBUFFEROFFSET);
435 * No fancy configs - Use this for promiscous debug
436 * - EMAC_RXMBPENABLE_RXCAFEN_ENABLE
438 writel(EMAC_RXMBPENABLE_RXBROADEN, &adap_emac->RXMBPENABLE);
440 /* Enable ch 0 only */
441 writel(1, &adap_emac->RXUNICASTSET);
443 /* Enable MII interface and Full duplex mode */
444 #ifdef CONFIG_SOC_DA8XX
445 writel((EMAC_MACCONTROL_MIIEN_ENABLE |
446 EMAC_MACCONTROL_FULLDUPLEX_ENABLE |
447 EMAC_MACCONTROL_RMIISPEED_100),
448 &adap_emac->MACCONTROL);
450 writel((EMAC_MACCONTROL_MIIEN_ENABLE |
451 EMAC_MACCONTROL_FULLDUPLEX_ENABLE),
452 &adap_emac->MACCONTROL);
455 /* Init MDIO & get link state */
456 clkdiv = (EMAC_MDIO_BUS_FREQ / EMAC_MDIO_CLOCK_FREQ) - 1;
457 writel((clkdiv & 0xff) | MDIO_CONTROL_ENABLE | MDIO_CONTROL_FAULT,
458 &adap_mdio->CONTROL);
460 /* We need to wait for MDIO to start */
463 if (!phy.get_link_speed(active_phy_addr))
466 emac_gigabit_enable();
468 /* Start receive process */
469 writel((u_int32_t)emac_rx_desc, &adap_emac->RX0HDP);
471 debug_emac("- emac_open\n");
476 /* EMAC Channel Teardown */
477 static void davinci_eth_ch_teardown(int ch)
482 debug_emac("+ emac_ch_teardown\n");
484 if (ch == EMAC_CH_TX) {
485 /* Init TX channel teardown */
486 writel(0, &adap_emac->TXTEARDOWN);
489 * Wait here for Tx teardown completion interrupt to
490 * occur. Note: A task delay can be called here to pend
491 * rather than occupying CPU cycles - anyway it has
492 * been found that teardown takes very few cpu cycles
493 * and does not affect functionality
499 cnt = readl(&adap_emac->TX0CP);
500 } while (cnt != 0xfffffffc);
501 writel(cnt, &adap_emac->TX0CP);
502 writel(0, &adap_emac->TX0HDP);
504 /* Init RX channel teardown */
505 writel(0, &adap_emac->RXTEARDOWN);
508 * Wait here for Rx teardown completion interrupt to
509 * occur. Note: A task delay can be called here to pend
510 * rather than occupying CPU cycles - anyway it has
511 * been found that teardown takes very few cpu cycles
512 * and does not affect functionality
518 cnt = readl(&adap_emac->RX0CP);
519 } while (cnt != 0xfffffffc);
520 writel(cnt, &adap_emac->RX0CP);
521 writel(0, &adap_emac->RX0HDP);
524 debug_emac("- emac_ch_teardown\n");
527 /* Eth device close */
528 static void davinci_eth_close(struct eth_device *dev)
530 debug_emac("+ emac_close\n");
532 davinci_eth_ch_teardown(EMAC_CH_TX); /* TX Channel teardown */
533 davinci_eth_ch_teardown(EMAC_CH_RX); /* RX Channel teardown */
535 /* Reset EMAC module and disable interrupts in wrapper */
536 writel(1, &adap_emac->SOFTRESET);
537 #if defined(DAVINCI_EMAC_VERSION2)
538 writel(1, &adap_ewrap->softrst);
540 writel(0, &adap_ewrap->EWCTL);
543 #if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \
544 defined(CONFIG_MACH_DAVINCI_DA850_EVM)
545 adap_ewrap->c0rxen = adap_ewrap->c1rxen = adap_ewrap->c2rxen = 0;
546 adap_ewrap->c0txen = adap_ewrap->c1txen = adap_ewrap->c2txen = 0;
547 adap_ewrap->c0miscen = adap_ewrap->c1miscen = adap_ewrap->c2miscen = 0;
549 debug_emac("- emac_close\n");
552 static int tx_send_loop = 0;
555 * This function sends a single packet on the network and returns
556 * positive number (number of bytes transmitted) or negative for error
558 static int davinci_eth_send_packet (struct eth_device *dev,
559 volatile void *packet, int length)
565 /* Return error if no link */
566 if (!phy.get_link_speed (active_phy_addr)) {
567 printf ("WARN: emac_send_packet: No link\n");
571 emac_gigabit_enable();
573 /* Check packet size and if < EMAC_MIN_ETHERNET_PKT_SIZE, pad it up */
574 if (length < EMAC_MIN_ETHERNET_PKT_SIZE) {
575 length = EMAC_MIN_ETHERNET_PKT_SIZE;
578 /* Populate the TX descriptor */
579 emac_tx_desc->next = 0;
580 emac_tx_desc->buffer = (u_int8_t *) packet;
581 emac_tx_desc->buff_off_len = (length & 0xffff);
582 emac_tx_desc->pkt_flag_len = ((length & 0xffff) |
584 EMAC_CPPI_OWNERSHIP_BIT |
586 /* Send the packet */
587 writel((unsigned long)emac_tx_desc, &adap_emac->TX0HDP);
589 /* Wait for packet to complete or link down */
591 if (!phy.get_link_speed (active_phy_addr)) {
592 davinci_eth_ch_teardown (EMAC_CH_TX);
596 emac_gigabit_enable();
598 if (readl(&adap_emac->TXINTSTATRAW) & 0x01) {
609 * This function handles receipt of a packet from the network
611 static int davinci_eth_rcv_packet (struct eth_device *dev)
613 volatile emac_desc *rx_curr_desc;
614 volatile emac_desc *curr_desc;
615 volatile emac_desc *tail_desc;
616 int status, ret = -1;
618 rx_curr_desc = emac_rx_active_head;
619 status = rx_curr_desc->pkt_flag_len;
620 if ((rx_curr_desc) && ((status & EMAC_CPPI_OWNERSHIP_BIT) == 0)) {
621 if (status & EMAC_CPPI_RX_ERROR_FRAME) {
622 /* Error in packet - discard it and requeue desc */
623 printf ("WARN: emac_rcv_pkt: Error in packet\n");
625 NetReceive (rx_curr_desc->buffer,
626 (rx_curr_desc->buff_off_len & 0xffff));
627 ret = rx_curr_desc->buff_off_len & 0xffff;
630 /* Ack received packet descriptor */
631 writel((unsigned long)rx_curr_desc, &adap_emac->RX0CP);
632 curr_desc = rx_curr_desc;
633 emac_rx_active_head =
634 (volatile emac_desc *) rx_curr_desc->next;
636 if (status & EMAC_CPPI_EOQ_BIT) {
637 if (emac_rx_active_head) {
638 writel((unsigned long)emac_rx_active_head,
641 emac_rx_queue_active = 0;
642 printf ("INFO:emac_rcv_packet: RX Queue not active\n");
646 /* Recycle RX descriptor */
647 rx_curr_desc->buff_off_len = EMAC_MAX_ETHERNET_PKT_SIZE;
648 rx_curr_desc->pkt_flag_len = EMAC_CPPI_OWNERSHIP_BIT;
649 rx_curr_desc->next = 0;
651 if (emac_rx_active_head == 0) {
652 printf ("INFO: emac_rcv_pkt: active queue head = 0\n");
653 emac_rx_active_head = curr_desc;
654 emac_rx_active_tail = curr_desc;
655 if (emac_rx_queue_active != 0) {
656 writel((unsigned long)emac_rx_active_head,
658 printf ("INFO: emac_rcv_pkt: active queue head = 0, HDP fired\n");
659 emac_rx_queue_active = 1;
662 tail_desc = emac_rx_active_tail;
663 emac_rx_active_tail = curr_desc;
664 tail_desc->next = (unsigned int) curr_desc;
665 status = tail_desc->pkt_flag_len;
666 if (status & EMAC_CPPI_EOQ_BIT) {
667 writel((unsigned long)curr_desc,
669 status &= ~EMAC_CPPI_EOQ_BIT;
670 tail_desc->pkt_flag_len = status;
679 * This function initializes the emac hardware. It does NOT initialize
680 * EMAC modules power or pin multiplexors, that is done by board_init()
681 * much earlier in bootup process. Returns 1 on success, 0 otherwise.
683 int davinci_emac_initialize(void)
688 struct eth_device *dev;
690 dev = malloc(sizeof *dev);
695 memset(dev, 0, sizeof *dev);
696 sprintf(dev->name, "DaVinci-EMAC");
699 dev->init = davinci_eth_open;
700 dev->halt = davinci_eth_close;
701 dev->send = davinci_eth_send_packet;
702 dev->recv = davinci_eth_rcv_packet;
703 dev->write_hwaddr = davinci_eth_set_mac_addr;
707 davinci_eth_mdio_enable();
709 /* let the EMAC detect the PHYs */
712 for (i = 0; i < 256; i++) {
713 if (readl(&adap_mdio->ALIVE))
719 printf("No ETH PHY detected!!!\n");
723 /* Find if a PHY is connected and get it's address */
724 if (!davinci_eth_phy_detect())
727 /* Get PHY ID and initialize phy_ops for a detected PHY */
728 if (!davinci_eth_phy_read(active_phy_addr, MII_PHYSID1, &tmp)) {
729 active_phy_addr = 0xff;
733 phy_id = (tmp << 16) & 0xffff0000;
735 if (!davinci_eth_phy_read(active_phy_addr, MII_PHYSID2, &tmp)) {
736 active_phy_addr = 0xff;
740 phy_id |= tmp & 0x0000ffff;
744 sprintf(phy.name, "KSZ8873 @ 0x%02x", active_phy_addr);
745 phy.init = ksz8873_init_phy;
746 phy.is_phy_connected = ksz8873_is_phy_connected;
747 phy.get_link_speed = ksz8873_get_link_speed;
748 phy.auto_negotiate = ksz8873_auto_negotiate;
751 sprintf(phy.name, "LXT972 @ 0x%02x", active_phy_addr);
752 phy.init = lxt972_init_phy;
753 phy.is_phy_connected = lxt972_is_phy_connected;
754 phy.get_link_speed = lxt972_get_link_speed;
755 phy.auto_negotiate = lxt972_auto_negotiate;
758 sprintf(phy.name, "DP83848 @ 0x%02x", active_phy_addr);
759 phy.init = dp83848_init_phy;
760 phy.is_phy_connected = dp83848_is_phy_connected;
761 phy.get_link_speed = dp83848_get_link_speed;
762 phy.auto_negotiate = dp83848_auto_negotiate;
765 sprintf(phy.name, "ET1011C @ 0x%02x", active_phy_addr);
766 phy.init = gen_init_phy;
767 phy.is_phy_connected = gen_is_phy_connected;
768 phy.get_link_speed = et1011c_get_link_speed;
769 phy.auto_negotiate = gen_auto_negotiate;
772 sprintf(phy.name, "GENERIC @ 0x%02x", active_phy_addr);
773 phy.init = gen_init_phy;
774 phy.is_phy_connected = gen_is_phy_connected;
775 phy.get_link_speed = gen_get_link_speed;
776 phy.auto_negotiate = gen_auto_negotiate;
779 debug("Ethernet PHY: %s\n", phy.name);
781 miiphy_register(phy.name, davinci_mii_phy_read, davinci_mii_phy_write);