2 * Ethernet driver for TI TMS320DM644x (DaVinci) chips.
4 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
6 * Parts shamelessly stolen from TI's dm644x_emac.c. Original copyright
9 * ----------------------------------------------------------------------------
13 * TI DaVinci (DM644X) EMAC peripheral driver source for DV-EVM
15 * Copyright (C) 2005 Texas Instruments.
17 * ----------------------------------------------------------------------------
19 * This program is free software; you can redistribute it and/or modify
20 * it under the terms of the GNU General Public License as published by
21 * the Free Software Foundation; either version 2 of the License, or
22 * (at your option) any later version.
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
32 * ----------------------------------------------------------------------------
35 * ver. 1.0: Sep 2005, Anant Gole - Created EMAC version for uBoot.
36 * ver 1.1: Nov 2005, Anant Gole - Extended the RX logic for multiple descriptors
44 #include <asm/arch/emac_defs.h>
46 #include "davinci_emac.h"
48 unsigned int emac_dbg = 0;
49 #define debug_emac(fmt,args...) if (emac_dbg) printf(fmt,##args)
51 #ifdef DAVINCI_EMAC_GIG_ENABLE
52 #define emac_gigabit_enable(phy_addr) davinci_eth_gigabit_enable(phy_addr)
54 #define emac_gigabit_enable(phy_addr) /* no gigabit to enable */
57 #if !defined(CONFIG_SYS_EMAC_TI_CLKDIV)
58 #define CONFIG_SYS_EMAC_TI_CLKDIV ((EMAC_MDIO_BUS_FREQ / \
59 EMAC_MDIO_CLOCK_FREQ) - 1)
62 static void davinci_eth_mdio_enable(void);
64 static int gen_init_phy(int phy_addr);
65 static int gen_is_phy_connected(int phy_addr);
66 static int gen_get_link_speed(int phy_addr);
67 static int gen_auto_negotiate(int phy_addr);
69 void eth_mdio_enable(void)
71 davinci_eth_mdio_enable();
75 static volatile emac_regs *adap_emac = (emac_regs *)EMAC_BASE_ADDR;
76 static volatile ewrap_regs *adap_ewrap = (ewrap_regs *)EMAC_WRAPPER_BASE_ADDR;
77 static volatile mdio_regs *adap_mdio = (mdio_regs *)EMAC_MDIO_BASE_ADDR;
79 /* EMAC descriptors */
80 static volatile emac_desc *emac_rx_desc = (emac_desc *)(EMAC_WRAPPER_RAM_ADDR + EMAC_RX_DESC_BASE);
81 static volatile emac_desc *emac_tx_desc = (emac_desc *)(EMAC_WRAPPER_RAM_ADDR + EMAC_TX_DESC_BASE);
82 static volatile emac_desc *emac_rx_active_head = 0;
83 static volatile emac_desc *emac_rx_active_tail = 0;
84 static int emac_rx_queue_active = 0;
86 /* Receive packet buffers */
87 static unsigned char emac_rx_buffers[EMAC_MAX_RX_BUFFERS * (EMAC_MAX_ETHERNET_PKT_SIZE + EMAC_PKT_ALIGN)];
89 #ifndef CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT
90 #define CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT 3
93 /* PHY address for a discovered PHY (0xff - not found) */
94 static u_int8_t active_phy_addr[CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT];
96 /* number of PHY found active */
97 static u_int8_t num_phy;
99 phy_t phy[CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT];
101 static int davinci_eth_set_mac_addr(struct eth_device *dev)
103 unsigned long mac_hi;
104 unsigned long mac_lo;
107 * Set MAC Addresses & Init multicast Hash to 0 (disable any multicast
109 * Using channel 0 only - other channels are disabled
111 writel(0, &adap_emac->MACINDEX);
112 mac_hi = (dev->enetaddr[3] << 24) |
113 (dev->enetaddr[2] << 16) |
114 (dev->enetaddr[1] << 8) |
116 mac_lo = (dev->enetaddr[5] << 8) |
119 writel(mac_hi, &adap_emac->MACADDRHI);
120 #if defined(DAVINCI_EMAC_VERSION2)
121 writel(mac_lo | EMAC_MAC_ADDR_IS_VALID | EMAC_MAC_ADDR_MATCH,
122 &adap_emac->MACADDRLO);
124 writel(mac_lo, &adap_emac->MACADDRLO);
127 writel(0, &adap_emac->MACHASH1);
128 writel(0, &adap_emac->MACHASH2);
130 /* Set source MAC address - REQUIRED */
131 writel(mac_hi, &adap_emac->MACSRCADDRHI);
132 writel(mac_lo, &adap_emac->MACSRCADDRLO);
138 static void davinci_eth_mdio_enable(void)
142 clkdiv = CONFIG_SYS_EMAC_TI_CLKDIV;
144 writel((clkdiv & 0xff) |
145 MDIO_CONTROL_ENABLE |
147 MDIO_CONTROL_FAULT_ENABLE,
148 &adap_mdio->CONTROL);
150 while (readl(&adap_mdio->CONTROL) & MDIO_CONTROL_IDLE)
155 * Tries to find an active connected PHY. Returns 1 if address if found.
156 * If no active PHY (or more than one PHY) found returns 0.
157 * Sets active_phy_addr variable.
159 static int davinci_eth_phy_detect(void)
161 u_int32_t phy_act_state;
164 unsigned int count = 0;
166 for (i = 0; i < CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT; i++)
167 active_phy_addr[i] = 0xff;
170 phy_act_state = readl(&adap_mdio->ALIVE);
172 if (phy_act_state == 0)
173 return 0; /* No active PHYs */
175 debug_emac("davinci_eth_phy_detect(), ALIVE = 0x%08x\n", phy_act_state);
177 for (i = 0, j = 0; i < 32; i++)
178 if (phy_act_state & (1 << i)) {
180 if (count < CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT) {
181 active_phy_addr[j++] = i;
183 printf("%s: to many PHYs detected.\n",
196 /* Read a PHY register via MDIO inteface. Returns 1 on success, 0 otherwise */
197 int davinci_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data)
201 while (readl(&adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO)
204 writel(MDIO_USERACCESS0_GO |
205 MDIO_USERACCESS0_WRITE_READ |
206 ((reg_num & 0x1f) << 21) |
207 ((phy_addr & 0x1f) << 16),
208 &adap_mdio->USERACCESS0);
210 /* Wait for command to complete */
211 while ((tmp = readl(&adap_mdio->USERACCESS0)) & MDIO_USERACCESS0_GO)
214 if (tmp & MDIO_USERACCESS0_ACK) {
215 *data = tmp & 0xffff;
223 /* Write to a PHY register via MDIO inteface. Blocks until operation is complete. */
224 int davinci_eth_phy_write(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data)
227 while (readl(&adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO)
230 writel(MDIO_USERACCESS0_GO |
231 MDIO_USERACCESS0_WRITE_WRITE |
232 ((reg_num & 0x1f) << 21) |
233 ((phy_addr & 0x1f) << 16) |
235 &adap_mdio->USERACCESS0);
237 /* Wait for command to complete */
238 while (readl(&adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO)
244 /* PHY functions for a generic PHY */
245 static int gen_init_phy(int phy_addr)
249 if (gen_get_link_speed(phy_addr)) {
250 /* Try another time */
251 ret = gen_get_link_speed(phy_addr);
257 static int gen_is_phy_connected(int phy_addr)
261 return davinci_eth_phy_read(phy_addr, MII_PHYSID1, &dummy);
264 static int get_active_phy(void)
268 for (i = 0; i < num_phy; i++)
269 if (phy[i].get_link_speed(active_phy_addr[i]))
272 return -1; /* Return error if no link */
275 static int gen_get_link_speed(int phy_addr)
279 if (davinci_eth_phy_read(phy_addr, MII_STATUS_REG, &tmp) &&
281 #if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \
282 defined(CONFIG_MACH_DAVINCI_DA850_EVM)
283 davinci_eth_phy_read(phy_addr, MII_LPA, &tmp);
285 /* Speed doesn't matter, there is no setting for it in EMAC. */
286 if (tmp & (LPA_100FULL | LPA_10FULL)) {
287 /* set EMAC for Full Duplex */
288 writel(EMAC_MACCONTROL_MIIEN_ENABLE |
289 EMAC_MACCONTROL_FULLDUPLEX_ENABLE,
290 &adap_emac->MACCONTROL);
292 /*set EMAC for Half Duplex */
293 writel(EMAC_MACCONTROL_MIIEN_ENABLE,
294 &adap_emac->MACCONTROL);
297 if (tmp & (LPA_100FULL | LPA_100HALF))
298 writel(readl(&adap_emac->MACCONTROL) |
299 EMAC_MACCONTROL_RMIISPEED_100,
300 &adap_emac->MACCONTROL);
302 writel(readl(&adap_emac->MACCONTROL) &
303 ~EMAC_MACCONTROL_RMIISPEED_100,
304 &adap_emac->MACCONTROL);
312 static int gen_auto_negotiate(int phy_addr)
316 unsigned long cntr = 0;
318 if (!davinci_eth_phy_read(phy_addr, MII_BMCR, &tmp))
321 val = tmp | BMCR_FULLDPLX | BMCR_ANENABLE |
323 davinci_eth_phy_write(phy_addr, MII_BMCR, val);
325 if (!davinci_eth_phy_read(phy_addr, MII_ADVERTISE, &val))
328 val |= (ADVERTISE_100FULL | ADVERTISE_100HALF | ADVERTISE_10FULL |
330 davinci_eth_phy_write(phy_addr, MII_ADVERTISE, val);
332 if (!davinci_eth_phy_read(phy_addr, MII_BMCR, &tmp))
335 /* Restart Auto_negotiation */
336 tmp |= BMCR_ANRESTART;
337 davinci_eth_phy_write(phy_addr, MII_BMCR, tmp);
339 /*check AutoNegotiate complete */
342 if (!davinci_eth_phy_read(phy_addr, MII_BMSR, &tmp))
345 if (tmp & BMSR_ANEGCOMPLETE)
349 } while (cntr < 200);
351 if (!davinci_eth_phy_read(phy_addr, MII_BMSR, &tmp))
354 if (!(tmp & BMSR_ANEGCOMPLETE))
357 return(gen_get_link_speed(phy_addr));
359 /* End of generic PHY functions */
362 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
363 static int davinci_mii_phy_read(const char *devname, unsigned char addr, unsigned char reg, unsigned short *value)
365 return(davinci_eth_phy_read(addr, reg, value) ? 0 : 1);
368 static int davinci_mii_phy_write(const char *devname, unsigned char addr, unsigned char reg, unsigned short value)
370 return(davinci_eth_phy_write(addr, reg, value) ? 0 : 1);
374 static void __attribute__((unused)) davinci_eth_gigabit_enable(int phy_addr)
378 if (davinci_eth_phy_read(phy_addr, 0, &data)) {
379 if (data & (1 << 6)) { /* speed selection MSB */
381 * Check if link detected is giga-bit
382 * If Gigabit mode detected, enable gigbit in MAC
384 writel(readl(&adap_emac->MACCONTROL) |
385 EMAC_MACCONTROL_GIGFORCE |
386 EMAC_MACCONTROL_GIGABIT_ENABLE,
387 &adap_emac->MACCONTROL);
392 /* Eth device open */
393 static int davinci_eth_open(struct eth_device *dev, bd_t *bis)
396 u_int32_t clkdiv, cnt;
397 volatile emac_desc *rx_desc;
400 debug_emac("+ emac_open\n");
402 /* Reset EMAC module and disable interrupts in wrapper */
403 writel(1, &adap_emac->SOFTRESET);
404 while (readl(&adap_emac->SOFTRESET) != 0)
406 #if defined(DAVINCI_EMAC_VERSION2)
407 writel(1, &adap_ewrap->softrst);
408 while (readl(&adap_ewrap->softrst) != 0)
411 writel(0, &adap_ewrap->EWCTL);
412 for (cnt = 0; cnt < 5; cnt++) {
413 clkdiv = readl(&adap_ewrap->EWCTL);
417 #if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \
418 defined(CONFIG_MACH_DAVINCI_DA850_EVM)
419 adap_ewrap->c0rxen = adap_ewrap->c1rxen = adap_ewrap->c2rxen = 0;
420 adap_ewrap->c0txen = adap_ewrap->c1txen = adap_ewrap->c2txen = 0;
421 adap_ewrap->c0miscen = adap_ewrap->c1miscen = adap_ewrap->c2miscen = 0;
423 rx_desc = emac_rx_desc;
425 writel(1, &adap_emac->TXCONTROL);
426 writel(1, &adap_emac->RXCONTROL);
428 davinci_eth_set_mac_addr(dev);
430 /* Set DMA 8 TX / 8 RX Head pointers to 0 */
431 addr = &adap_emac->TX0HDP;
432 for(cnt = 0; cnt < 16; cnt++)
435 addr = &adap_emac->RX0HDP;
436 for(cnt = 0; cnt < 16; cnt++)
439 /* Clear Statistics (do this before setting MacControl register) */
440 addr = &adap_emac->RXGOODFRAMES;
441 for(cnt = 0; cnt < EMAC_NUM_STATS; cnt++)
444 /* No multicast addressing */
445 writel(0, &adap_emac->MACHASH1);
446 writel(0, &adap_emac->MACHASH2);
448 /* Create RX queue and set receive process in place */
449 emac_rx_active_head = emac_rx_desc;
450 for (cnt = 0; cnt < EMAC_MAX_RX_BUFFERS; cnt++) {
451 rx_desc->next = (u_int32_t)(rx_desc + 1);
452 rx_desc->buffer = &emac_rx_buffers[cnt * (EMAC_MAX_ETHERNET_PKT_SIZE + EMAC_PKT_ALIGN)];
453 rx_desc->buff_off_len = EMAC_MAX_ETHERNET_PKT_SIZE;
454 rx_desc->pkt_flag_len = EMAC_CPPI_OWNERSHIP_BIT;
458 /* Finalize the rx desc list */
461 emac_rx_active_tail = rx_desc;
462 emac_rx_queue_active = 1;
465 writel(EMAC_MAX_ETHERNET_PKT_SIZE, &adap_emac->RXMAXLEN);
466 writel(0, &adap_emac->RXBUFFEROFFSET);
469 * No fancy configs - Use this for promiscous debug
470 * - EMAC_RXMBPENABLE_RXCAFEN_ENABLE
472 writel(EMAC_RXMBPENABLE_RXBROADEN, &adap_emac->RXMBPENABLE);
474 /* Enable ch 0 only */
475 writel(1, &adap_emac->RXUNICASTSET);
477 /* Enable MII interface and Full duplex mode */
478 #ifdef CONFIG_SOC_DA8XX
479 writel((EMAC_MACCONTROL_MIIEN_ENABLE |
480 EMAC_MACCONTROL_FULLDUPLEX_ENABLE |
481 EMAC_MACCONTROL_RMIISPEED_100),
482 &adap_emac->MACCONTROL);
484 writel((EMAC_MACCONTROL_MIIEN_ENABLE |
485 EMAC_MACCONTROL_FULLDUPLEX_ENABLE),
486 &adap_emac->MACCONTROL);
489 /* Init MDIO & get link state */
490 clkdiv = CONFIG_SYS_EMAC_TI_CLKDIV;
491 writel((clkdiv & 0xff) | MDIO_CONTROL_ENABLE | MDIO_CONTROL_FAULT,
492 &adap_mdio->CONTROL);
494 /* We need to wait for MDIO to start */
497 index = get_active_phy();
501 emac_gigabit_enable(active_phy_addr[index]);
503 /* Start receive process */
504 writel((u_int32_t)emac_rx_desc, &adap_emac->RX0HDP);
506 debug_emac("- emac_open\n");
511 /* EMAC Channel Teardown */
512 static void davinci_eth_ch_teardown(int ch)
517 debug_emac("+ emac_ch_teardown\n");
519 if (ch == EMAC_CH_TX) {
520 /* Init TX channel teardown */
521 writel(0, &adap_emac->TXTEARDOWN);
524 * Wait here for Tx teardown completion interrupt to
525 * occur. Note: A task delay can be called here to pend
526 * rather than occupying CPU cycles - anyway it has
527 * been found that teardown takes very few cpu cycles
528 * and does not affect functionality
534 cnt = readl(&adap_emac->TX0CP);
535 } while (cnt != 0xfffffffc);
536 writel(cnt, &adap_emac->TX0CP);
537 writel(0, &adap_emac->TX0HDP);
539 /* Init RX channel teardown */
540 writel(0, &adap_emac->RXTEARDOWN);
543 * Wait here for Rx teardown completion interrupt to
544 * occur. Note: A task delay can be called here to pend
545 * rather than occupying CPU cycles - anyway it has
546 * been found that teardown takes very few cpu cycles
547 * and does not affect functionality
553 cnt = readl(&adap_emac->RX0CP);
554 } while (cnt != 0xfffffffc);
555 writel(cnt, &adap_emac->RX0CP);
556 writel(0, &adap_emac->RX0HDP);
559 debug_emac("- emac_ch_teardown\n");
562 /* Eth device close */
563 static void davinci_eth_close(struct eth_device *dev)
565 debug_emac("+ emac_close\n");
567 davinci_eth_ch_teardown(EMAC_CH_TX); /* TX Channel teardown */
568 davinci_eth_ch_teardown(EMAC_CH_RX); /* RX Channel teardown */
570 /* Reset EMAC module and disable interrupts in wrapper */
571 writel(1, &adap_emac->SOFTRESET);
572 #if defined(DAVINCI_EMAC_VERSION2)
573 writel(1, &adap_ewrap->softrst);
575 writel(0, &adap_ewrap->EWCTL);
578 #if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \
579 defined(CONFIG_MACH_DAVINCI_DA850_EVM)
580 adap_ewrap->c0rxen = adap_ewrap->c1rxen = adap_ewrap->c2rxen = 0;
581 adap_ewrap->c0txen = adap_ewrap->c1txen = adap_ewrap->c2txen = 0;
582 adap_ewrap->c0miscen = adap_ewrap->c1miscen = adap_ewrap->c2miscen = 0;
584 debug_emac("- emac_close\n");
587 static int tx_send_loop = 0;
590 * This function sends a single packet on the network and returns
591 * positive number (number of bytes transmitted) or negative for error
593 static int davinci_eth_send_packet (struct eth_device *dev,
594 volatile void *packet, int length)
600 index = get_active_phy();
602 printf(" WARN: emac_send_packet: No link\n");
606 emac_gigabit_enable(active_phy_addr[index]);
608 /* Check packet size and if < EMAC_MIN_ETHERNET_PKT_SIZE, pad it up */
609 if (length < EMAC_MIN_ETHERNET_PKT_SIZE) {
610 length = EMAC_MIN_ETHERNET_PKT_SIZE;
613 /* Populate the TX descriptor */
614 emac_tx_desc->next = 0;
615 emac_tx_desc->buffer = (u_int8_t *) packet;
616 emac_tx_desc->buff_off_len = (length & 0xffff);
617 emac_tx_desc->pkt_flag_len = ((length & 0xffff) |
619 EMAC_CPPI_OWNERSHIP_BIT |
621 /* Send the packet */
622 writel((unsigned long)emac_tx_desc, &adap_emac->TX0HDP);
624 /* Wait for packet to complete or link down */
626 if (!phy[index].get_link_speed(active_phy_addr[index])) {
627 davinci_eth_ch_teardown (EMAC_CH_TX);
631 emac_gigabit_enable(active_phy_addr[index]);
633 if (readl(&adap_emac->TXINTSTATRAW) & 0x01) {
644 * This function handles receipt of a packet from the network
646 static int davinci_eth_rcv_packet (struct eth_device *dev)
648 volatile emac_desc *rx_curr_desc;
649 volatile emac_desc *curr_desc;
650 volatile emac_desc *tail_desc;
651 int status, ret = -1;
653 rx_curr_desc = emac_rx_active_head;
654 status = rx_curr_desc->pkt_flag_len;
655 if ((rx_curr_desc) && ((status & EMAC_CPPI_OWNERSHIP_BIT) == 0)) {
656 if (status & EMAC_CPPI_RX_ERROR_FRAME) {
657 /* Error in packet - discard it and requeue desc */
658 printf ("WARN: emac_rcv_pkt: Error in packet\n");
660 NetReceive (rx_curr_desc->buffer,
661 (rx_curr_desc->buff_off_len & 0xffff));
662 ret = rx_curr_desc->buff_off_len & 0xffff;
665 /* Ack received packet descriptor */
666 writel((unsigned long)rx_curr_desc, &adap_emac->RX0CP);
667 curr_desc = rx_curr_desc;
668 emac_rx_active_head =
669 (volatile emac_desc *) rx_curr_desc->next;
671 if (status & EMAC_CPPI_EOQ_BIT) {
672 if (emac_rx_active_head) {
673 writel((unsigned long)emac_rx_active_head,
676 emac_rx_queue_active = 0;
677 printf ("INFO:emac_rcv_packet: RX Queue not active\n");
681 /* Recycle RX descriptor */
682 rx_curr_desc->buff_off_len = EMAC_MAX_ETHERNET_PKT_SIZE;
683 rx_curr_desc->pkt_flag_len = EMAC_CPPI_OWNERSHIP_BIT;
684 rx_curr_desc->next = 0;
686 if (emac_rx_active_head == 0) {
687 printf ("INFO: emac_rcv_pkt: active queue head = 0\n");
688 emac_rx_active_head = curr_desc;
689 emac_rx_active_tail = curr_desc;
690 if (emac_rx_queue_active != 0) {
691 writel((unsigned long)emac_rx_active_head,
693 printf ("INFO: emac_rcv_pkt: active queue head = 0, HDP fired\n");
694 emac_rx_queue_active = 1;
697 tail_desc = emac_rx_active_tail;
698 emac_rx_active_tail = curr_desc;
699 tail_desc->next = (unsigned int) curr_desc;
700 status = tail_desc->pkt_flag_len;
701 if (status & EMAC_CPPI_EOQ_BIT) {
702 writel((unsigned long)curr_desc,
704 status &= ~EMAC_CPPI_EOQ_BIT;
705 tail_desc->pkt_flag_len = status;
714 * This function initializes the emac hardware. It does NOT initialize
715 * EMAC modules power or pin multiplexors, that is done by board_init()
716 * much earlier in bootup process. Returns 1 on success, 0 otherwise.
718 int davinci_emac_initialize(void)
724 struct eth_device *dev;
726 dev = malloc(sizeof *dev);
731 memset(dev, 0, sizeof *dev);
732 sprintf(dev->name, "DaVinci-EMAC");
735 dev->init = davinci_eth_open;
736 dev->halt = davinci_eth_close;
737 dev->send = davinci_eth_send_packet;
738 dev->recv = davinci_eth_rcv_packet;
739 dev->write_hwaddr = davinci_eth_set_mac_addr;
743 davinci_eth_mdio_enable();
745 /* let the EMAC detect the PHYs */
748 for (i = 0; i < 256; i++) {
749 if (readl(&adap_mdio->ALIVE))
755 printf("No ETH PHY detected!!!\n");
759 /* Find if PHY(s) is/are connected */
760 ret = davinci_eth_phy_detect();
764 debug_emac(" %d ETH PHY detected\n", ret);
766 /* Get PHY ID and initialize phy_ops for a detected PHY */
767 for (i = 0; i < num_phy; i++) {
768 if (!davinci_eth_phy_read(active_phy_addr[i], MII_PHYSID1,
770 active_phy_addr[i] = 0xff;
774 phy_id = (tmp << 16) & 0xffff0000;
776 if (!davinci_eth_phy_read(active_phy_addr[i], MII_PHYSID2,
778 active_phy_addr[i] = 0xff;
782 phy_id |= tmp & 0x0000ffff;
786 sprintf(phy[i].name, "KSZ8873 @ 0x%02x",
788 phy[i].init = ksz8873_init_phy;
789 phy[i].is_phy_connected = ksz8873_is_phy_connected;
790 phy[i].get_link_speed = ksz8873_get_link_speed;
791 phy[i].auto_negotiate = ksz8873_auto_negotiate;
794 sprintf(phy[i].name, "LXT972 @ 0x%02x",
796 phy[i].init = lxt972_init_phy;
797 phy[i].is_phy_connected = lxt972_is_phy_connected;
798 phy[i].get_link_speed = lxt972_get_link_speed;
799 phy[i].auto_negotiate = lxt972_auto_negotiate;
802 sprintf(phy[i].name, "DP83848 @ 0x%02x",
804 phy[i].init = dp83848_init_phy;
805 phy[i].is_phy_connected = dp83848_is_phy_connected;
806 phy[i].get_link_speed = dp83848_get_link_speed;
807 phy[i].auto_negotiate = dp83848_auto_negotiate;
810 sprintf(phy[i].name, "ET1011C @ 0x%02x",
812 phy[i].init = gen_init_phy;
813 phy[i].is_phy_connected = gen_is_phy_connected;
814 phy[i].get_link_speed = et1011c_get_link_speed;
815 phy[i].auto_negotiate = gen_auto_negotiate;
818 sprintf(phy[i].name, "GENERIC @ 0x%02x",
820 phy[i].init = gen_init_phy;
821 phy[i].is_phy_connected = gen_is_phy_connected;
822 phy[i].get_link_speed = gen_get_link_speed;
823 phy[i].auto_negotiate = gen_auto_negotiate;
826 debug("Ethernet PHY: %s\n", phy[i].name);
828 miiphy_register(phy[i].name, davinci_mii_phy_read,
829 davinci_mii_phy_write);