2 * CPSW Ethernet Switch Driver
4 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
24 #include <asm/errno.h>
27 #include <asm/arch/cpu.h>
29 #include <fdt_support.h>
31 DECLARE_GLOBAL_DATA_PTR;
33 #define BITMASK(bits) (BIT(bits) - 1)
34 #define PHY_REG_MASK 0x1f
35 #define PHY_ID_MASK 0x1f
36 #define NUM_DESCS (PKTBUFSRX * 2)
38 #define PKT_MAX (1500 + 14 + 4 + 4)
40 #define GIGABITEN BIT(7)
41 #define FULLDUPLEXEN BIT(0)
45 #define CPSW_HOST_PORT_OFFSET 0x108
46 #define CPSW_SLAVE0_OFFSET 0x208
47 #define CPSW_SLAVE1_OFFSET 0x308
48 #define CPSW_SLAVE_SIZE 0x100
49 #define CPSW_CPDMA_OFFSET 0x800
50 #define CPSW_HW_STATS 0x900
51 #define CPSW_STATERAM_OFFSET 0xa00
52 #define CPSW_CPTS_OFFSET 0xc00
53 #define CPSW_ALE_OFFSET 0xd00
54 #define CPSW_SLIVER0_OFFSET 0xd80
55 #define CPSW_SLIVER1_OFFSET 0xdc0
56 #define CPSW_BD_OFFSET 0x2000
57 #define CPSW_MDIO_DIV 0xff
59 #define AM335X_GMII_SEL_OFFSET 0x630
62 #define CPDMA_TXCONTROL 0x004
63 #define CPDMA_RXCONTROL 0x014
64 #define CPDMA_SOFTRESET 0x01c
65 #define CPDMA_RXFREE 0x0e0
66 #define CPDMA_TXHDP_VER1 0x100
67 #define CPDMA_TXHDP_VER2 0x200
68 #define CPDMA_RXHDP_VER1 0x120
69 #define CPDMA_RXHDP_VER2 0x220
70 #define CPDMA_TXCP_VER1 0x140
71 #define CPDMA_TXCP_VER2 0x240
72 #define CPDMA_RXCP_VER1 0x160
73 #define CPDMA_RXCP_VER2 0x260
75 /* Descriptor mode bits */
76 #define CPDMA_DESC_SOP BIT(31)
77 #define CPDMA_DESC_EOP BIT(30)
78 #define CPDMA_DESC_OWNER BIT(29)
79 #define CPDMA_DESC_EOQ BIT(28)
82 * This timeout definition is a worst-case ultra defensive measure against
83 * unexpected controller lock ups. Ideally, we should never ever hit this
84 * scenario in practice.
86 #define MDIO_TIMEOUT 100 /* msecs */
87 #define CPDMA_TIMEOUT 100 /* msecs */
89 struct cpsw_mdio_regs {
92 #define CONTROL_IDLE BIT(31)
93 #define CONTROL_ENABLE BIT(30)
104 u32 __reserved_1[20];
109 #define USERACCESS_GO BIT(31)
110 #define USERACCESS_WRITE BIT(30)
111 #define USERACCESS_ACK BIT(29)
112 #define USERACCESS_READ (0)
113 #define USERACCESS_DATA (0xffff)
125 struct cpsw_slave_regs {
133 #elif defined(CONFIG_TI814X)
142 struct cpsw_host_regs {
148 u32 cpdma_tx_pri_map;
149 u32 cpdma_rx_chan_map;
152 struct cpsw_sliver_regs {
165 #define ALE_ENTRY_BITS 68
166 #define ALE_ENTRY_WORDS DIV_ROUND_UP(ALE_ENTRY_BITS, 32)
169 #define ALE_CONTROL 0x08
170 #define ALE_UNKNOWNVLAN 0x18
171 #define ALE_TABLE_CONTROL 0x20
172 #define ALE_TABLE 0x34
173 #define ALE_PORTCTL 0x40
175 #define ALE_TABLE_WRITE BIT(31)
177 #define ALE_TYPE_FREE 0
178 #define ALE_TYPE_ADDR 1
179 #define ALE_TYPE_VLAN 2
180 #define ALE_TYPE_VLAN_ADDR 3
182 #define ALE_UCAST_PERSISTANT 0
183 #define ALE_UCAST_UNTOUCHED 1
184 #define ALE_UCAST_OUI 2
185 #define ALE_UCAST_TOUCHED 3
187 #define ALE_MCAST_FWD 0
188 #define ALE_MCAST_BLOCK_LEARN_FWD 1
189 #define ALE_MCAST_FWD_LEARN 2
190 #define ALE_MCAST_FWD_2 3
192 enum cpsw_ale_port_state {
193 ALE_PORT_STATE_DISABLE = 0x00,
194 ALE_PORT_STATE_BLOCK = 0x01,
195 ALE_PORT_STATE_LEARN = 0x02,
196 ALE_PORT_STATE_FORWARD = 0x03,
199 /* ALE unicast entry flags - passed into cpsw_ale_add_ucast() */
201 #define ALE_BLOCKED 2
204 struct cpsw_slave_regs *regs;
205 struct cpsw_sliver_regs *sliver;
208 struct cpsw_slave_data *data;
212 /* hardware fields */
217 /* software fields */
223 struct cpdma_desc *head, *tail;
224 void *hdp, *cp, *rxfree;
227 #define desc_write(desc, fld, val) __raw_writel((u32)(val), &(desc)->fld)
228 #define desc_read(desc, fld) __raw_readl(&(desc)->fld)
229 #define desc_read_ptr(desc, fld) ((void *)__raw_readl(&(desc)->fld))
231 #define chan_write(chan, fld, val) __raw_writel((u32)(val), (chan)->fld)
232 #define chan_read(chan, fld) __raw_readl((chan)->fld)
233 #define chan_read_ptr(chan, fld) ((void *)__raw_readl((chan)->fld))
235 #define for_active_slave(slave, priv) \
236 slave = (priv)->slaves + (priv)->data.active_slave; if (slave)
237 #define for_each_slave(slave, priv) \
238 for (slave = (priv)->slaves; slave != (priv)->slaves + \
239 (priv)->data.slaves; slave++)
245 struct eth_device *dev;
247 struct cpsw_platform_data data;
250 struct cpsw_regs *regs;
252 struct cpsw_host_regs *host_port_regs;
255 struct cpdma_desc *descs;
256 struct cpdma_desc *desc_free;
257 struct cpdma_chan rx_chan, tx_chan;
259 struct cpsw_slave *slaves;
260 struct phy_device *phydev;
266 static inline int cpsw_ale_get_field(u32 *ale_entry, u32 start, u32 bits)
272 idx = 2 - idx; /* flip */
273 return (ale_entry[idx] >> start) & BITMASK(bits);
276 static inline void cpsw_ale_set_field(u32 *ale_entry, u32 start, u32 bits,
281 value &= BITMASK(bits);
284 idx = 2 - idx; /* flip */
285 ale_entry[idx] &= ~(BITMASK(bits) << start);
286 ale_entry[idx] |= (value << start);
289 #define DEFINE_ALE_FIELD(name, start, bits) \
290 static inline int cpsw_ale_get_##name(u32 *ale_entry) \
292 return cpsw_ale_get_field(ale_entry, start, bits); \
294 static inline void cpsw_ale_set_##name(u32 *ale_entry, u32 value) \
296 cpsw_ale_set_field(ale_entry, start, bits, value); \
299 DEFINE_ALE_FIELD(entry_type, 60, 2)
300 DEFINE_ALE_FIELD(mcast_state, 62, 2)
301 DEFINE_ALE_FIELD(port_mask, 66, 3)
302 DEFINE_ALE_FIELD(ucast_type, 62, 2)
303 DEFINE_ALE_FIELD(port_num, 66, 2)
304 DEFINE_ALE_FIELD(blocked, 65, 1)
305 DEFINE_ALE_FIELD(secure, 64, 1)
306 DEFINE_ALE_FIELD(mcast, 40, 1)
308 /* The MAC address field in the ALE entry cannot be macroized as above */
309 static inline void cpsw_ale_get_addr(u32 *ale_entry, u8 *addr)
313 for (i = 0; i < 6; i++)
314 addr[i] = cpsw_ale_get_field(ale_entry, 40 - 8*i, 8);
317 static inline void cpsw_ale_set_addr(u32 *ale_entry, const u8 *addr)
321 for (i = 0; i < 6; i++)
322 cpsw_ale_set_field(ale_entry, 40 - 8*i, 8, addr[i]);
325 static int cpsw_ale_read(struct cpsw_priv *priv, int idx, u32 *ale_entry)
329 __raw_writel(idx, priv->ale_regs + ALE_TABLE_CONTROL);
331 for (i = 0; i < ALE_ENTRY_WORDS; i++)
332 ale_entry[i] = __raw_readl(priv->ale_regs + ALE_TABLE + 4 * i);
337 static int cpsw_ale_write(struct cpsw_priv *priv, int idx, u32 *ale_entry)
341 for (i = 0; i < ALE_ENTRY_WORDS; i++)
342 __raw_writel(ale_entry[i], priv->ale_regs + ALE_TABLE + 4 * i);
344 __raw_writel(idx | ALE_TABLE_WRITE, priv->ale_regs + ALE_TABLE_CONTROL);
349 static int cpsw_ale_match_addr(struct cpsw_priv *priv, const u8 *addr)
351 u32 ale_entry[ALE_ENTRY_WORDS];
354 for (idx = 0; idx < priv->data.ale_entries; idx++) {
357 cpsw_ale_read(priv, idx, ale_entry);
358 type = cpsw_ale_get_entry_type(ale_entry);
359 if (type != ALE_TYPE_ADDR && type != ALE_TYPE_VLAN_ADDR)
361 cpsw_ale_get_addr(ale_entry, entry_addr);
362 if (memcmp(entry_addr, addr, 6) == 0)
368 static int cpsw_ale_match_free(struct cpsw_priv *priv)
370 u32 ale_entry[ALE_ENTRY_WORDS];
373 for (idx = 0; idx < priv->data.ale_entries; idx++) {
374 cpsw_ale_read(priv, idx, ale_entry);
375 type = cpsw_ale_get_entry_type(ale_entry);
376 if (type == ALE_TYPE_FREE)
382 static int cpsw_ale_find_ageable(struct cpsw_priv *priv)
384 u32 ale_entry[ALE_ENTRY_WORDS];
387 for (idx = 0; idx < priv->data.ale_entries; idx++) {
388 cpsw_ale_read(priv, idx, ale_entry);
389 type = cpsw_ale_get_entry_type(ale_entry);
390 if (type != ALE_TYPE_ADDR && type != ALE_TYPE_VLAN_ADDR)
392 if (cpsw_ale_get_mcast(ale_entry))
394 type = cpsw_ale_get_ucast_type(ale_entry);
395 if (type != ALE_UCAST_PERSISTANT &&
396 type != ALE_UCAST_OUI)
402 static int cpsw_ale_add_ucast(struct cpsw_priv *priv, const u8 *addr,
405 u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
408 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_ADDR);
409 cpsw_ale_set_addr(ale_entry, addr);
410 cpsw_ale_set_ucast_type(ale_entry, ALE_UCAST_PERSISTANT);
411 cpsw_ale_set_secure(ale_entry, (flags & ALE_SECURE) ? 1 : 0);
412 cpsw_ale_set_blocked(ale_entry, (flags & ALE_BLOCKED) ? 1 : 0);
413 cpsw_ale_set_port_num(ale_entry, port);
415 idx = cpsw_ale_match_addr(priv, addr);
417 idx = cpsw_ale_match_free(priv);
419 idx = cpsw_ale_find_ageable(priv);
423 cpsw_ale_write(priv, idx, ale_entry);
427 static int cpsw_ale_add_mcast(struct cpsw_priv *priv, const u8 *addr,
430 u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
433 idx = cpsw_ale_match_addr(priv, addr);
435 cpsw_ale_read(priv, idx, ale_entry);
437 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_ADDR);
438 cpsw_ale_set_addr(ale_entry, addr);
439 cpsw_ale_set_mcast_state(ale_entry, ALE_MCAST_FWD_2);
441 mask = cpsw_ale_get_port_mask(ale_entry);
443 cpsw_ale_set_port_mask(ale_entry, port_mask);
446 idx = cpsw_ale_match_free(priv);
448 idx = cpsw_ale_find_ageable(priv);
452 cpsw_ale_write(priv, idx, ale_entry);
456 static inline void cpsw_ale_control(struct cpsw_priv *priv, int bit, int val)
458 u32 tmp, mask = BIT(bit);
460 tmp = __raw_readl(priv->ale_regs + ALE_CONTROL);
462 tmp |= val ? mask : 0;
463 __raw_writel(tmp, priv->ale_regs + ALE_CONTROL);
466 #define cpsw_ale_enable(priv, val) cpsw_ale_control(priv, 31, val)
467 #define cpsw_ale_clear(priv, val) cpsw_ale_control(priv, 30, val)
468 #define cpsw_ale_vlan_aware(priv, val) cpsw_ale_control(priv, 2, val)
470 static inline void cpsw_ale_port_state(struct cpsw_priv *priv, int port,
473 int offset = ALE_PORTCTL + 4 * port;
476 tmp = __raw_readl(priv->ale_regs + offset);
479 __raw_writel(tmp, priv->ale_regs + offset);
482 static struct cpsw_mdio_regs *mdio_regs;
484 /* wait until hardware is ready for another user access */
485 static inline u32 wait_for_user_access(void)
488 int timeout = MDIO_TIMEOUT;
491 ((reg = __raw_readl(&mdio_regs->user[0].access)) & USERACCESS_GO))
495 printf("wait_for_user_access Timeout\n");
501 /* wait until hardware state machine is idle */
502 static inline void wait_for_idle(void)
504 int timeout = MDIO_TIMEOUT;
507 ((__raw_readl(&mdio_regs->control) & CONTROL_IDLE) == 0))
511 printf("wait_for_idle Timeout\n");
514 static int cpsw_mdio_read(struct mii_dev *bus, int phy_id,
515 int dev_addr, int phy_reg)
520 if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK)
523 wait_for_user_access();
524 reg = (USERACCESS_GO | USERACCESS_READ | (phy_reg << 21) |
526 __raw_writel(reg, &mdio_regs->user[0].access);
527 reg = wait_for_user_access();
529 data = (reg & USERACCESS_ACK) ? (reg & USERACCESS_DATA) : -1;
533 static int cpsw_mdio_write(struct mii_dev *bus, int phy_id, int dev_addr,
534 int phy_reg, u16 data)
538 if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK)
541 wait_for_user_access();
542 reg = (USERACCESS_GO | USERACCESS_WRITE | (phy_reg << 21) |
543 (phy_id << 16) | (data & USERACCESS_DATA));
544 __raw_writel(reg, &mdio_regs->user[0].access);
545 wait_for_user_access();
550 static void cpsw_mdio_init(const char *name, u32 mdio_base, u32 div)
552 struct mii_dev *bus = mdio_alloc();
554 mdio_regs = (struct cpsw_mdio_regs *)mdio_base;
556 /* set enable and clock divider */
557 __raw_writel(div | CONTROL_ENABLE, &mdio_regs->control);
560 * wait for scan logic to settle:
561 * the scan time consists of (a) a large fixed component, and (b) a
562 * small component that varies with the mii bus frequency. These
563 * were estimated using measurements at 1.1 and 2.2 MHz on tnetv107x
564 * silicon. Since the effect of (b) was found to be largely
565 * negligible, we keep things simple here.
569 bus->read = cpsw_mdio_read;
570 bus->write = cpsw_mdio_write;
571 strcpy(bus->name, name);
576 /* Set a self-clearing bit in a register, and wait for it to clear */
577 static inline void setbit_and_wait_for_clear32(void *addr)
579 __raw_writel(CLEAR_BIT, addr);
580 while (__raw_readl(addr) & CLEAR_BIT)
584 #define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \
585 ((mac)[2] << 16) | ((mac)[3] << 24))
586 #define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8))
588 static void cpsw_set_slave_mac(struct cpsw_slave *slave,
589 struct cpsw_priv *priv)
592 struct eth_pdata *pdata = dev_get_platdata(priv->dev);
594 writel(mac_hi(pdata->enetaddr), &slave->regs->sa_hi);
595 writel(mac_lo(pdata->enetaddr), &slave->regs->sa_lo);
597 __raw_writel(mac_hi(priv->dev->enetaddr), &slave->regs->sa_hi);
598 __raw_writel(mac_lo(priv->dev->enetaddr), &slave->regs->sa_lo);
602 static void cpsw_slave_update_link(struct cpsw_slave *slave,
603 struct cpsw_priv *priv, int *link)
605 struct phy_device *phy;
616 if (*link) { /* link up */
617 mac_control = priv->data.mac_control;
618 if (phy->speed == 1000)
619 mac_control |= GIGABITEN;
620 if (phy->duplex == DUPLEX_FULL)
621 mac_control |= FULLDUPLEXEN;
622 if (phy->speed == 100)
623 mac_control |= MIIEN;
626 if (mac_control == slave->mac_control)
630 printf("link up on port %d, speed %d, %s duplex\n",
631 slave->slave_num, phy->speed,
632 (phy->duplex == DUPLEX_FULL) ? "full" : "half");
634 printf("link down on port %d\n", slave->slave_num);
637 __raw_writel(mac_control, &slave->sliver->mac_control);
638 slave->mac_control = mac_control;
641 static int cpsw_update_link(struct cpsw_priv *priv)
644 struct cpsw_slave *slave;
646 for_active_slave(slave, priv)
647 cpsw_slave_update_link(slave, priv, &link);
652 static inline u32 cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num)
654 if (priv->host_port == 0)
655 return slave_num + 1;
660 static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv)
664 setbit_and_wait_for_clear32(&slave->sliver->soft_reset);
666 /* setup priority mapping */
667 __raw_writel(0x76543210, &slave->sliver->rx_pri_map);
668 __raw_writel(0x33221100, &slave->regs->tx_pri_map);
670 /* setup max packet size, and mac address */
671 __raw_writel(PKT_MAX, &slave->sliver->rx_maxlen);
672 cpsw_set_slave_mac(slave, priv);
674 slave->mac_control = 0; /* no link yet */
676 /* enable forwarding */
677 slave_port = cpsw_get_slave_port(priv, slave->slave_num);
678 cpsw_ale_port_state(priv, slave_port, ALE_PORT_STATE_FORWARD);
680 cpsw_ale_add_mcast(priv, net_bcast_ethaddr, 1 << slave_port);
682 priv->phy_mask |= 1 << slave->data->phy_addr;
685 static struct cpdma_desc *cpdma_desc_alloc(struct cpsw_priv *priv)
687 struct cpdma_desc *desc = priv->desc_free;
690 priv->desc_free = desc_read_ptr(desc, hw_next);
694 static void cpdma_desc_free(struct cpsw_priv *priv, struct cpdma_desc *desc)
697 desc_write(desc, hw_next, priv->desc_free);
698 priv->desc_free = desc;
702 static int cpdma_submit(struct cpsw_priv *priv, struct cpdma_chan *chan,
703 void *buffer, int len)
705 struct cpdma_desc *desc, *prev;
708 desc = cpdma_desc_alloc(priv);
715 mode = CPDMA_DESC_OWNER | CPDMA_DESC_SOP | CPDMA_DESC_EOP;
717 desc_write(desc, hw_next, 0);
718 desc_write(desc, hw_buffer, buffer);
719 desc_write(desc, hw_len, len);
720 desc_write(desc, hw_mode, mode | len);
721 desc_write(desc, sw_buffer, buffer);
722 desc_write(desc, sw_len, len);
725 /* simple case - first packet enqueued */
728 chan_write(chan, hdp, desc);
732 /* not the first packet - enqueue at the tail */
734 desc_write(prev, hw_next, desc);
737 /* next check if EOQ has been triggered already */
738 if (desc_read(prev, hw_mode) & CPDMA_DESC_EOQ)
739 chan_write(chan, hdp, desc);
743 chan_write(chan, rxfree, 1);
747 static int cpdma_process(struct cpsw_priv *priv, struct cpdma_chan *chan,
748 void **buffer, int *len)
750 struct cpdma_desc *desc = chan->head;
756 status = desc_read(desc, hw_mode);
759 *len = status & 0x7ff;
762 *buffer = desc_read_ptr(desc, sw_buffer);
764 if (status & CPDMA_DESC_OWNER) {
765 if (chan_read(chan, hdp) == 0) {
766 if (desc_read(desc, hw_mode) & CPDMA_DESC_OWNER)
767 chan_write(chan, hdp, desc);
773 chan->head = desc_read_ptr(desc, hw_next);
774 chan_write(chan, cp, desc);
776 cpdma_desc_free(priv, desc);
780 static int _cpsw_init(struct cpsw_priv *priv, u8 *enetaddr)
782 struct cpsw_slave *slave;
785 /* soft reset the controller and initialize priv */
786 setbit_and_wait_for_clear32(&priv->regs->soft_reset);
788 /* initialize and reset the address lookup engine */
789 cpsw_ale_enable(priv, 1);
790 cpsw_ale_clear(priv, 1);
791 cpsw_ale_vlan_aware(priv, 0); /* vlan unaware mode */
793 /* setup host port priority mapping */
794 __raw_writel(0x76543210, &priv->host_port_regs->cpdma_tx_pri_map);
795 __raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map);
797 /* disable priority elevation and enable statistics on all ports */
798 __raw_writel(0, &priv->regs->ptype);
800 /* enable statistics collection only on the host port */
801 __raw_writel(BIT(priv->host_port), &priv->regs->stat_port_en);
802 __raw_writel(0x7, &priv->regs->stat_port_en);
804 cpsw_ale_port_state(priv, priv->host_port, ALE_PORT_STATE_FORWARD);
806 cpsw_ale_add_ucast(priv, enetaddr, priv->host_port, ALE_SECURE);
807 cpsw_ale_add_mcast(priv, net_bcast_ethaddr, 1 << priv->host_port);
809 for_active_slave(slave, priv)
810 cpsw_slave_init(slave, priv);
812 cpsw_update_link(priv);
814 /* init descriptor pool */
815 for (i = 0; i < NUM_DESCS; i++) {
816 desc_write(&priv->descs[i], hw_next,
817 (i == (NUM_DESCS - 1)) ? 0 : &priv->descs[i+1]);
819 priv->desc_free = &priv->descs[0];
821 /* initialize channels */
822 if (priv->data.version == CPSW_CTRL_VERSION_2) {
823 memset(&priv->rx_chan, 0, sizeof(struct cpdma_chan));
824 priv->rx_chan.hdp = priv->dma_regs + CPDMA_RXHDP_VER2;
825 priv->rx_chan.cp = priv->dma_regs + CPDMA_RXCP_VER2;
826 priv->rx_chan.rxfree = priv->dma_regs + CPDMA_RXFREE;
828 memset(&priv->tx_chan, 0, sizeof(struct cpdma_chan));
829 priv->tx_chan.hdp = priv->dma_regs + CPDMA_TXHDP_VER2;
830 priv->tx_chan.cp = priv->dma_regs + CPDMA_TXCP_VER2;
832 memset(&priv->rx_chan, 0, sizeof(struct cpdma_chan));
833 priv->rx_chan.hdp = priv->dma_regs + CPDMA_RXHDP_VER1;
834 priv->rx_chan.cp = priv->dma_regs + CPDMA_RXCP_VER1;
835 priv->rx_chan.rxfree = priv->dma_regs + CPDMA_RXFREE;
837 memset(&priv->tx_chan, 0, sizeof(struct cpdma_chan));
838 priv->tx_chan.hdp = priv->dma_regs + CPDMA_TXHDP_VER1;
839 priv->tx_chan.cp = priv->dma_regs + CPDMA_TXCP_VER1;
842 /* clear dma state */
843 setbit_and_wait_for_clear32(priv->dma_regs + CPDMA_SOFTRESET);
845 if (priv->data.version == CPSW_CTRL_VERSION_2) {
846 for (i = 0; i < priv->data.channels; i++) {
847 __raw_writel(0, priv->dma_regs + CPDMA_RXHDP_VER2 + 4
849 __raw_writel(0, priv->dma_regs + CPDMA_RXFREE + 4
851 __raw_writel(0, priv->dma_regs + CPDMA_RXCP_VER2 + 4
853 __raw_writel(0, priv->dma_regs + CPDMA_TXHDP_VER2 + 4
855 __raw_writel(0, priv->dma_regs + CPDMA_TXCP_VER2 + 4
859 for (i = 0; i < priv->data.channels; i++) {
860 __raw_writel(0, priv->dma_regs + CPDMA_RXHDP_VER1 + 4
862 __raw_writel(0, priv->dma_regs + CPDMA_RXFREE + 4
864 __raw_writel(0, priv->dma_regs + CPDMA_RXCP_VER1 + 4
866 __raw_writel(0, priv->dma_regs + CPDMA_TXHDP_VER1 + 4
868 __raw_writel(0, priv->dma_regs + CPDMA_TXCP_VER1 + 4
874 __raw_writel(1, priv->dma_regs + CPDMA_TXCONTROL);
875 __raw_writel(1, priv->dma_regs + CPDMA_RXCONTROL);
877 /* submit rx descs */
878 for (i = 0; i < PKTBUFSRX; i++) {
879 ret = cpdma_submit(priv, &priv->rx_chan, net_rx_packets[i],
882 printf("error %d submitting rx desc\n", ret);
890 static void _cpsw_halt(struct cpsw_priv *priv)
892 writel(0, priv->dma_regs + CPDMA_TXCONTROL);
893 writel(0, priv->dma_regs + CPDMA_RXCONTROL);
895 /* soft reset the controller and initialize priv */
896 setbit_and_wait_for_clear32(&priv->regs->soft_reset);
898 /* clear dma state */
899 setbit_and_wait_for_clear32(priv->dma_regs + CPDMA_SOFTRESET);
903 static int _cpsw_send(struct cpsw_priv *priv, void *packet, int length)
907 int timeout = CPDMA_TIMEOUT;
909 flush_dcache_range((unsigned long)packet,
910 (unsigned long)packet + length);
912 /* first reap completed packets */
914 (cpdma_process(priv, &priv->tx_chan, &buffer, &len) >= 0))
918 printf("cpdma_process timeout\n");
922 return cpdma_submit(priv, &priv->tx_chan, packet, length);
925 static int _cpsw_recv(struct cpsw_priv *priv, uchar **pkt)
931 ret = cpdma_process(priv, &priv->rx_chan, &buffer, &len);
935 invalidate_dcache_range((unsigned long)buffer,
936 (unsigned long)buffer + PKTSIZE_ALIGN);
942 static void cpsw_slave_setup(struct cpsw_slave *slave, int slave_num,
943 struct cpsw_priv *priv)
945 void *regs = priv->regs;
946 struct cpsw_slave_data *data = priv->data.slave_data + slave_num;
947 slave->slave_num = slave_num;
949 slave->regs = regs + data->slave_reg_ofs;
950 slave->sliver = regs + data->sliver_reg_ofs;
953 static int cpsw_phy_init(struct cpsw_priv *priv, struct cpsw_slave *slave)
955 struct phy_device *phydev;
956 u32 supported = PHY_GBIT_FEATURES;
958 phydev = phy_connect(priv->bus,
959 slave->data->phy_addr,
961 slave->data->phy_if);
966 phydev->supported &= supported;
967 phydev->advertising = phydev->supported;
970 if (slave->data->phy_of_handle)
971 phydev->dev->of_offset = slave->data->phy_of_handle;
974 priv->phydev = phydev;
980 int _cpsw_register(struct cpsw_priv *priv)
982 struct cpsw_slave *slave;
983 struct cpsw_platform_data *data = &priv->data;
984 void *regs = (void *)data->cpsw_base;
986 priv->slaves = malloc(sizeof(struct cpsw_slave) * data->slaves);
991 priv->host_port = data->host_port_num;
993 priv->host_port_regs = regs + data->host_port_reg_ofs;
994 priv->dma_regs = regs + data->cpdma_reg_ofs;
995 priv->ale_regs = regs + data->ale_reg_ofs;
996 priv->descs = (void *)regs + data->bd_ram_ofs;
1000 for_each_slave(slave, priv) {
1001 cpsw_slave_setup(slave, idx, priv);
1005 cpsw_mdio_init(priv->dev->name, data->mdio_base, data->mdio_div);
1006 priv->bus = miiphy_get_dev_by_name(priv->dev->name);
1007 for_active_slave(slave, priv)
1008 cpsw_phy_init(priv, slave);
1013 #ifndef CONFIG_DM_ETH
1014 static int cpsw_init(struct eth_device *dev, bd_t *bis)
1016 struct cpsw_priv *priv = dev->priv;
1018 return _cpsw_init(priv, dev->enetaddr);
1021 static void cpsw_halt(struct eth_device *dev)
1023 struct cpsw_priv *priv = dev->priv;
1025 return _cpsw_halt(priv);
1028 static int cpsw_send(struct eth_device *dev, void *packet, int length)
1030 struct cpsw_priv *priv = dev->priv;
1032 return _cpsw_send(priv, packet, length);
1035 static int cpsw_recv(struct eth_device *dev)
1037 struct cpsw_priv *priv = dev->priv;
1041 len = _cpsw_recv(priv, &pkt);
1044 net_process_received_packet(pkt, len);
1045 cpdma_submit(priv, &priv->rx_chan, pkt, PKTSIZE);
1051 int cpsw_register(struct cpsw_platform_data *data)
1053 struct cpsw_priv *priv;
1054 struct eth_device *dev;
1057 dev = calloc(sizeof(*dev), 1);
1061 priv = calloc(sizeof(*priv), 1);
1070 strcpy(dev->name, "cpsw");
1072 dev->init = cpsw_init;
1073 dev->halt = cpsw_halt;
1074 dev->send = cpsw_send;
1075 dev->recv = cpsw_recv;
1080 ret = _cpsw_register(priv);
1082 eth_unregister(dev);
1091 static int cpsw_eth_start(struct udevice *dev)
1093 struct eth_pdata *pdata = dev_get_platdata(dev);
1094 struct cpsw_priv *priv = dev_get_priv(dev);
1096 return _cpsw_init(priv, pdata->enetaddr);
1099 static int cpsw_eth_send(struct udevice *dev, void *packet, int length)
1101 struct cpsw_priv *priv = dev_get_priv(dev);
1103 return _cpsw_send(priv, packet, length);
1106 static int cpsw_eth_recv(struct udevice *dev, int flags, uchar **packetp)
1108 struct cpsw_priv *priv = dev_get_priv(dev);
1110 return _cpsw_recv(priv, packetp);
1113 static int cpsw_eth_free_pkt(struct udevice *dev, uchar *packet,
1116 struct cpsw_priv *priv = dev_get_priv(dev);
1118 return cpdma_submit(priv, &priv->rx_chan, packet, PKTSIZE);
1121 static void cpsw_eth_stop(struct udevice *dev)
1123 struct cpsw_priv *priv = dev_get_priv(dev);
1125 return _cpsw_halt(priv);
1129 static int cpsw_eth_probe(struct udevice *dev)
1131 struct cpsw_priv *priv = dev_get_priv(dev);
1135 return _cpsw_register(priv);
1138 static const struct eth_ops cpsw_eth_ops = {
1139 .start = cpsw_eth_start,
1140 .send = cpsw_eth_send,
1141 .recv = cpsw_eth_recv,
1142 .free_pkt = cpsw_eth_free_pkt,
1143 .stop = cpsw_eth_stop,
1146 static inline fdt_addr_t cpsw_get_addr_by_node(const void *fdt, int node)
1148 return fdtdec_get_addr_size_auto_noparent(fdt, node, "reg", 0, NULL);
1151 static int cpsw_eth_ofdata_to_platdata(struct udevice *dev)
1153 struct eth_pdata *pdata = dev_get_platdata(dev);
1154 struct cpsw_priv *priv = dev_get_priv(dev);
1155 const char *phy_mode;
1156 const void *fdt = gd->fdt_blob;
1157 int node = dev->of_offset;
1159 int slave_index = 0;
1163 pdata->iobase = dev_get_addr(dev);
1164 priv->data.version = CPSW_CTRL_VERSION_2;
1165 priv->data.bd_ram_ofs = CPSW_BD_OFFSET;
1166 priv->data.ale_reg_ofs = CPSW_ALE_OFFSET;
1167 priv->data.cpdma_reg_ofs = CPSW_CPDMA_OFFSET;
1168 priv->data.mdio_div = CPSW_MDIO_DIV;
1169 priv->data.host_port_reg_ofs = CPSW_HOST_PORT_OFFSET,
1171 pdata->phy_interface = -1;
1173 priv->data.cpsw_base = pdata->iobase;
1174 priv->data.channels = fdtdec_get_int(fdt, node, "cpdma_channels", -1);
1175 if (priv->data.channels <= 0) {
1176 printf("error: cpdma_channels not found in dt\n");
1180 priv->data.slaves = fdtdec_get_int(fdt, node, "slaves", -1);
1181 if (priv->data.slaves <= 0) {
1182 printf("error: slaves not found in dt\n");
1185 priv->data.slave_data = malloc(sizeof(struct cpsw_slave_data) *
1188 priv->data.ale_entries = fdtdec_get_int(fdt, node, "ale_entries", -1);
1189 if (priv->data.ale_entries <= 0) {
1190 printf("error: ale_entries not found in dt\n");
1194 priv->data.bd_ram_ofs = fdtdec_get_int(fdt, node, "bd_ram_size", -1);
1195 if (priv->data.bd_ram_ofs <= 0) {
1196 printf("error: bd_ram_size not found in dt\n");
1200 priv->data.mac_control = fdtdec_get_int(fdt, node, "mac_control", -1);
1201 if (priv->data.mac_control <= 0) {
1202 printf("error: ale_entries not found in dt\n");
1206 active_slave = fdtdec_get_int(fdt, node, "active_slave", 0);
1207 priv->data.active_slave = active_slave;
1209 fdt_for_each_subnode(fdt, subnode, node) {
1213 name = fdt_get_name(fdt, subnode, &len);
1214 if (!strncmp(name, "mdio", 4)) {
1217 mdio_base = cpsw_get_addr_by_node(fdt, subnode);
1218 if (mdio_base == FDT_ADDR_T_NONE) {
1219 error("Not able to get MDIO address space\n");
1222 priv->data.mdio_base = mdio_base;
1225 if (!strncmp(name, "slave", 5)) {
1228 if (slave_index >= priv->data.slaves)
1230 phy_mode = fdt_getprop(fdt, subnode, "phy-mode", NULL);
1232 priv->data.slave_data[slave_index].phy_if =
1233 phy_get_interface_by_name(phy_mode);
1235 priv->data.slave_data[slave_index].phy_of_handle =
1236 fdtdec_lookup_phandle(fdt, subnode,
1239 if (priv->data.slave_data[slave_index].phy_of_handle >= 0) {
1240 priv->data.slave_data[slave_index].phy_addr =
1241 fdtdec_get_int(gd->fdt_blob,
1242 priv->data.slave_data[slave_index].phy_of_handle,
1245 fdtdec_get_int_array(fdt, subnode, "phy_id",
1247 priv->data.slave_data[slave_index].phy_addr =
1253 if (!strncmp(name, "cpsw-phy-sel", 12)) {
1254 priv->data.gmii_sel = cpsw_get_addr_by_node(fdt,
1257 if (priv->data.gmii_sel == FDT_ADDR_T_NONE) {
1258 error("Not able to get gmii_sel reg address\n");
1264 priv->data.slave_data[0].slave_reg_ofs = CPSW_SLAVE0_OFFSET;
1265 priv->data.slave_data[0].sliver_reg_ofs = CPSW_SLIVER0_OFFSET;
1267 if (priv->data.slaves == 2) {
1268 priv->data.slave_data[1].slave_reg_ofs = CPSW_SLAVE1_OFFSET;
1269 priv->data.slave_data[1].sliver_reg_ofs = CPSW_SLIVER1_OFFSET;
1272 ret = ti_cm_get_macid(dev, active_slave, pdata->enetaddr);
1274 error("cpsw read efuse mac failed\n");
1278 pdata->phy_interface = priv->data.slave_data[active_slave].phy_if;
1279 if (pdata->phy_interface == -1) {
1280 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
1283 switch (pdata->phy_interface) {
1284 case PHY_INTERFACE_MODE_MII:
1285 writel(MII_MODE_ENABLE, priv->data.gmii_sel);
1287 case PHY_INTERFACE_MODE_RMII:
1288 writel(RMII_MODE_ENABLE, priv->data.gmii_sel);
1290 case PHY_INTERFACE_MODE_RGMII:
1291 case PHY_INTERFACE_MODE_RGMII_ID:
1292 case PHY_INTERFACE_MODE_RGMII_RXID:
1293 case PHY_INTERFACE_MODE_RGMII_TXID:
1294 writel(RGMII_MODE_ENABLE, priv->data.gmii_sel);
1302 static const struct udevice_id cpsw_eth_ids[] = {
1303 { .compatible = "ti,cpsw" },
1304 { .compatible = "ti,am335x-cpsw" },
1308 U_BOOT_DRIVER(eth_cpsw) = {
1311 .of_match = cpsw_eth_ids,
1312 .ofdata_to_platdata = cpsw_eth_ofdata_to_platdata,
1313 .probe = cpsw_eth_probe,
1314 .ops = &cpsw_eth_ops,
1315 .priv_auto_alloc_size = sizeof(struct cpsw_priv),
1316 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
1317 .flags = DM_FLAG_ALLOC_PRIV_DMA,
1319 #endif /* CONFIG_DM_ETH */