1 /* ax88180.h: ASIX AX88180 Non-PCI Gigabit Ethernet u-boot driver */
4 * This program is free software; you can distribute it and/or modify it
5 * under the terms of the GNU General Public License (Version 2) as
6 * published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * You should have received a copy of the GNU General Public License along
14 * with this program; if not, write to the Free Software Foundation, Inc.,
15 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
22 #include <asm/types.h>
25 typedef enum _ax88180_link_state {
31 struct ax88180_private {
32 unsigned char BusWidth;
33 unsigned char PadSize;
34 unsigned short PhyAddr;
35 unsigned short PhyID0;
36 unsigned short PhyID1;
37 unsigned short FirstTxDesc;
38 unsigned short NextTxDesc;
39 ax88180_link_state LinkState;
42 #define BUS_WIDTH_16 1
43 #define BUS_WIDTH_32 2
45 #define ENABLE_JUMBO 1
46 #define DISABLE_JUMBO 0
48 #define ENABLE_BURST 1
49 #define DISABLE_BURST 0
51 #define NORMAL_RX_MODE 0
52 #define RX_LOOPBACK_MODE 1
53 #define RX_INIFINIT_LOOP_MODE 2
54 #define TX_INIFINIT_LOOP_MODE 3
56 #define DEFAULT_ETH_MTU 1500
58 /* Jumbo packet size 4086 bytes included 4 bytes CRC*/
59 #define MAX_JUMBO_MTU 4072
61 /* Max Tx Jumbo size 4086 bytes included 4 bytes CRC */
62 #define MAX_TX_JUMBO_SIZE 4086
64 /* Max Rx Jumbo size is 15K Bytes */
65 #define MAX_RX_SIZE 0x3C00
67 #define MARVELL_ALASKA_PHYSID0 0x141
68 #define MARVELL_88E1118_PHYSID1 0xE40
70 #define CICADA_CIS8201_PHYSID0 0x000F
73 #define MEDIA_1000FULL 1
74 #define MEDIA_1000HALF 2
75 #define MEDIA_100FULL 3
76 #define MEDIA_100HALF 4
77 #define MEDIA_10FULL 5
78 #define MEDIA_10HALF 6
79 #define MEDIA_UNKNOWN 7
90 #define CMD_MAP_SIZE 0x100
92 #if defined (CONFIG_DRIVER_AX88180_16BIT)
93 #define AX88180_MEMORY_SIZE 0x00004000
94 #define START_BASE 0x1000
96 #define RX_BUF_SIZE 0x1000
97 #define TX_BUF_SIZE 0x0F00
99 #define TX_BASE START_BASE
100 #define CMD_BASE (TX_BASE + TX_BUF_SIZE)
101 #define RX_BASE (CMD_BASE + CMD_MAP_SIZE)
103 #define AX88180_MEMORY_SIZE 0x00010000
105 #define RX_BUF_SIZE 0x8000
106 #define TX_BUF_SIZE 0x7C00
108 #define RX_BASE 0x0000
109 #define TX_BASE (RX_BASE + RX_BUF_SIZE)
110 #define CMD_BASE (TX_BASE + TX_BUF_SIZE)
113 /* AX88180 Memory Mapping Definition */
114 #define RXBUFFER_START RX_BASE
115 #define RX_PACKET_LEN_OFFSET 0
116 #define RX_PAGE_NUM_MASK 0x7FF /* RX pages 0~7FFh */
117 #define TXBUFFER_START TX_BASE
119 /* AX88180 MAC Register Definition */
121 #define DECODE_EN 0x00000001
123 #define CMD (CMD_BASE + 0x0000)
124 #define WAKEMOD 0x00000001
125 #define TXEN 0x00000100
126 #define RXEN 0x00000200
127 #define DEFAULT_CMD WAKEMOD
128 #define IMR (CMD_BASE + 0x0004)
129 #define IMR_RXBUFFOVR 0x00000001
130 #define IMR_WATCHDOG 0x00000002
131 #define IMR_TX 0x00000008
132 #define IMR_RX 0x00000010
133 #define IMR_PHY 0x00000020
134 #define CLEAR_IMR 0x00000000
135 #define DEFAULT_IMR (IMR_PHY | IMR_RX | IMR_TX |\
136 IMR_RXBUFFOVR | IMR_WATCHDOG)
137 #define ISR (CMD_BASE + 0x0008)
138 #define ISR_RXBUFFOVR 0x00000001
139 #define ISR_WATCHDOG 0x00000002
140 #define ISR_TX 0x00000008
141 #define ISR_RX 0x00000010
142 #define ISR_PHY 0x00000020
143 #define TXCFG (CMD_BASE + 0x0010)
144 #define AUTOPAD_CRC 0x00000050
145 #define DEFAULT_TXCFG AUTOPAD_CRC
146 #define TXCMD (CMD_BASE + 0x0014)
147 #define TXCMD_TXDP_MASK 0x00006000
148 #define TXCMD_TXDP0 0x00000000
149 #define TXCMD_TXDP1 0x00002000
150 #define TXCMD_TXDP2 0x00004000
151 #define TXCMD_TXDP3 0x00006000
152 #define TX_START_WRITE 0x00008000
153 #define TX_STOP_WRITE 0x00000000
154 #define DEFAULT_TXCMD 0x00000000
155 #define TXBS (CMD_BASE + 0x0018)
156 #define TXDP0_USED 0x00000001
157 #define TXDP1_USED 0x00000002
158 #define TXDP2_USED 0x00000004
159 #define TXDP3_USED 0x00000008
160 #define DEFAULT_TXBS 0x00000000
161 #define TXDES0 (CMD_BASE + 0x0020)
162 #define TXDPx_ENABLE 0x00008000
163 #define TXDPx_LEN_MASK 0x00001FFF
164 #define DEFAULT_TXDES0 0x00000000
165 #define TXDES1 (CMD_BASE + 0x0024)
166 #define TXDPx_ENABLE 0x00008000
167 #define TXDPx_LEN_MASK 0x00001FFF
168 #define DEFAULT_TXDES1 0x00000000
169 #define TXDES2 (CMD_BASE + 0x0028)
170 #define TXDPx_ENABLE 0x00008000
171 #define TXDPx_LEN_MASK 0x00001FFF
172 #define DEFAULT_TXDES2 0x00000000
173 #define TXDES3 (CMD_BASE + 0x002C)
174 #define TXDPx_ENABLE 0x00008000
175 #define TXDPx_LEN_MASK 0x00001FFF
176 #define DEFAULT_TXDES3 0x00000000
177 #define RXCFG (CMD_BASE + 0x0030)
178 #define RXBUFF_PROTECT 0x00000001
179 #define RXTCPCRC_CHECK 0x00000010
180 #define RXFLOW_ENABLE 0x00000100
181 #define DEFAULT_RXCFG RXBUFF_PROTECT
182 #define RXCURT (CMD_BASE + 0x0034)
183 #define DEFAULT_RXCURT 0x00000000
184 #define RXBOUND (CMD_BASE + 0x0038)
185 #define DEFAULT_RXBOUND 0x7FF /* RX pages 0~7FFh */
186 #define MACCFG0 (CMD_BASE + 0x0040)
187 #define MACCFG0_BIT3_0 0x00000007
188 #define IPGT_VAL 0x00000150
189 #define TXFLOW_ENABLE 0x00001000
190 #define SPEED100 0x00008000
191 #define DEFAULT_MACCFG0 (IPGT_VAL | MACCFG0_BIT3_0)
192 #define MACCFG1 (CMD_BASE + 0x0044)
193 #define RGMII_EN 0x00000002
194 #define RXFLOW_EN 0x00000020
195 #define FULLDUPLEX 0x00000040
196 #define MAX_JUMBO_LEN 0x00000780
197 #define RXJUMBO_EN 0x00000800
198 #define GIGA_MODE_EN 0x00001000
199 #define RXCRC_CHECK 0x00002000
200 #define RXPAUSE_DA_CHECK 0x00004000
202 #define JUMBO_LEN_4K 0x00000200
203 #define JUMBO_LEN_15K 0x00000780
204 #define DEFAULT_MACCFG1 (RXCRC_CHECK | RXPAUSE_DA_CHECK | \
206 #define CICADA_DEFAULT_MACCFG1 (RXCRC_CHECK | RXPAUSE_DA_CHECK)
207 #define MACCFG2 (CMD_BASE + 0x0048)
208 #define MACCFG2_BIT15_8 0x00000100
209 #define JAM_LIMIT_MASK 0x000000FC
210 #define DEFAULT_JAM_LIMIT 0x00000064
211 #define DEFAULT_MACCFG2 MACCFG2_BIT15_8
212 #define MACCFG3 (CMD_BASE + 0x004C)
213 #define IPGR2_VAL 0x0000000E
214 #define IPGR1_VAL 0x00000600
215 #define NOABORT 0x00008000
216 #define DEFAULT_MACCFG3 (IPGR1_VAL | IPGR2_VAL)
217 #define TXPAUT (CMD_BASE + 0x0054)
218 #define DEFAULT_TXPAUT 0x001FE000
219 #define RXBTHD0 (CMD_BASE + 0x0058)
220 #define DEFAULT_RXBTHD0 0x00000300
221 #define RXBTHD1 (CMD_BASE + 0x005C)
222 #define DEFAULT_RXBTHD1 0x00000600
223 #define RXFULTHD (CMD_BASE + 0x0060)
224 #define DEFAULT_RXFULTHD 0x00000100
225 #define MISC (CMD_BASE + 0x0068)
226 /* Normal operation mode */
227 #define MISC_NORMAL 0x00000003
228 /* Clear bit 0 to reset MAC */
229 #define MISC_RESET_MAC 0x00000002
230 /* Clear bit 1 to reset PHY */
231 #define MISC_RESET_PHY 0x00000001
232 /* Clear bit 0 and 1 to reset MAC and PHY */
233 #define MISC_RESET_MAC_PHY 0x00000000
234 #define DEFAULT_MISC MISC_NORMAL
235 #define MACID0 (CMD_BASE + 0x0070)
236 #define MACID1 (CMD_BASE + 0x0074)
237 #define MACID2 (CMD_BASE + 0x0078)
238 #define TXLEN (CMD_BASE + 0x007C)
239 #define DEFAULT_TXLEN 0x000005FC
240 #define RXFILTER (CMD_BASE + 0x0080)
241 #define RX_RXANY 0x00000001
242 #define RX_MULTICAST 0x00000002
243 #define RX_UNICAST 0x00000004
244 #define RX_BROADCAST 0x00000008
245 #define RX_MULTI_HASH 0x00000010
246 #define DISABLE_RXFILTER 0x00000000
247 #define DEFAULT_RXFILTER (RX_BROADCAST + RX_UNICAST)
248 #define MDIOCTRL (CMD_BASE + 0x0084)
249 #define PHY_ADDR_MASK 0x0000001F
250 #define REG_ADDR_MASK 0x00001F00
251 #define READ_PHY 0x00004000
252 #define WRITE_PHY 0x00008000
253 #define MDIODP (CMD_BASE + 0x0088)
254 #define GPIOCTRL (CMD_BASE + 0x008C)
255 #define RXINDICATOR (CMD_BASE + 0x0090)
256 #define RX_START_READ 0x00000001
257 #define RX_STOP_READ 0x00000000
258 #define DEFAULT_RXINDICATOR RX_STOP_READ
259 #define TXST (CMD_BASE + 0x0094)
260 #define MDCCLKPAT (CMD_BASE + 0x00A0)
261 #define RXIPCRCCNT (CMD_BASE + 0x00A4)
262 #define RXCRCCNT (CMD_BASE + 0x00A8)
263 #define TXFAILCNT (CMD_BASE + 0x00AC)
264 #define PROMDP (CMD_BASE + 0x00B0)
265 #define PROMCTRL (CMD_BASE + 0x00B4)
266 #define RELOAD_EEPROM 0x00000200
267 #define MAXRXLEN (CMD_BASE + 0x00B8)
268 #define HASHTAB0 (CMD_BASE + 0x00C0)
269 #define HASHTAB1 (CMD_BASE + 0x00C4)
270 #define HASHTAB2 (CMD_BASE + 0x00C8)
271 #define HASHTAB3 (CMD_BASE + 0x00CC)
272 #define DOGTHD0 (CMD_BASE + 0x00E0)
273 #define DEFAULT_DOGTHD0 0x0000FFFF
274 #define DOGTHD1 (CMD_BASE + 0x00E4)
275 #define START_WATCHDOG_TIMER 0x00008000
276 #define DEFAULT_DOGTHD1 0x00000FFF
277 #define SOFTRST (CMD_BASE + 0x00EC)
278 #define SOFTRST_NORMAL 0x00000003
279 #define SOFTRST_RESET_MAC 0x00000002
281 /* Marvell 88E1111 Gigabit PHY Register Definition */
282 #define M88_SSR 0x0011
283 #define SSR_SPEED_MASK 0xC000
284 #define SSR_SPEED_1000 0x8000
285 #define SSR_SPEED_100 0x4000
286 #define SSR_SPEED_10 0x0000
287 #define SSR_DUPLEX 0x2000
288 #define SSR_MEDIA_RESOLVED_OK 0x0800
290 #define SSR_MEDIA_MASK (SSR_SPEED_MASK | SSR_DUPLEX)
291 #define SSR_1000FULL (SSR_SPEED_1000 | SSR_DUPLEX)
292 #define SSR_1000HALF SSR_SPEED_1000
293 #define SSR_100FULL (SSR_SPEED_100 | SSR_DUPLEX)
294 #define SSR_100HALF SSR_SPEED_100
295 #define SSR_10FULL (SSR_SPEED_10 | SSR_DUPLEX)
296 #define SSR_10HALF SSR_SPEED_10
297 #define M88_IER 0x0012
298 #define LINK_CHANGE_INT 0x0400
299 #define M88_ISR 0x0013
300 #define LINK_CHANGE_STATUS 0x0400
301 #define M88E1111_EXT_SCR 0x0014
302 #define RGMII_RXCLK_DELAY 0x0080
303 #define RGMII_TXCLK_DELAY 0x0002
304 #define DEFAULT_EXT_SCR (RGMII_TXCLK_DELAY | RGMII_RXCLK_DELAY)
305 #define M88E1111_EXT_SSR 0x001B
306 #define HWCFG_MODE_MASK 0x000F
307 #define RGMII_COPPER_MODE 0x000B
309 /* Marvell 88E1118 Gigabit PHY Register Definition */
310 #define M88E1118_CR 0x14
311 #define M88E1118_CR_RGMII_RXCLK_DELAY 0x0020
312 #define M88E1118_CR_RGMII_TXCLK_DELAY 0x0010
313 #define M88E1118_CR_DEFAULT (M88E1118_CR_RGMII_TXCLK_DELAY | \
314 M88E1118_CR_RGMII_RXCLK_DELAY)
315 #define M88E1118_LEDCTL 0x10 /* Reg 16 on page 3 */
316 #define M88E1118_LEDCTL_LED2INT 0x200
317 #define M88E1118_LEDCTL_LED2BLNK 0x400
318 #define M88E1118_LEDCTL_LED0DUALMODE1 0xc
319 #define M88E1118_LEDCTL_LED0DUALMODE2 0xd
320 #define M88E1118_LEDCTL_LED0DUALMODE3 0xe
321 #define M88E1118_LEDCTL_LED0DUALMODE4 0xf
322 #define M88E1118_LEDCTL_DEFAULT (M88E1118_LEDCTL_LED2BLNK | \
323 M88E1118_LEDCTL_LED0DUALMODE4)
325 #define M88E1118_LEDMIX 0x11 /* Reg 17 on page 3 */
326 #define M88E1118_LEDMIX_LED050 0x4
327 #define M88E1118_LEDMIX_LED150 0x8
329 #define M88E1118_PAGE_SEL 0x16 /* Reg page select */
331 /* CICADA CIS8201 Gigabit PHY Register Definition */
332 #define CIS_IMR 0x0019
333 #define CIS_INT_ENABLE 0x8000
334 #define CIS_LINK_CHANGE_INT 0x2000
335 #define CIS_ISR 0x001A
336 #define CIS_INT_PENDING 0x8000
337 #define CIS_LINK_CHANGE_STATUS 0x2000
338 #define CIS_AUX_CTRL_STATUS 0x001C
339 #define CIS_AUTONEG_COMPLETE 0x8000
340 #define CIS_SPEED_MASK 0x0018
341 #define CIS_SPEED_1000 0x0010
342 #define CIS_SPEED_100 0x0008
343 #define CIS_SPEED_10 0x0000
344 #define CIS_DUPLEX 0x0020
346 #define CIS_MEDIA_MASK (CIS_SPEED_MASK | CIS_DUPLEX)
347 #define CIS_1000FULL (CIS_SPEED_1000 | CIS_DUPLEX)
348 #define CIS_1000HALF CIS_SPEED_1000
349 #define CIS_100FULL (CIS_SPEED_100 | CIS_DUPLEX)
350 #define CIS_100HALF CIS_SPEED_100
351 #define CIS_10FULL (CIS_SPEED_10 | CIS_DUPLEX)
352 #define CIS_10HALF CIS_SPEED_10
353 #define CIS_SMI_PRIORITY 0x0004
355 static inline unsigned short INW (struct eth_device *dev, unsigned long addr)
357 return le16_to_cpu (*(volatile unsigned short *) (addr + dev->iobase));
361 Access RXBUFFER_START/TXBUFFER_START to read RX buffer/write TX buffer
363 #if defined (CONFIG_DRIVER_AX88180_16BIT)
364 static inline void OUTW (struct eth_device *dev, unsigned short command, unsigned long addr)
366 *(volatile unsigned short *) ((addr + dev->iobase)) = cpu_to_le16 (command);
369 static inline unsigned short READ_RXBUF (struct eth_device *dev)
371 return le16_to_cpu (*(volatile unsigned short *) (RXBUFFER_START + dev->iobase));
374 static inline void WRITE_TXBUF (struct eth_device *dev, unsigned short data)
376 *(volatile unsigned short *) ((TXBUFFER_START + dev->iobase)) = cpu_to_le16 (data);
379 static inline void OUTW (struct eth_device *dev, unsigned short command, unsigned long addr)
381 *(volatile unsigned long *) ((addr + dev->iobase)) = cpu_to_le32 (command);
384 static inline unsigned long READ_RXBUF (struct eth_device *dev)
386 return le32_to_cpu (*(volatile unsigned long *) (RXBUFFER_START + dev->iobase));
389 static inline void WRITE_TXBUF (struct eth_device *dev, unsigned long data)
391 *(volatile unsigned long *) ((TXBUFFER_START + dev->iobase)) = cpu_to_le32 (data);
395 #endif /* _AX88180_H_ */