2 * ax88180: ASIX AX88180 Non-PCI Gigabit Ethernet u-boot driver
4 * This program is free software; you can distribute it and/or modify
5 * it under the terms of the GNU General Public License (Version 2) as
6 * published by the Free Software Foundation.
7 * This program is distributed in the hope it will be useful, but
8 * WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
10 * See the GNU General Public License for more details.
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, write to the Free Software
13 * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307,
18 * ========================================================================
19 * ASIX AX88180 Non-PCI 16/32-bit Gigabit Ethernet Linux Driver
21 * The AX88180 Ethernet controller is a high performance and highly
22 * integrated local CPU bus Ethernet controller with embedded 40K bytes
23 * SRAM and supports both 16-bit and 32-bit SRAM-Like interfaces for any
25 * The AX88180 is a single chip 10/100/1000Mbps Gigabit Ethernet
26 * controller that supports both MII and RGMII interfaces and is
27 * compliant to IEEE 802.3, IEEE 802.3u and IEEE 802.3z standards.
29 * Please visit ASIX's web site (http://www.asix.com.tw) for more
32 * Module Name : ax88180.c
35 * 09/06/2006 : New release for AX88180 US2 chip.
36 * 07/07/2008 : Fix up the coding style and using inline functions
38 * ========================================================================
44 #include <linux/mii.h>
48 * ===========================================================================
49 * Local SubProgram Declaration
50 * ===========================================================================
52 static void ax88180_rx_handler (struct eth_device *dev);
53 static int ax88180_phy_initial (struct eth_device *dev);
54 static void ax88180_media_config (struct eth_device *dev);
55 static unsigned long get_CicadaPHY_media_mode (struct eth_device *dev);
56 static unsigned long get_MarvellPHY_media_mode (struct eth_device *dev);
57 static unsigned short ax88180_mdio_read (struct eth_device *dev,
58 unsigned long regaddr);
59 static void ax88180_mdio_write (struct eth_device *dev,
60 unsigned long regaddr, unsigned short regdata);
63 * ===========================================================================
64 * Local SubProgram Bodies
65 * ===========================================================================
67 static int ax88180_mdio_check_complete (struct eth_device *dev)
70 unsigned short tmpval;
72 /* MDIO read/write should not take more than 10 ms */
74 tmpval = INW (dev, MDIOCTRL);
75 if (((tmpval & READ_PHY) == 0) && ((tmpval & WRITE_PHY) == 0))
83 ax88180_mdio_read (struct eth_device *dev, unsigned long regaddr)
85 struct ax88180_private *priv = (struct ax88180_private *)dev->priv;
86 unsigned long tmpval = 0;
88 OUTW (dev, (READ_PHY | (regaddr << 8) | priv->PhyAddr), MDIOCTRL);
90 if (ax88180_mdio_check_complete (dev))
91 tmpval = INW (dev, MDIODP);
93 printf ("Failed to read PHY register!\n");
95 return (unsigned short)(tmpval & 0xFFFF);
99 ax88180_mdio_write (struct eth_device *dev, unsigned long regaddr,
100 unsigned short regdata)
102 struct ax88180_private *priv = (struct ax88180_private *)dev->priv;
104 OUTW (dev, regdata, MDIODP);
106 OUTW (dev, (WRITE_PHY | (regaddr << 8) | priv->PhyAddr), MDIOCTRL);
108 if (!ax88180_mdio_check_complete (dev))
109 printf ("Failed to write PHY register!\n");
112 static int ax88180_phy_reset (struct eth_device *dev)
114 unsigned short delay_cnt = 500;
116 ax88180_mdio_write (dev, MII_BMCR, (BMCR_RESET | BMCR_ANENABLE));
118 /* Wait for the reset to complete, or time out (500 ms) */
119 while (ax88180_mdio_read (dev, MII_BMCR) & BMCR_RESET) {
121 if (--delay_cnt == 0) {
122 printf ("Failed to reset PHY!\n");
130 static void ax88180_mac_reset (struct eth_device *dev)
132 unsigned long tmpval;
136 unsigned short offset, value;
139 MISC, MISC_NORMAL}, {
140 RXINDICATOR, DEFAULT_RXINDICATOR}, {
141 TXCMD, DEFAULT_TXCMD}, {
142 TXBS, DEFAULT_TXBS}, {
143 TXDES0, DEFAULT_TXDES0}, {
144 TXDES1, DEFAULT_TXDES1}, {
145 TXDES2, DEFAULT_TXDES2}, {
146 TXDES3, DEFAULT_TXDES3}, {
147 TXCFG, DEFAULT_TXCFG}, {
148 MACCFG2, DEFAULT_MACCFG2}, {
149 MACCFG3, DEFAULT_MACCFG3}, {
150 TXLEN, DEFAULT_TXLEN}, {
151 RXBTHD0, DEFAULT_RXBTHD0}, {
152 RXBTHD1, DEFAULT_RXBTHD1}, {
153 RXFULTHD, DEFAULT_RXFULTHD}, {
154 DOGTHD0, DEFAULT_DOGTHD0}, {
155 DOGTHD1, DEFAULT_DOGTHD1},};
157 OUTW (dev, MISC_RESET_MAC, MISC);
158 tmpval = INW (dev, MISC);
160 for (i = 0; i < (sizeof (program_seq) / sizeof (program_seq[0])); i++)
161 OUTW (dev, program_seq[i].value, program_seq[i].offset);
164 static int ax88180_poll_tx_complete (struct eth_device *dev)
166 struct ax88180_private *priv = (struct ax88180_private *)dev->priv;
167 unsigned long tmpval, txbs_txdp;
168 int TimeOutCnt = 10000;
170 txbs_txdp = 1 << priv->NextTxDesc;
172 while (TimeOutCnt--) {
174 tmpval = INW (dev, TXBS);
176 if ((tmpval & txbs_txdp) == 0)
188 static void ax88180_rx_handler (struct eth_device *dev)
190 struct ax88180_private *priv = (struct ax88180_private *)dev->priv;
191 unsigned long data_size;
192 unsigned short rxcurt_ptr, rxbound_ptr, next_ptr;
194 #if defined (CONFIG_DRIVER_AX88180_16BIT)
195 unsigned short *rxdata = (unsigned short *)NetRxPackets[0];
197 unsigned long *rxdata = (unsigned long *)NetRxPackets[0];
199 unsigned short count;
201 rxcurt_ptr = INW (dev, RXCURT);
202 rxbound_ptr = INW (dev, RXBOUND);
203 next_ptr = (rxbound_ptr + 1) & RX_PAGE_NUM_MASK;
205 debug ("ax88180: RX original RXBOUND=0x%04x,"
206 " RXCURT=0x%04x\n", rxbound_ptr, rxcurt_ptr);
208 while (next_ptr != rxcurt_ptr) {
210 OUTW (dev, RX_START_READ, RXINDICATOR);
212 data_size = READ_RXBUF (dev) & 0xFFFF;
214 if ((data_size == 0) || (data_size > MAX_RX_SIZE)) {
216 OUTW (dev, RX_STOP_READ, RXINDICATOR);
218 ax88180_mac_reset (dev);
219 printf ("ax88180: Invalid Rx packet length!"
220 " (len=0x%04lx)\n", data_size);
222 debug ("ax88180: RX RXBOUND=0x%04x,"
223 "RXCURT=0x%04x\n", rxbound_ptr, rxcurt_ptr);
227 rxbound_ptr += (((data_size + 0xF) & 0xFFF0) >> 4) + 1;
228 rxbound_ptr &= RX_PAGE_NUM_MASK;
230 /* Comput access times */
231 count = (data_size + priv->PadSize) >> priv->BusWidth;
233 for (i = 0; i < count; i++) {
234 *(rxdata + i) = READ_RXBUF (dev);
237 OUTW (dev, RX_STOP_READ, RXINDICATOR);
239 /* Pass the packet up to the protocol layers. */
240 NetReceive (NetRxPackets[0], data_size);
242 OUTW (dev, rxbound_ptr, RXBOUND);
244 rxcurt_ptr = INW (dev, RXCURT);
245 rxbound_ptr = INW (dev, RXBOUND);
246 next_ptr = (rxbound_ptr + 1) & RX_PAGE_NUM_MASK;
248 debug ("ax88180: RX updated RXBOUND=0x%04x,"
249 "RXCURT=0x%04x\n", rxbound_ptr, rxcurt_ptr);
255 static int ax88180_phy_initial (struct eth_device *dev)
257 struct ax88180_private *priv = (struct ax88180_private *)dev->priv;
258 unsigned long tmp_regval;
259 unsigned short phyaddr;
261 /* Search for first avaliable PHY chipset */
262 #ifdef CONFIG_PHY_ADDR
263 phyaddr = CONFIG_PHY_ADDR;
265 for (phyaddr = 0; phyaddr < 32; ++phyaddr)
268 priv->PhyAddr = phyaddr;
269 priv->PhyID0 = ax88180_mdio_read(dev, MII_PHYSID1);
271 switch (priv->PhyID0) {
272 case MARVELL_88E1111_PHYSID0:
273 debug("ax88180: Found Marvell 88E1111 PHY."
274 " (PHY Addr=0x%x)\n", priv->PhyAddr);
276 tmp_regval = ax88180_mdio_read(dev, M88_EXT_SSR);
277 if ((tmp_regval & HWCFG_MODE_MASK) != RGMII_COPPER_MODE) {
278 ax88180_mdio_write(dev, M88_EXT_SCR, DEFAULT_EXT_SCR);
279 if (ax88180_phy_reset(dev) < 0)
281 ax88180_mdio_write(dev, M88_IER, LINK_CHANGE_INT);
286 case CICADA_CIS8201_PHYSID0:
287 debug("ax88180: Found CICADA CIS8201 PHY"
288 " chipset. (PHY Addr=0x%x)\n", priv->PhyAddr);
290 ax88180_mdio_write(dev, CIS_IMR,
291 (CIS_INT_ENABLE | LINK_CHANGE_INT));
293 /* Set CIS_SMI_PRIORITY bit before force the media mode */
294 tmp_regval = ax88180_mdio_read(dev, CIS_AUX_CTRL_STATUS);
295 tmp_regval &= ~CIS_SMI_PRIORITY;
296 ax88180_mdio_write(dev, CIS_AUX_CTRL_STATUS, tmp_regval);
301 /* No PHY at this addr */
305 printf("ax88180: Unknown PHY chipset %#x at addr %#x\n",
306 priv->PhyID0, priv->PhyAddr);
311 printf("ax88180: Unknown PHY chipset!!\n");
315 static void ax88180_media_config (struct eth_device *dev)
317 struct ax88180_private *priv = (struct ax88180_private *)dev->priv;
318 unsigned long bmcr_val, bmsr_val;
319 unsigned long rxcfg_val, maccfg0_val, maccfg1_val;
320 unsigned long RealMediaMode;
323 /* Waiting 2 seconds for PHY link stable */
324 for (i = 0; i < 20000; i++) {
325 bmsr_val = ax88180_mdio_read (dev, MII_BMSR);
326 if (bmsr_val & BMSR_LSTATUS) {
332 bmsr_val = ax88180_mdio_read (dev, MII_BMSR);
333 debug ("ax88180: BMSR=0x%04x\n", (unsigned int)bmsr_val);
335 if (bmsr_val & BMSR_LSTATUS) {
336 bmcr_val = ax88180_mdio_read (dev, MII_BMCR);
338 if (bmcr_val & BMCR_ANENABLE) {
341 * Waiting for Auto-negotiation completion, this may
342 * take up to 5 seconds.
344 debug ("ax88180: Auto-negotiation is "
345 "enabled. Waiting for NWay completion..\n");
346 for (i = 0; i < 50000; i++) {
347 bmsr_val = ax88180_mdio_read (dev, MII_BMSR);
348 if (bmsr_val & BMSR_ANEGCOMPLETE) {
354 debug ("ax88180: Auto-negotiation is disabled.\n");
356 debug ("ax88180: BMCR=0x%04x, BMSR=0x%04x\n",
357 (unsigned int)bmcr_val, (unsigned int)bmsr_val);
359 /* Get real media mode here */
360 switch (priv->PhyID0) {
361 case MARVELL_88E1111_PHYSID0:
362 RealMediaMode = get_MarvellPHY_media_mode(dev);
364 case CICADA_CIS8201_PHYSID0:
365 RealMediaMode = get_CicadaPHY_media_mode(dev);
368 RealMediaMode = MEDIA_1000FULL;
372 priv->LinkState = INS_LINK_UP;
374 switch (RealMediaMode) {
376 debug ("ax88180: 1000Mbps Full-duplex mode.\n");
377 rxcfg_val = RXFLOW_ENABLE | DEFAULT_RXCFG;
378 maccfg0_val = TXFLOW_ENABLE | DEFAULT_MACCFG0;
379 maccfg1_val = GIGA_MODE_EN | RXFLOW_EN |
380 FULLDUPLEX | DEFAULT_MACCFG1;
384 debug ("ax88180: 1000Mbps Half-duplex mode.\n");
385 rxcfg_val = DEFAULT_RXCFG;
386 maccfg0_val = DEFAULT_MACCFG0;
387 maccfg1_val = GIGA_MODE_EN | DEFAULT_MACCFG1;
391 debug ("ax88180: 100Mbps Full-duplex mode.\n");
392 rxcfg_val = RXFLOW_ENABLE | DEFAULT_RXCFG;
393 maccfg0_val = SPEED100 | TXFLOW_ENABLE
395 maccfg1_val = RXFLOW_EN | FULLDUPLEX | DEFAULT_MACCFG1;
399 debug ("ax88180: 100Mbps Half-duplex mode.\n");
400 rxcfg_val = DEFAULT_RXCFG;
401 maccfg0_val = SPEED100 | DEFAULT_MACCFG0;
402 maccfg1_val = DEFAULT_MACCFG1;
406 debug ("ax88180: 10Mbps Full-duplex mode.\n");
407 rxcfg_val = RXFLOW_ENABLE | DEFAULT_RXCFG;
408 maccfg0_val = TXFLOW_ENABLE | DEFAULT_MACCFG0;
409 maccfg1_val = RXFLOW_EN | FULLDUPLEX | DEFAULT_MACCFG1;
413 debug ("ax88180: 10Mbps Half-duplex mode.\n");
414 rxcfg_val = DEFAULT_RXCFG;
415 maccfg0_val = DEFAULT_MACCFG0;
416 maccfg1_val = DEFAULT_MACCFG1;
419 debug ("ax88180: Unknow media mode.\n");
420 rxcfg_val = DEFAULT_RXCFG;
421 maccfg0_val = DEFAULT_MACCFG0;
422 maccfg1_val = DEFAULT_MACCFG1;
424 priv->LinkState = INS_LINK_DOWN;
429 rxcfg_val = DEFAULT_RXCFG;
430 maccfg0_val = DEFAULT_MACCFG0;
431 maccfg1_val = DEFAULT_MACCFG1;
433 priv->LinkState = INS_LINK_DOWN;
436 OUTW (dev, rxcfg_val, RXCFG);
437 OUTW (dev, maccfg0_val, MACCFG0);
438 OUTW (dev, maccfg1_val, MACCFG1);
443 static unsigned long get_MarvellPHY_media_mode (struct eth_device *dev)
445 unsigned long m88_ssr;
446 unsigned long MediaMode;
448 m88_ssr = ax88180_mdio_read (dev, M88_SSR);
449 switch (m88_ssr & SSR_MEDIA_MASK) {
451 MediaMode = MEDIA_1000FULL;
454 MediaMode = MEDIA_1000HALF;
457 MediaMode = MEDIA_100FULL;
460 MediaMode = MEDIA_100HALF;
463 MediaMode = MEDIA_10FULL;
466 MediaMode = MEDIA_10HALF;
469 MediaMode = MEDIA_UNKNOWN;
476 static unsigned long get_CicadaPHY_media_mode (struct eth_device *dev)
478 unsigned long tmp_regval;
479 unsigned long MediaMode;
481 tmp_regval = ax88180_mdio_read (dev, CIS_AUX_CTRL_STATUS);
482 switch (tmp_regval & CIS_MEDIA_MASK) {
484 MediaMode = MEDIA_1000FULL;
487 MediaMode = MEDIA_1000HALF;
490 MediaMode = MEDIA_100FULL;
493 MediaMode = MEDIA_100HALF;
496 MediaMode = MEDIA_10FULL;
499 MediaMode = MEDIA_10HALF;
502 MediaMode = MEDIA_UNKNOWN;
509 static void ax88180_halt (struct eth_device *dev)
511 /* Disable AX88180 TX/RX functions */
512 OUTW (dev, WAKEMOD, CMD);
515 static int ax88180_init (struct eth_device *dev, bd_t * bd)
517 struct ax88180_private *priv = (struct ax88180_private *)dev->priv;
518 unsigned short tmp_regval;
520 ax88180_mac_reset (dev);
522 /* Disable interrupt */
523 OUTW (dev, CLEAR_IMR, IMR);
525 /* Disable AX88180 TX/RX functions */
526 OUTW (dev, WAKEMOD, CMD);
528 /* Fill the MAC address */
530 dev->enetaddr[0] | (((unsigned short)dev->enetaddr[1]) << 8);
531 OUTW (dev, tmp_regval, MACID0);
534 dev->enetaddr[2] | (((unsigned short)dev->enetaddr[3]) << 8);
535 OUTW (dev, tmp_regval, MACID1);
538 dev->enetaddr[4] | (((unsigned short)dev->enetaddr[5]) << 8);
539 OUTW (dev, tmp_regval, MACID2);
541 ax88180_media_config (dev);
543 OUTW (dev, DEFAULT_RXFILTER, RXFILTER);
545 /* Initial variables here */
546 priv->FirstTxDesc = TXDP0;
547 priv->NextTxDesc = TXDP0;
549 /* Check if there is any invalid interrupt status and clear it. */
550 OUTW (dev, INW (dev, ISR), ISR);
552 /* Start AX88180 TX/RX functions */
553 OUTW (dev, (RXEN | TXEN | WAKEMOD), CMD);
558 /* Get a data block via Ethernet */
559 static int ax88180_recv (struct eth_device *dev)
561 unsigned short ISR_Status;
562 unsigned short tmp_regval;
564 /* Read and check interrupt status here. */
565 ISR_Status = INW (dev, ISR);
568 /* Clear the interrupt status */
569 OUTW (dev, ISR_Status, ISR);
571 debug ("\nax88180: The interrupt status = 0x%04x\n",
574 if (ISR_Status & ISR_PHY) {
575 /* Read ISR register once to clear PHY interrupt bit */
576 tmp_regval = ax88180_mdio_read (dev, M88_ISR);
577 ax88180_media_config (dev);
580 if ((ISR_Status & ISR_RX) || (ISR_Status & ISR_RXBUFFOVR)) {
581 ax88180_rx_handler (dev);
584 /* Read and check interrupt status again */
585 ISR_Status = INW (dev, ISR);
591 /* Send a data block via Ethernet. */
593 ax88180_send (struct eth_device *dev, volatile void *packet, int length)
595 struct ax88180_private *priv = (struct ax88180_private *)dev->priv;
596 unsigned short TXDES_addr;
597 unsigned short txcmd_txdp, txbs_txdp;
598 unsigned short tmp_data;
600 #if defined (CONFIG_DRIVER_AX88180_16BIT)
601 volatile unsigned short *txdata = (volatile unsigned short *)packet;
603 volatile unsigned long *txdata = (volatile unsigned long *)packet;
605 unsigned short count;
607 if (priv->LinkState != INS_LINK_UP) {
611 priv->FirstTxDesc = priv->NextTxDesc;
612 txbs_txdp = 1 << priv->FirstTxDesc;
614 debug ("ax88180: TXDP%d is available\n", priv->FirstTxDesc);
616 txcmd_txdp = priv->FirstTxDesc << 13;
617 TXDES_addr = TXDES0 + (priv->FirstTxDesc << 2);
619 OUTW (dev, (txcmd_txdp | length | TX_START_WRITE), TXCMD);
621 /* Comput access times */
622 count = (length + priv->PadSize) >> priv->BusWidth;
624 for (i = 0; i < count; i++) {
625 WRITE_TXBUF (dev, *(txdata + i));
628 OUTW (dev, txcmd_txdp | length, TXCMD);
629 OUTW (dev, txbs_txdp, TXBS);
630 OUTW (dev, (TXDPx_ENABLE | length), TXDES_addr);
632 priv->NextTxDesc = (priv->NextTxDesc + 1) & TXDP_MASK;
635 * Check the available transmit descriptor, if we had exhausted all
636 * transmit descriptor ,then we have to wait for at least one free
639 txbs_txdp = 1 << priv->NextTxDesc;
640 tmp_data = INW (dev, TXBS);
642 if (tmp_data & txbs_txdp) {
643 if (ax88180_poll_tx_complete (dev) < 0) {
644 ax88180_mac_reset (dev);
645 priv->FirstTxDesc = TXDP0;
646 priv->NextTxDesc = TXDP0;
647 printf ("ax88180: Transmit time out occurred!\n");
654 static void ax88180_read_mac_addr (struct eth_device *dev)
656 unsigned short macid0_val, macid1_val, macid2_val;
657 unsigned short tmp_regval;
660 /* Reload MAC address from EEPROM */
661 OUTW (dev, RELOAD_EEPROM, PROMCTRL);
663 /* Waiting for reload eeprom completion */
664 for (i = 0; i < 500; i++) {
665 tmp_regval = INW (dev, PROMCTRL);
666 if ((tmp_regval & RELOAD_EEPROM) == 0)
671 /* Get MAC addresses */
672 macid0_val = INW (dev, MACID0);
673 macid1_val = INW (dev, MACID1);
674 macid2_val = INW (dev, MACID2);
676 if (((macid0_val | macid1_val | macid2_val) != 0) &&
677 ((macid0_val & 0x01) == 0)) {
678 dev->enetaddr[0] = (unsigned char)macid0_val;
679 dev->enetaddr[1] = (unsigned char)(macid0_val >> 8);
680 dev->enetaddr[2] = (unsigned char)macid1_val;
681 dev->enetaddr[3] = (unsigned char)(macid1_val >> 8);
682 dev->enetaddr[4] = (unsigned char)macid2_val;
683 dev->enetaddr[5] = (unsigned char)(macid2_val >> 8);
688 ===========================================================================
689 <<<<<< Exported SubProgram Bodies >>>>>>
690 ===========================================================================
692 int ax88180_initialize (bd_t * bis)
694 struct eth_device *dev;
695 struct ax88180_private *priv;
697 dev = (struct eth_device *)malloc (sizeof *dev);
702 memset (dev, 0, sizeof *dev);
704 priv = (struct ax88180_private *)malloc (sizeof (*priv));
709 memset (priv, 0, sizeof *priv);
711 sprintf (dev->name, "ax88180");
712 dev->iobase = AX88180_BASE;
714 dev->init = ax88180_init;
715 dev->halt = ax88180_halt;
716 dev->send = ax88180_send;
717 dev->recv = ax88180_recv;
719 priv->BusWidth = BUS_WIDTH_32;
721 #if defined (CONFIG_DRIVER_AX88180_16BIT)
722 OUTW (dev, (START_BASE >> 8), BASE);
723 OUTW (dev, DECODE_EN, DECODE);
725 priv->BusWidth = BUS_WIDTH_16;
729 ax88180_mac_reset (dev);
731 /* Disable interrupt */
732 OUTW (dev, CLEAR_IMR, IMR);
734 /* Disable AX88180 TX/RX functions */
735 OUTW (dev, WAKEMOD, CMD);
737 ax88180_read_mac_addr (dev);
741 return ax88180_phy_initial (dev);