2 * Altera 10/100/1000 triple speed ethernet mac
4 * Copyright (C) 2008 Altera Corporation.
5 * Copyright (C) 2010 Thomas Chou <thomas@wytron.com.tw>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 #ifndef _ALTERA_TSE_H_
12 #define _ALTERA_TSE_H_
14 #include <linux/bitops.h>
15 #define __packed_1_ __packed __aligned(1)
22 #define ALT_SGDMA_STATUS_BUSY_MSK BIT(4)
24 #define ALT_SGDMA_CONTROL_RUN_MSK BIT(5)
25 #define ALT_SGDMA_CONTROL_STOP_DMA_ER_MSK BIT(6)
26 #define ALT_SGDMA_CONTROL_SOFTWARERESET_MSK BIT(16)
29 * Descriptor control bit masks & offsets
31 * Note: The control byte physically occupies bits [31:24] in memory.
32 * The following bit-offsets are expressed relative to the LSB of
33 * the control register bitfield.
35 #define ALT_SGDMA_DESCRIPTOR_CONTROL_GENERATE_EOP_MSK BIT(0)
36 #define ALT_SGDMA_DESCRIPTOR_CONTROL_READ_FIXED_ADDRESS_MSK BIT(1)
37 #define ALT_SGDMA_DESCRIPTOR_CONTROL_WRITE_FIXED_ADDRESS_MSK BIT(2)
38 #define ALT_SGDMA_DESCRIPTOR_CONTROL_OWNED_BY_HW_MSK BIT(7)
41 * Descriptor status bit masks & offsets
43 * Note: The status byte physically occupies bits [23:16] in memory.
44 * The following bit-offsets are expressed relative to the LSB of
45 * the status register bitfield.
47 #define ALT_SGDMA_DESCRIPTOR_STATUS_TERMINATED_BY_EOP_MSK BIT(7)
50 * The SGDMA controller buffer descriptor allocates
51 * 64 bits for each address. To support ANSI C, the
52 * struct implementing a descriptor places 32-bits
53 * of padding directly above each address; each pad must
54 * be cleared when initializing a descriptor.
58 * Buffer Descriptor data structure
61 struct alt_sgdma_descriptor {
62 u32 source; /* the address of data to be read. */
65 u32 destination; /* the address to write data */
68 u32 next; /* the next descriptor in the list. */
71 u16 bytes_to_transfer; /* the number of bytes to transfer */
75 u16 actual_bytes_transferred;/* bytes transferred by DMA */
77 u8 descriptor_control;
81 /* SG-DMA Control/Status Slave registers map */
83 struct alt_sgdma_registers {
88 u32 next_descriptor_pointer;
89 u32 descriptor_pad[3];
94 /* mSGDMA extended descriptor format */
95 struct msgdma_extended_desc {
96 u32 read_addr_lo; /* data buffer source address low bits */
97 u32 write_addr_lo; /* data buffer destination address low bits */
101 u32 read_addr_hi; /* data buffer source address high bits */
102 u32 write_addr_hi; /* data buffer destination address high bits */
103 u32 control; /* characteristics of the transfer */
106 /* mSGDMA descriptor control field bit definitions */
107 #define MSGDMA_DESC_CTL_GEN_SOP BIT(8)
108 #define MSGDMA_DESC_CTL_GEN_EOP BIT(9)
109 #define MSGDMA_DESC_CTL_END_ON_EOP BIT(12)
110 #define MSGDMA_DESC_CTL_END_ON_LEN BIT(13)
111 #define MSGDMA_DESC_CTL_GO BIT(31)
113 /* Tx buffer control flags */
114 #define MSGDMA_DESC_CTL_TX_SINGLE (MSGDMA_DESC_CTL_GEN_SOP | \
115 MSGDMA_DESC_CTL_GEN_EOP | \
118 #define MSGDMA_DESC_CTL_RX_SINGLE (MSGDMA_DESC_CTL_END_ON_EOP | \
119 MSGDMA_DESC_CTL_END_ON_LEN | \
122 /* mSGDMA extended descriptor stride definitions */
123 #define MSGDMA_DESC_TX_STRIDE 0x00010001
124 #define MSGDMA_DESC_RX_STRIDE 0x00010001
126 /* mSGDMA dispatcher control and status register map */
128 u32 status; /* Read/Clear */
129 u32 control; /* Read/Write */
131 u32 resp_fill_level; /* bit 15:0 */
133 u32 pad[3]; /* reserved */
136 /* mSGDMA CSR status register bit definitions */
137 #define MSGDMA_CSR_STAT_BUSY BIT(0)
138 #define MSGDMA_CSR_STAT_RESETTING BIT(6)
139 #define MSGDMA_CSR_STAT_MASK 0x3FF
141 /* mSGDMA CSR control register bit definitions */
142 #define MSGDMA_CSR_CTL_RESET BIT(1)
144 /* mSGDMA response register map */
145 struct msgdma_response {
146 u32 bytes_transferred;
151 #define ALTERA_TSE_CMD_TX_ENA_MSK BIT(0)
152 #define ALTERA_TSE_CMD_RX_ENA_MSK BIT(1)
153 #define ALTERA_TSE_CMD_ETH_SPEED_MSK BIT(3)
154 #define ALTERA_TSE_CMD_HD_ENA_MSK BIT(10)
155 #define ALTERA_TSE_CMD_SW_RESET_MSK BIT(13)
156 #define ALTERA_TSE_CMD_ENA_10_MSK BIT(25)
158 #define ALT_TSE_SW_RESET_TIMEOUT (3 * CONFIG_SYS_HZ)
159 #define ALT_TSE_SGDMA_BUSY_TIMEOUT (3 * CONFIG_SYS_HZ)
161 /* MAC register Space */
164 u32 megacore_revision;
169 u32 max_frame_length;
171 u32 rx_sel_empty_threshold;
172 u32 rx_sel_full_threshold;
173 u32 tx_sel_empty_threshold;
174 u32 tx_sel_full_threshold;
175 u32 rx_almost_empty_threshold;
176 u32 rx_almost_full_threshold;
177 u32 tx_almost_empty_threshold;
178 u32 tx_almost_full_threshold;
184 /*FIFO control register. */
190 /*Registers 0 to 31 within PHY device 0/1 */
194 /*4 Supplemental MAC Addresses */
195 u32 supp_mac_addr_0_0;
196 u32 supp_mac_addr_0_1;
197 u32 supp_mac_addr_1_0;
198 u32 supp_mac_addr_1_1;
199 u32 supp_mac_addr_2_0;
200 u32 supp_mac_addr_2_1;
201 u32 supp_mac_addr_3_0;
202 u32 supp_mac_addr_3_1;
208 int (*send)(struct udevice *dev, void *packet, int length);
209 int (*recv)(struct udevice *dev, int flags, uchar **packetp);
210 int (*free_pkt)(struct udevice *dev, uchar *packet, int length);
211 void (*stop)(struct udevice *dev);
214 struct altera_tse_priv {
215 struct alt_tse_mac *mac_dev;
218 unsigned int rx_fifo_depth;
219 unsigned int tx_fifo_depth;
223 unsigned char *rx_buf;
224 unsigned int phyaddr;
225 unsigned int interface;
226 struct phy_device *phydev;
228 const struct tse_ops *ops;
232 #endif /* _ALTERA_TSE_H_ */