2 * Altera 10/100/1000 triple speed ethernet mac
4 * Copyright (C) 2008 Altera Corporation.
5 * Copyright (C) 2010 Thomas Chou <thomas@wytron.com.tw>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 #ifndef _ALTERA_TSE_H_
12 #define _ALTERA_TSE_H_
14 #define __packed_1_ __packed __aligned(1)
17 #define ALT_SGDMA_STATUS_BUSY_MSK BIT(4)
19 #define ALT_SGDMA_CONTROL_RUN_MSK BIT(5)
20 #define ALT_SGDMA_CONTROL_STOP_DMA_ER_MSK BIT(6)
21 #define ALT_SGDMA_CONTROL_SOFTWARERESET_MSK BIT(16)
24 * Descriptor control bit masks & offsets
26 * Note: The control byte physically occupies bits [31:24] in memory.
27 * The following bit-offsets are expressed relative to the LSB of
28 * the control register bitfield.
30 #define ALT_SGDMA_DESCRIPTOR_CONTROL_GENERATE_EOP_MSK BIT(0)
31 #define ALT_SGDMA_DESCRIPTOR_CONTROL_READ_FIXED_ADDRESS_MSK BIT(1)
32 #define ALT_SGDMA_DESCRIPTOR_CONTROL_WRITE_FIXED_ADDRESS_MSK BIT(2)
33 #define ALT_SGDMA_DESCRIPTOR_CONTROL_OWNED_BY_HW_MSK BIT(7)
36 * Descriptor status bit masks & offsets
38 * Note: The status byte physically occupies bits [23:16] in memory.
39 * The following bit-offsets are expressed relative to the LSB of
40 * the status register bitfield.
42 #define ALT_SGDMA_DESCRIPTOR_STATUS_TERMINATED_BY_EOP_MSK BIT(7)
45 * The SGDMA controller buffer descriptor allocates
46 * 64 bits for each address. To support ANSI C, the
47 * struct implementing a descriptor places 32-bits
48 * of padding directly above each address; each pad must
49 * be cleared when initializing a descriptor.
53 * Buffer Descriptor data structure
56 struct alt_sgdma_descriptor {
57 u32 source; /* the address of data to be read. */
60 u32 destination; /* the address to write data */
63 u32 next; /* the next descriptor in the list. */
66 u16 bytes_to_transfer; /* the number of bytes to transfer */
70 u16 actual_bytes_transferred;/* bytes transferred by DMA */
72 u8 descriptor_control;
76 /* SG-DMA Control/Status Slave registers map */
78 struct alt_sgdma_registers {
83 u32 next_descriptor_pointer;
84 u32 descriptor_pad[3];
88 #define ALTERA_TSE_CMD_TX_ENA_MSK BIT(0)
89 #define ALTERA_TSE_CMD_RX_ENA_MSK BIT(1)
90 #define ALTERA_TSE_CMD_ETH_SPEED_MSK BIT(3)
91 #define ALTERA_TSE_CMD_HD_ENA_MSK BIT(10)
92 #define ALTERA_TSE_CMD_SW_RESET_MSK BIT(13)
93 #define ALTERA_TSE_CMD_ENA_10_MSK BIT(25)
95 #define ALT_TSE_SW_RESET_TIMEOUT (3 * CONFIG_SYS_HZ)
96 #define ALT_TSE_SGDMA_BUSY_TIMEOUT (3 * CONFIG_SYS_HZ)
98 /* MAC register Space */
101 u32 megacore_revision;
106 u32 max_frame_length;
108 u32 rx_sel_empty_threshold;
109 u32 rx_sel_full_threshold;
110 u32 tx_sel_empty_threshold;
111 u32 tx_sel_full_threshold;
112 u32 rx_almost_empty_threshold;
113 u32 rx_almost_full_threshold;
114 u32 tx_almost_empty_threshold;
115 u32 tx_almost_full_threshold;
121 /*FIFO control register. */
127 /*Registers 0 to 31 within PHY device 0/1 */
131 /*4 Supplemental MAC Addresses */
132 u32 supp_mac_addr_0_0;
133 u32 supp_mac_addr_0_1;
134 u32 supp_mac_addr_1_0;
135 u32 supp_mac_addr_1_1;
136 u32 supp_mac_addr_2_0;
137 u32 supp_mac_addr_2_1;
138 u32 supp_mac_addr_3_0;
139 u32 supp_mac_addr_3_1;
144 struct altera_tse_priv {
145 struct alt_tse_mac *mac_dev;
146 struct alt_sgdma_registers *sgdma_rx;
147 struct alt_sgdma_registers *sgdma_tx;
148 unsigned int rx_fifo_depth;
149 unsigned int tx_fifo_depth;
150 struct alt_sgdma_descriptor *rx_desc;
151 struct alt_sgdma_descriptor *tx_desc;
152 unsigned char *rx_buf;
153 unsigned int phyaddr;
154 unsigned int interface;
155 struct phy_device *phydev;
159 #endif /* _ALTERA_TSE_H_ */