2 * Altera 10/100/1000 triple speed ethernet mac driver
4 * Copyright (C) 2008 Altera Corporation.
5 * Copyright (C) 2010 Thomas Chou <thomas@wytron.com.tw>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
15 #include <fdt_support.h>
19 #include <asm/cache.h>
20 #include <asm/dma-mapping.h>
22 #include "altera_tse.h"
24 DECLARE_GLOBAL_DATA_PTR;
26 static inline void alt_sgdma_construct_descriptor(
27 struct alt_sgdma_descriptor *desc,
28 struct alt_sgdma_descriptor *next,
34 int write_fixed_or_sop)
39 * Mark the "next" descriptor as "not" owned by hardware. This prevents
40 * The SGDMA controller from continuing to process the chain.
42 next->descriptor_control = next->descriptor_control &
43 ~ALT_SGDMA_DESCRIPTOR_CONTROL_OWNED_BY_HW_MSK;
45 memset(desc, 0, sizeof(struct alt_sgdma_descriptor));
46 desc->source = virt_to_phys(read_addr);
47 desc->destination = virt_to_phys(write_addr);
48 desc->next = virt_to_phys(next);
49 desc->bytes_to_transfer = length_or_eop;
52 * Set the descriptor control block as follows:
53 * - Set "owned by hardware" bit
54 * - Optionally set "generate EOP" bit
55 * - Optionally set the "read from fixed address" bit
56 * - Optionally set the "write to fixed address bit (which serves
57 * serves as a "generate SOP" control bit in memory-to-stream mode).
58 * - Set the 4-bit atlantic channel, if specified
60 * Note this step is performed after all other descriptor information
61 * has been filled out so that, if the controller already happens to be
62 * pointing at this descriptor, it will not run (via the "owned by
63 * hardware" bit) until all other descriptor has been set up.
65 val = ALT_SGDMA_DESCRIPTOR_CONTROL_OWNED_BY_HW_MSK;
67 val |= ALT_SGDMA_DESCRIPTOR_CONTROL_GENERATE_EOP_MSK;
69 val |= ALT_SGDMA_DESCRIPTOR_CONTROL_READ_FIXED_ADDRESS_MSK;
70 if (write_fixed_or_sop)
71 val |= ALT_SGDMA_DESCRIPTOR_CONTROL_WRITE_FIXED_ADDRESS_MSK;
72 desc->descriptor_control = val;
75 static int alt_sgdma_wait_transfer(struct alt_sgdma_registers *regs)
80 /* Wait for the descriptor (chain) to complete */
83 status = readl(®s->status);
84 if (!(status & ALT_SGDMA_STATUS_BUSY_MSK))
86 if (get_timer(ctime) > ALT_TSE_SGDMA_BUSY_TIMEOUT) {
88 debug("sgdma timeout\n");
94 writel(0, ®s->control);
96 writel(0xff, ®s->status);
101 static int alt_sgdma_start_transfer(struct alt_sgdma_registers *regs,
102 struct alt_sgdma_descriptor *desc)
106 /* Point the controller at the descriptor */
107 writel(virt_to_phys(desc), ®s->next_descriptor_pointer);
110 * Set up SGDMA controller to:
111 * - Disable interrupt generation
112 * - Run once a valid descriptor is written to controller
113 * - Stop on an error with any particular descriptor
115 val = ALT_SGDMA_CONTROL_RUN_MSK | ALT_SGDMA_CONTROL_STOP_DMA_ER_MSK;
116 writel(val, ®s->control);
121 static void tse_adjust_link(struct altera_tse_priv *priv,
122 struct phy_device *phydev)
124 struct alt_tse_mac *mac_dev = priv->mac_dev;
128 debug("%s: No link.\n", phydev->dev->name);
132 refvar = readl(&mac_dev->command_config);
135 refvar |= ALTERA_TSE_CMD_HD_ENA_MSK;
137 refvar &= ~ALTERA_TSE_CMD_HD_ENA_MSK;
139 switch (phydev->speed) {
141 refvar |= ALTERA_TSE_CMD_ETH_SPEED_MSK;
142 refvar &= ~ALTERA_TSE_CMD_ENA_10_MSK;
145 refvar &= ~ALTERA_TSE_CMD_ETH_SPEED_MSK;
146 refvar &= ~ALTERA_TSE_CMD_ENA_10_MSK;
149 refvar &= ~ALTERA_TSE_CMD_ETH_SPEED_MSK;
150 refvar |= ALTERA_TSE_CMD_ENA_10_MSK;
153 writel(refvar, &mac_dev->command_config);
156 static int altera_tse_send_sgdma(struct udevice *dev, void *packet, int length)
158 struct altera_tse_priv *priv = dev_get_priv(dev);
159 struct alt_sgdma_descriptor *tx_desc = priv->tx_desc;
161 alt_sgdma_construct_descriptor(
164 packet, /* read addr */
165 NULL, /* write addr */
166 length, /* length or EOP ,will change for each tx */
169 1 /* write fixed or sop */
172 /* send the packet */
173 alt_sgdma_start_transfer(priv->sgdma_tx, tx_desc);
174 alt_sgdma_wait_transfer(priv->sgdma_tx);
175 debug("sent %d bytes\n", tx_desc->actual_bytes_transferred);
177 return tx_desc->actual_bytes_transferred;
180 static int altera_tse_recv_sgdma(struct udevice *dev, int flags,
183 struct altera_tse_priv *priv = dev_get_priv(dev);
184 struct alt_sgdma_descriptor *rx_desc = priv->rx_desc;
187 if (rx_desc->descriptor_status &
188 ALT_SGDMA_DESCRIPTOR_STATUS_TERMINATED_BY_EOP_MSK) {
189 alt_sgdma_wait_transfer(priv->sgdma_rx);
190 packet_length = rx_desc->actual_bytes_transferred;
191 debug("recv %d bytes\n", packet_length);
192 *packetp = priv->rx_buf;
194 return packet_length;
200 static int altera_tse_free_pkt_sgdma(struct udevice *dev, uchar *packet,
203 struct altera_tse_priv *priv = dev_get_priv(dev);
204 struct alt_sgdma_descriptor *rx_desc = priv->rx_desc;
206 alt_sgdma_construct_descriptor(
209 NULL, /* read addr */
210 priv->rx_buf, /* write addr */
211 0, /* length or EOP */
214 0 /* write fixed or sop */
217 /* setup the sgdma */
218 alt_sgdma_start_transfer(priv->sgdma_rx, rx_desc);
219 debug("recv setup\n");
224 static void altera_tse_stop_mac(struct altera_tse_priv *priv)
226 struct alt_tse_mac *mac_dev = priv->mac_dev;
231 writel(ALTERA_TSE_CMD_SW_RESET_MSK, &mac_dev->command_config);
232 ctime = get_timer(0);
234 status = readl(&mac_dev->command_config);
235 if (!(status & ALTERA_TSE_CMD_SW_RESET_MSK))
237 if (get_timer(ctime) > ALT_TSE_SW_RESET_TIMEOUT) {
238 debug("Reset mac timeout\n");
244 static void altera_tse_stop_sgdma(struct udevice *dev)
246 struct altera_tse_priv *priv = dev_get_priv(dev);
247 struct alt_sgdma_registers *rx_sgdma = priv->sgdma_rx;
248 struct alt_sgdma_registers *tx_sgdma = priv->sgdma_tx;
249 struct alt_sgdma_descriptor *rx_desc = priv->rx_desc;
252 /* clear rx desc & wait for sgdma to complete */
253 rx_desc->descriptor_control = 0;
254 writel(0, &rx_sgdma->control);
255 ret = alt_sgdma_wait_transfer(rx_sgdma);
256 if (ret == -ETIMEDOUT)
257 writel(ALT_SGDMA_CONTROL_SOFTWARERESET_MSK,
260 writel(0, &tx_sgdma->control);
261 ret = alt_sgdma_wait_transfer(tx_sgdma);
262 if (ret == -ETIMEDOUT)
263 writel(ALT_SGDMA_CONTROL_SOFTWARERESET_MSK,
267 static void msgdma_reset(struct msgdma_csr *csr)
273 writel(MSGDMA_CSR_STAT_MASK, &csr->status);
274 writel(MSGDMA_CSR_CTL_RESET, &csr->control);
275 ctime = get_timer(0);
277 status = readl(&csr->status);
278 if (!(status & MSGDMA_CSR_STAT_RESETTING))
280 if (get_timer(ctime) > ALT_TSE_SW_RESET_TIMEOUT) {
281 debug("Reset msgdma timeout\n");
286 writel(MSGDMA_CSR_STAT_MASK, &csr->status);
289 static u32 msgdma_wait(struct msgdma_csr *csr)
294 /* Wait for the descriptor to complete */
295 ctime = get_timer(0);
297 status = readl(&csr->status);
298 if (!(status & MSGDMA_CSR_STAT_BUSY))
300 if (get_timer(ctime) > ALT_TSE_SGDMA_BUSY_TIMEOUT) {
301 debug("sgdma timeout\n");
306 writel(MSGDMA_CSR_STAT_MASK, &csr->status);
311 static int altera_tse_send_msgdma(struct udevice *dev, void *packet,
314 struct altera_tse_priv *priv = dev_get_priv(dev);
315 struct msgdma_extended_desc *desc = priv->tx_desc;
316 u32 tx_buf = virt_to_phys(packet);
319 writel(tx_buf, &desc->read_addr_lo);
320 writel(0, &desc->read_addr_hi);
321 writel(0, &desc->write_addr_lo);
322 writel(0, &desc->write_addr_hi);
323 writel(length, &desc->len);
324 writel(0, &desc->burst_seq_num);
325 writel(MSGDMA_DESC_TX_STRIDE, &desc->stride);
326 writel(MSGDMA_DESC_CTL_TX_SINGLE, &desc->control);
327 status = msgdma_wait(priv->sgdma_tx);
328 debug("sent %d bytes, status %08x\n", length, status);
333 static int altera_tse_recv_msgdma(struct udevice *dev, int flags,
336 struct altera_tse_priv *priv = dev_get_priv(dev);
337 struct msgdma_csr *csr = priv->sgdma_rx;
338 struct msgdma_response *resp = priv->rx_resp;
339 u32 level, length, status;
341 level = readl(&csr->resp_fill_level);
342 if (level & 0xffff) {
343 length = readl(&resp->bytes_transferred);
344 status = readl(&resp->status);
345 debug("recv %d bytes, status %08x\n", length, status);
346 *packetp = priv->rx_buf;
354 static int altera_tse_free_pkt_msgdma(struct udevice *dev, uchar *packet,
357 struct altera_tse_priv *priv = dev_get_priv(dev);
358 struct msgdma_extended_desc *desc = priv->rx_desc;
359 u32 rx_buf = virt_to_phys(priv->rx_buf);
361 writel(0, &desc->read_addr_lo);
362 writel(0, &desc->read_addr_hi);
363 writel(rx_buf, &desc->write_addr_lo);
364 writel(0, &desc->write_addr_hi);
365 writel(PKTSIZE_ALIGN, &desc->len);
366 writel(0, &desc->burst_seq_num);
367 writel(MSGDMA_DESC_RX_STRIDE, &desc->stride);
368 writel(MSGDMA_DESC_CTL_RX_SINGLE, &desc->control);
369 debug("recv setup\n");
374 static void altera_tse_stop_msgdma(struct udevice *dev)
376 struct altera_tse_priv *priv = dev_get_priv(dev);
378 msgdma_reset(priv->sgdma_rx);
379 msgdma_reset(priv->sgdma_tx);
382 static int tse_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
384 struct altera_tse_priv *priv = bus->priv;
385 struct alt_tse_mac *mac_dev = priv->mac_dev;
388 /* set mdio address */
389 writel(addr, &mac_dev->mdio_phy1_addr);
391 value = readl(&mac_dev->mdio_phy1[reg]);
393 return value & 0xffff;
396 static int tse_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
399 struct altera_tse_priv *priv = bus->priv;
400 struct alt_tse_mac *mac_dev = priv->mac_dev;
402 /* set mdio address */
403 writel(addr, &mac_dev->mdio_phy1_addr);
405 writel(val, &mac_dev->mdio_phy1[reg]);
410 static int tse_mdio_init(const char *name, struct altera_tse_priv *priv)
412 struct mii_dev *bus = mdio_alloc();
415 printf("Failed to allocate MDIO bus\n");
419 bus->read = tse_mdio_read;
420 bus->write = tse_mdio_write;
421 snprintf(bus->name, sizeof(bus->name), "%s", name);
423 bus->priv = (void *)priv;
425 return mdio_register(bus);
428 static int tse_phy_init(struct altera_tse_priv *priv, void *dev)
430 struct phy_device *phydev;
431 unsigned int mask = 0xffffffff;
434 mask = 1 << priv->phyaddr;
436 phydev = phy_find_by_mask(priv->bus, mask, priv->interface);
440 phy_connect_dev(phydev, dev);
442 phydev->supported &= PHY_GBIT_FEATURES;
443 phydev->advertising = phydev->supported;
445 priv->phydev = phydev;
451 static int altera_tse_write_hwaddr(struct udevice *dev)
453 struct altera_tse_priv *priv = dev_get_priv(dev);
454 struct alt_tse_mac *mac_dev = priv->mac_dev;
455 struct eth_pdata *pdata = dev_get_platdata(dev);
456 u8 *hwaddr = pdata->enetaddr;
459 mac_lo = (hwaddr[3] << 24) | (hwaddr[2] << 16) |
460 (hwaddr[1] << 8) | hwaddr[0];
461 mac_hi = (hwaddr[5] << 8) | hwaddr[4];
462 debug("Set MAC address to 0x%04x%08x\n", mac_hi, mac_lo);
464 writel(mac_lo, &mac_dev->mac_addr_0);
465 writel(mac_hi, &mac_dev->mac_addr_1);
466 writel(mac_lo, &mac_dev->supp_mac_addr_0_0);
467 writel(mac_hi, &mac_dev->supp_mac_addr_0_1);
468 writel(mac_lo, &mac_dev->supp_mac_addr_1_0);
469 writel(mac_hi, &mac_dev->supp_mac_addr_1_1);
470 writel(mac_lo, &mac_dev->supp_mac_addr_2_0);
471 writel(mac_hi, &mac_dev->supp_mac_addr_2_1);
472 writel(mac_lo, &mac_dev->supp_mac_addr_3_0);
473 writel(mac_hi, &mac_dev->supp_mac_addr_3_1);
478 static int altera_tse_send(struct udevice *dev, void *packet, int length)
480 struct altera_tse_priv *priv = dev_get_priv(dev);
481 unsigned long tx_buf = (unsigned long)packet;
483 flush_dcache_range(tx_buf, tx_buf + length);
485 return priv->ops->send(dev, packet, length);
488 static int altera_tse_recv(struct udevice *dev, int flags, uchar **packetp)
490 struct altera_tse_priv *priv = dev_get_priv(dev);
492 return priv->ops->recv(dev, flags, packetp);
495 static int altera_tse_free_pkt(struct udevice *dev, uchar *packet,
498 struct altera_tse_priv *priv = dev_get_priv(dev);
499 unsigned long rx_buf = (unsigned long)priv->rx_buf;
501 invalidate_dcache_range(rx_buf, rx_buf + PKTSIZE_ALIGN);
503 return priv->ops->free_pkt(dev, packet, length);
506 static void altera_tse_stop(struct udevice *dev)
508 struct altera_tse_priv *priv = dev_get_priv(dev);
510 priv->ops->stop(dev);
511 altera_tse_stop_mac(priv);
514 static int altera_tse_start(struct udevice *dev)
516 struct altera_tse_priv *priv = dev_get_priv(dev);
517 struct alt_tse_mac *mac_dev = priv->mac_dev;
521 /* need to create sgdma */
522 debug("Configuring rx desc\n");
523 altera_tse_free_pkt(dev, priv->rx_buf, PKTSIZE_ALIGN);
525 debug("Configuring TSE Mac\n");
526 /* Initialize MAC registers */
527 writel(PKTSIZE_ALIGN, &mac_dev->max_frame_length);
528 writel(priv->rx_fifo_depth - 16, &mac_dev->rx_sel_empty_threshold);
529 writel(0, &mac_dev->rx_sel_full_threshold);
530 writel(priv->tx_fifo_depth - 16, &mac_dev->tx_sel_empty_threshold);
531 writel(0, &mac_dev->tx_sel_full_threshold);
532 writel(8, &mac_dev->rx_almost_empty_threshold);
533 writel(8, &mac_dev->rx_almost_full_threshold);
534 writel(8, &mac_dev->tx_almost_empty_threshold);
535 writel(3, &mac_dev->tx_almost_full_threshold);
538 writel(0, &mac_dev->rx_cmd_stat);
539 writel(0, &mac_dev->tx_cmd_stat);
542 val = ALTERA_TSE_CMD_TX_ENA_MSK | ALTERA_TSE_CMD_RX_ENA_MSK;
543 writel(val, &mac_dev->command_config);
545 /* Start up the PHY */
546 ret = phy_startup(priv->phydev);
548 debug("Could not initialize PHY %s\n",
549 priv->phydev->dev->name);
553 tse_adjust_link(priv, priv->phydev);
555 if (!priv->phydev->link)
561 static const struct tse_ops tse_sgdma_ops = {
562 .send = altera_tse_send_sgdma,
563 .recv = altera_tse_recv_sgdma,
564 .free_pkt = altera_tse_free_pkt_sgdma,
565 .stop = altera_tse_stop_sgdma,
568 static const struct tse_ops tse_msgdma_ops = {
569 .send = altera_tse_send_msgdma,
570 .recv = altera_tse_recv_msgdma,
571 .free_pkt = altera_tse_free_pkt_msgdma,
572 .stop = altera_tse_stop_msgdma,
575 static int altera_tse_probe(struct udevice *dev)
577 struct eth_pdata *pdata = dev_get_platdata(dev);
578 struct altera_tse_priv *priv = dev_get_priv(dev);
579 void *blob = (void *)gd->fdt_blob;
580 int node = dev_of_offset(dev);
581 const char *list, *end;
583 void *base, *desc_mem = NULL;
584 unsigned long addr, size;
585 int parent, addrc, sizec;
589 priv->dma_type = dev_get_driver_data(dev);
590 if (priv->dma_type == ALT_SGDMA)
591 priv->ops = &tse_sgdma_ops;
593 priv->ops = &tse_msgdma_ops;
595 * decode regs. there are multiple reg tuples, and they need to
596 * match with reg-names.
598 parent = fdt_parent_offset(blob, node);
599 fdt_support_default_count_cells(blob, parent, &addrc, &sizec);
600 list = fdt_getprop(blob, node, "reg-names", &len);
604 cell = fdt_getprop(blob, node, "reg", &len);
609 addr = fdt_translate_address((void *)blob,
611 size = fdt_addr_to_cpu(cell[idx + addrc]);
612 base = map_physmem(addr, size, MAP_NOCACHE);
614 if (strcmp(list, "control_port") == 0)
615 priv->mac_dev = base;
616 else if (strcmp(list, "rx_csr") == 0)
617 priv->sgdma_rx = base;
618 else if (strcmp(list, "rx_desc") == 0)
619 priv->rx_desc = base;
620 else if (strcmp(list, "rx_resp") == 0)
621 priv->rx_resp = base;
622 else if (strcmp(list, "tx_csr") == 0)
623 priv->sgdma_tx = base;
624 else if (strcmp(list, "tx_desc") == 0)
625 priv->tx_desc = base;
626 else if (strcmp(list, "s1") == 0)
628 idx += addrc + sizec;
631 /* decode fifo depth */
632 priv->rx_fifo_depth = fdtdec_get_int(blob, node,
634 priv->tx_fifo_depth = fdtdec_get_int(blob, node,
637 addr = fdtdec_get_int(blob, node,
639 addr = fdt_node_offset_by_phandle(blob, addr);
640 priv->phyaddr = fdtdec_get_int(blob, addr,
643 if (priv->dma_type == ALT_SGDMA) {
644 len = sizeof(struct alt_sgdma_descriptor) * 4;
646 desc_mem = dma_alloc_coherent(len, &addr);
650 memset(desc_mem, 0, len);
651 priv->tx_desc = desc_mem;
652 priv->rx_desc = priv->tx_desc +
653 2 * sizeof(struct alt_sgdma_descriptor);
655 /* allocate recv packet buffer */
656 priv->rx_buf = malloc_cache_aligned(PKTSIZE_ALIGN);
660 /* stop controller */
661 debug("Reset TSE & SGDMAs\n");
662 altera_tse_stop(dev);
665 priv->interface = pdata->phy_interface;
666 tse_mdio_init(dev->name, priv);
667 priv->bus = miiphy_get_dev_by_name(dev->name);
669 ret = tse_phy_init(priv, dev);
674 static int altera_tse_ofdata_to_platdata(struct udevice *dev)
676 struct eth_pdata *pdata = dev_get_platdata(dev);
677 const char *phy_mode;
679 pdata->phy_interface = -1;
680 phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
683 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
684 if (pdata->phy_interface == -1) {
685 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
692 static const struct eth_ops altera_tse_ops = {
693 .start = altera_tse_start,
694 .send = altera_tse_send,
695 .recv = altera_tse_recv,
696 .free_pkt = altera_tse_free_pkt,
697 .stop = altera_tse_stop,
698 .write_hwaddr = altera_tse_write_hwaddr,
701 static const struct udevice_id altera_tse_ids[] = {
702 { .compatible = "altr,tse-msgdma-1.0", .data = ALT_MSGDMA },
703 { .compatible = "altr,tse-1.0", .data = ALT_SGDMA },
707 U_BOOT_DRIVER(altera_tse) = {
708 .name = "altera_tse",
710 .of_match = altera_tse_ids,
711 .ops = &altera_tse_ops,
712 .ofdata_to_platdata = altera_tse_ofdata_to_platdata,
713 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
714 .priv_auto_alloc_size = sizeof(struct altera_tse_priv),
715 .probe = altera_tse_probe,