1 // SPDX-License-Identifier: GPL-2.0-only
3 * SPI-NOR driver for NXP SPI Flash Interface (SPIFI)
5 * Copyright (C) 2015 Joachim Eastwood <manabian@gmail.com>
7 * Based on Freescale QuadSPI driver:
8 * Copyright (C) 2013 Freescale Semiconductor, Inc.
11 #include <linux/clk.h>
12 #include <linux/err.h>
14 #include <linux/iopoll.h>
15 #include <linux/module.h>
16 #include <linux/mtd/mtd.h>
17 #include <linux/mtd/partitions.h>
18 #include <linux/mtd/spi-nor.h>
20 #include <linux/of_device.h>
21 #include <linux/platform_device.h>
22 #include <linux/spi/spi.h>
24 /* NXP SPIFI registers, bits and macros */
25 #define SPIFI_CTRL 0x000
26 #define SPIFI_CTRL_TIMEOUT(timeout) (timeout)
27 #define SPIFI_CTRL_CSHIGH(cshigh) ((cshigh) << 16)
28 #define SPIFI_CTRL_MODE3 BIT(23)
29 #define SPIFI_CTRL_DUAL BIT(28)
30 #define SPIFI_CTRL_FBCLK BIT(30)
31 #define SPIFI_CMD 0x004
32 #define SPIFI_CMD_DATALEN(dlen) ((dlen) & 0x3fff)
33 #define SPIFI_CMD_DOUT BIT(15)
34 #define SPIFI_CMD_INTLEN(ilen) ((ilen) << 16)
35 #define SPIFI_CMD_FIELDFORM(field) ((field) << 19)
36 #define SPIFI_CMD_FIELDFORM_ALL_SERIAL SPIFI_CMD_FIELDFORM(0x0)
37 #define SPIFI_CMD_FIELDFORM_QUAD_DUAL_DATA SPIFI_CMD_FIELDFORM(0x1)
38 #define SPIFI_CMD_FRAMEFORM(frame) ((frame) << 21)
39 #define SPIFI_CMD_FRAMEFORM_OPCODE_ONLY SPIFI_CMD_FRAMEFORM(0x1)
40 #define SPIFI_CMD_OPCODE(op) ((op) << 24)
41 #define SPIFI_ADDR 0x008
42 #define SPIFI_IDATA 0x00c
43 #define SPIFI_CLIMIT 0x010
44 #define SPIFI_DATA 0x014
45 #define SPIFI_MCMD 0x018
46 #define SPIFI_STAT 0x01c
47 #define SPIFI_STAT_MCINIT BIT(0)
48 #define SPIFI_STAT_CMD BIT(1)
49 #define SPIFI_STAT_RESET BIT(4)
51 #define SPI_NOR_MAX_ID_LEN 6
55 struct clk *clk_spifi;
57 void __iomem *io_base;
58 void __iomem *flash_base;
64 static int nxp_spifi_wait_for_cmd(struct nxp_spifi *spifi)
69 ret = readb_poll_timeout(spifi->io_base + SPIFI_STAT, stat,
70 !(stat & SPIFI_STAT_CMD), 10, 30);
72 dev_warn(spifi->dev, "command timed out\n");
77 static int nxp_spifi_reset(struct nxp_spifi *spifi)
82 writel(SPIFI_STAT_RESET, spifi->io_base + SPIFI_STAT);
83 ret = readb_poll_timeout(spifi->io_base + SPIFI_STAT, stat,
84 !(stat & SPIFI_STAT_RESET), 10, 30);
86 dev_warn(spifi->dev, "state reset timed out\n");
91 static int nxp_spifi_set_memory_mode_off(struct nxp_spifi *spifi)
95 if (!spifi->memory_mode)
98 ret = nxp_spifi_reset(spifi);
100 dev_err(spifi->dev, "unable to enter command mode\n");
102 spifi->memory_mode = false;
107 static int nxp_spifi_set_memory_mode_on(struct nxp_spifi *spifi)
112 if (spifi->memory_mode)
115 writel(spifi->mcmd, spifi->io_base + SPIFI_MCMD);
116 ret = readb_poll_timeout(spifi->io_base + SPIFI_STAT, stat,
117 stat & SPIFI_STAT_MCINIT, 10, 30);
119 dev_err(spifi->dev, "unable to enter memory mode\n");
121 spifi->memory_mode = true;
126 static int nxp_spifi_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
128 struct nxp_spifi *spifi = nor->priv;
132 ret = nxp_spifi_set_memory_mode_off(spifi);
136 cmd = SPIFI_CMD_DATALEN(len) |
137 SPIFI_CMD_OPCODE(opcode) |
138 SPIFI_CMD_FIELDFORM_ALL_SERIAL |
139 SPIFI_CMD_FRAMEFORM_OPCODE_ONLY;
140 writel(cmd, spifi->io_base + SPIFI_CMD);
143 *buf++ = readb(spifi->io_base + SPIFI_DATA);
145 return nxp_spifi_wait_for_cmd(spifi);
148 static int nxp_spifi_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
150 struct nxp_spifi *spifi = nor->priv;
154 ret = nxp_spifi_set_memory_mode_off(spifi);
158 cmd = SPIFI_CMD_DOUT |
159 SPIFI_CMD_DATALEN(len) |
160 SPIFI_CMD_OPCODE(opcode) |
161 SPIFI_CMD_FIELDFORM_ALL_SERIAL |
162 SPIFI_CMD_FRAMEFORM_OPCODE_ONLY;
163 writel(cmd, spifi->io_base + SPIFI_CMD);
166 writeb(*buf++, spifi->io_base + SPIFI_DATA);
168 return nxp_spifi_wait_for_cmd(spifi);
171 static ssize_t nxp_spifi_read(struct spi_nor *nor, loff_t from, size_t len,
174 struct nxp_spifi *spifi = nor->priv;
177 ret = nxp_spifi_set_memory_mode_on(spifi);
181 memcpy_fromio(buf, spifi->flash_base + from, len);
186 static ssize_t nxp_spifi_write(struct spi_nor *nor, loff_t to, size_t len,
189 struct nxp_spifi *spifi = nor->priv;
194 ret = nxp_spifi_set_memory_mode_off(spifi);
198 writel(to, spifi->io_base + SPIFI_ADDR);
200 cmd = SPIFI_CMD_DOUT |
201 SPIFI_CMD_DATALEN(len) |
202 SPIFI_CMD_FIELDFORM_ALL_SERIAL |
203 SPIFI_CMD_OPCODE(nor->program_opcode) |
204 SPIFI_CMD_FRAMEFORM(spifi->nor.addr_width + 1);
205 writel(cmd, spifi->io_base + SPIFI_CMD);
207 for (i = 0; i < len; i++)
208 writeb(buf[i], spifi->io_base + SPIFI_DATA);
210 ret = nxp_spifi_wait_for_cmd(spifi);
217 static int nxp_spifi_erase(struct spi_nor *nor, loff_t offs)
219 struct nxp_spifi *spifi = nor->priv;
223 ret = nxp_spifi_set_memory_mode_off(spifi);
227 writel(offs, spifi->io_base + SPIFI_ADDR);
229 cmd = SPIFI_CMD_FIELDFORM_ALL_SERIAL |
230 SPIFI_CMD_OPCODE(nor->erase_opcode) |
231 SPIFI_CMD_FRAMEFORM(spifi->nor.addr_width + 1);
232 writel(cmd, spifi->io_base + SPIFI_CMD);
234 return nxp_spifi_wait_for_cmd(spifi);
237 static int nxp_spifi_setup_memory_cmd(struct nxp_spifi *spifi)
239 switch (spifi->nor.read_proto) {
240 case SNOR_PROTO_1_1_1:
241 spifi->mcmd = SPIFI_CMD_FIELDFORM_ALL_SERIAL;
243 case SNOR_PROTO_1_1_2:
244 case SNOR_PROTO_1_1_4:
245 spifi->mcmd = SPIFI_CMD_FIELDFORM_QUAD_DUAL_DATA;
248 dev_err(spifi->dev, "unsupported SPI read mode\n");
252 /* Memory mode supports address length between 1 and 4 */
253 if (spifi->nor.addr_width < 1 || spifi->nor.addr_width > 4)
256 spifi->mcmd |= SPIFI_CMD_OPCODE(spifi->nor.read_opcode) |
257 SPIFI_CMD_INTLEN(spifi->nor.read_dummy / 8) |
258 SPIFI_CMD_FRAMEFORM(spifi->nor.addr_width + 1);
263 static void nxp_spifi_dummy_id_read(struct spi_nor *nor)
265 u8 id[SPI_NOR_MAX_ID_LEN];
266 nor->read_reg(nor, SPINOR_OP_RDID, id, SPI_NOR_MAX_ID_LEN);
269 static int nxp_spifi_setup_flash(struct nxp_spifi *spifi,
270 struct device_node *np)
272 struct spi_nor_hwcaps hwcaps = {
273 .mask = SNOR_HWCAPS_READ |
274 SNOR_HWCAPS_READ_FAST |
281 if (!of_property_read_u32(np, "spi-rx-bus-width", &property)) {
292 dev_err(spifi->dev, "unsupported rx-bus-width\n");
297 if (of_find_property(np, "spi-cpha", NULL))
300 if (of_find_property(np, "spi-cpol", NULL))
303 /* Setup control register defaults */
304 ctrl = SPIFI_CTRL_TIMEOUT(1000) |
305 SPIFI_CTRL_CSHIGH(15) |
308 if (mode & SPI_RX_DUAL) {
309 ctrl |= SPIFI_CTRL_DUAL;
310 hwcaps.mask |= SNOR_HWCAPS_READ_1_1_2;
311 } else if (mode & SPI_RX_QUAD) {
312 ctrl &= ~SPIFI_CTRL_DUAL;
313 hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4;
315 ctrl |= SPIFI_CTRL_DUAL;
318 switch (mode & (SPI_CPHA | SPI_CPOL)) {
320 ctrl &= ~SPIFI_CTRL_MODE3;
323 ctrl |= SPIFI_CTRL_MODE3;
326 dev_err(spifi->dev, "only mode 0 and 3 supported\n");
330 writel(ctrl, spifi->io_base + SPIFI_CTRL);
332 spifi->nor.dev = spifi->dev;
333 spi_nor_set_flash_node(&spifi->nor, np);
334 spifi->nor.priv = spifi;
335 spifi->nor.read = nxp_spifi_read;
336 spifi->nor.write = nxp_spifi_write;
337 spifi->nor.erase = nxp_spifi_erase;
338 spifi->nor.read_reg = nxp_spifi_read_reg;
339 spifi->nor.write_reg = nxp_spifi_write_reg;
342 * The first read on a hard reset isn't reliable so do a
343 * dummy read of the id before calling spi_nor_scan().
344 * The reason for this problem is unknown.
346 * The official NXP spifilib uses more or less the same
347 * workaround that is applied here by reading the device
350 nxp_spifi_dummy_id_read(&spifi->nor);
352 ret = spi_nor_scan(&spifi->nor, NULL, &hwcaps);
354 dev_err(spifi->dev, "device scan failed\n");
358 ret = nxp_spifi_setup_memory_cmd(spifi);
360 dev_err(spifi->dev, "memory command setup failed\n");
364 ret = mtd_device_register(&spifi->nor.mtd, NULL, 0);
366 dev_err(spifi->dev, "mtd device parse failed\n");
373 static int nxp_spifi_probe(struct platform_device *pdev)
375 struct device_node *flash_np;
376 struct nxp_spifi *spifi;
377 struct resource *res;
380 spifi = devm_kzalloc(&pdev->dev, sizeof(*spifi), GFP_KERNEL);
384 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "spifi");
385 spifi->io_base = devm_ioremap_resource(&pdev->dev, res);
386 if (IS_ERR(spifi->io_base))
387 return PTR_ERR(spifi->io_base);
389 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "flash");
390 spifi->flash_base = devm_ioremap_resource(&pdev->dev, res);
391 if (IS_ERR(spifi->flash_base))
392 return PTR_ERR(spifi->flash_base);
394 spifi->clk_spifi = devm_clk_get(&pdev->dev, "spifi");
395 if (IS_ERR(spifi->clk_spifi)) {
396 dev_err(&pdev->dev, "spifi clock not found\n");
397 return PTR_ERR(spifi->clk_spifi);
400 spifi->clk_reg = devm_clk_get(&pdev->dev, "reg");
401 if (IS_ERR(spifi->clk_reg)) {
402 dev_err(&pdev->dev, "reg clock not found\n");
403 return PTR_ERR(spifi->clk_reg);
406 ret = clk_prepare_enable(spifi->clk_reg);
408 dev_err(&pdev->dev, "unable to enable reg clock\n");
412 ret = clk_prepare_enable(spifi->clk_spifi);
414 dev_err(&pdev->dev, "unable to enable spifi clock\n");
418 spifi->dev = &pdev->dev;
419 platform_set_drvdata(pdev, spifi);
421 /* Initialize and reset device */
422 nxp_spifi_reset(spifi);
423 writel(0, spifi->io_base + SPIFI_IDATA);
424 writel(0, spifi->io_base + SPIFI_MCMD);
425 nxp_spifi_reset(spifi);
427 flash_np = of_get_next_available_child(pdev->dev.of_node, NULL);
429 dev_err(&pdev->dev, "no SPI flash device to configure\n");
434 ret = nxp_spifi_setup_flash(spifi, flash_np);
435 of_node_put(flash_np);
437 dev_err(&pdev->dev, "unable to setup flash chip\n");
444 clk_disable_unprepare(spifi->clk_spifi);
446 clk_disable_unprepare(spifi->clk_reg);
450 static int nxp_spifi_remove(struct platform_device *pdev)
452 struct nxp_spifi *spifi = platform_get_drvdata(pdev);
454 mtd_device_unregister(&spifi->nor.mtd);
455 clk_disable_unprepare(spifi->clk_spifi);
456 clk_disable_unprepare(spifi->clk_reg);
461 static const struct of_device_id nxp_spifi_match[] = {
462 {.compatible = "nxp,lpc1773-spifi"},
465 MODULE_DEVICE_TABLE(of, nxp_spifi_match);
467 static struct platform_driver nxp_spifi_driver = {
468 .probe = nxp_spifi_probe,
469 .remove = nxp_spifi_remove,
472 .of_match_table = nxp_spifi_match,
475 module_platform_driver(nxp_spifi_driver);
477 MODULE_DESCRIPTION("NXP SPI Flash Interface driver");
478 MODULE_AUTHOR("Joachim Eastwood <manabian@gmail.com>");
479 MODULE_LICENSE("GPL v2");