2 * Copyright (C) 2016 Siarhei Siamashka <siarhei.siamashka@gmail.com>
4 * SPDX-License-Identifier: GPL-2.0+
12 #ifdef CONFIG_SPL_OS_BOOT
13 #error CONFIG_SPL_OS_BOOT is not supported yet
17 * This is a very simple U-Boot image loading implementation, trying to
18 * replicate what the boot ROM is doing when loading the SPL. Because we
19 * know the exact pins where the SPI Flash is connected and also know
20 * that the Read Data Bytes (03h) command is supported, the hardware
21 * configuration is very simple and we don't need the extra flexibility
22 * of the SPI framework. Moreover, we rely on the default settings of
23 * the SPI controler hardware registers and only adjust what needs to
24 * be changed. This is good for the code size and this implementation
25 * adds less than 400 bytes to the SPL.
27 * There are two variants of the SPI controller in Allwinner SoCs:
28 * A10/A13/A20 (sun4i variant) and everything else (sun6i variant).
29 * Both of them are supported.
31 * The pin mixing part is SoC specific and only A10/A13/A20/H3/A64 are
32 * supported at the moment.
35 /*****************************************************************************/
36 /* SUN4I variant of the SPI controller */
37 /*****************************************************************************/
39 #define SUN4I_SPI0_CCTL (0x01C05000 + 0x1C)
40 #define SUN4I_SPI0_CTL (0x01C05000 + 0x08)
41 #define SUN4I_SPI0_RX (0x01C05000 + 0x00)
42 #define SUN4I_SPI0_TX (0x01C05000 + 0x04)
43 #define SUN4I_SPI0_FIFO_STA (0x01C05000 + 0x28)
44 #define SUN4I_SPI0_BC (0x01C05000 + 0x20)
45 #define SUN4I_SPI0_TC (0x01C05000 + 0x24)
47 #define SUN4I_CTL_ENABLE BIT(0)
48 #define SUN4I_CTL_MASTER BIT(1)
49 #define SUN4I_CTL_TF_RST BIT(8)
50 #define SUN4I_CTL_RF_RST BIT(9)
51 #define SUN4I_CTL_XCH BIT(10)
53 /*****************************************************************************/
54 /* SUN6I variant of the SPI controller */
55 /*****************************************************************************/
57 #define SUN6I_SPI0_CCTL (0x01C68000 + 0x24)
58 #define SUN6I_SPI0_GCR (0x01C68000 + 0x04)
59 #define SUN6I_SPI0_TCR (0x01C68000 + 0x08)
60 #define SUN6I_SPI0_FIFO_STA (0x01C68000 + 0x1C)
61 #define SUN6I_SPI0_MBC (0x01C68000 + 0x30)
62 #define SUN6I_SPI0_MTC (0x01C68000 + 0x34)
63 #define SUN6I_SPI0_BCC (0x01C68000 + 0x38)
64 #define SUN6I_SPI0_TXD (0x01C68000 + 0x200)
65 #define SUN6I_SPI0_RXD (0x01C68000 + 0x300)
67 #define SUN6I_CTL_ENABLE BIT(0)
68 #define SUN6I_CTL_MASTER BIT(1)
69 #define SUN6I_CTL_SRST BIT(31)
70 #define SUN6I_TCR_XCH BIT(31)
72 /*****************************************************************************/
74 #define CCM_AHB_GATING0 (0x01C20000 + 0x60)
75 #define CCM_SPI0_CLK (0x01C20000 + 0xA0)
76 #define SUN6I_BUS_SOFT_RST_REG0 (0x01C20000 + 0x2C0)
78 #define AHB_RESET_SPI0_SHIFT 20
79 #define AHB_GATE_OFFSET_SPI0 20
81 #define SPI0_CLK_DIV_BY_2 0x1000
82 #define SPI0_CLK_DIV_BY_4 0x1001
84 /*****************************************************************************/
87 * Allwinner A10/A20 SoCs were using pins PC0,PC1,PC2,PC23 for booting
88 * from SPI Flash, everything else is using pins PC0,PC1,PC2,PC3.
90 static void spi0_pinmux_setup(unsigned int pin_function)
94 for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(2); pin++)
95 sunxi_gpio_set_cfgpin(pin, pin_function);
97 if (IS_ENABLED(CONFIG_MACH_SUN4I) || IS_ENABLED(CONFIG_MACH_SUN7I))
98 sunxi_gpio_set_cfgpin(SUNXI_GPC(23), pin_function);
100 sunxi_gpio_set_cfgpin(SUNXI_GPC(3), pin_function);
104 * Setup 6 MHz from OSC24M (because the BROM is doing the same).
106 static void spi0_enable_clock(void)
108 /* Deassert SPI0 reset on SUN6I */
109 if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I))
110 setbits_le32(SUN6I_BUS_SOFT_RST_REG0,
111 (1 << AHB_RESET_SPI0_SHIFT));
113 /* Open the SPI0 gate */
114 setbits_le32(CCM_AHB_GATING0, (1 << AHB_GATE_OFFSET_SPI0));
117 writel(SPI0_CLK_DIV_BY_4, IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I) ?
118 SUN6I_SPI0_CCTL : SUN4I_SPI0_CCTL);
119 /* 24MHz from OSC24M */
120 writel((1 << 31), CCM_SPI0_CLK);
122 if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I)) {
123 /* Enable SPI in the master mode and do a soft reset */
124 setbits_le32(SUN6I_SPI0_GCR, SUN6I_CTL_MASTER |
127 /* Wait for completion */
128 while (readl(SUN6I_SPI0_GCR) & SUN6I_CTL_SRST)
131 /* Enable SPI in the master mode and reset FIFO */
132 setbits_le32(SUN4I_SPI0_CTL, SUN4I_CTL_MASTER |
139 static void spi0_disable_clock(void)
141 /* Disable the SPI0 controller */
142 if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I))
143 clrbits_le32(SUN6I_SPI0_GCR, SUN6I_CTL_MASTER |
146 clrbits_le32(SUN4I_SPI0_CTL, SUN4I_CTL_MASTER |
149 /* Disable the SPI0 clock */
150 writel(0, CCM_SPI0_CLK);
152 /* Close the SPI0 gate */
153 clrbits_le32(CCM_AHB_GATING0, (1 << AHB_GATE_OFFSET_SPI0));
155 /* Assert SPI0 reset on SUN6I */
156 if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I))
157 clrbits_le32(SUN6I_BUS_SOFT_RST_REG0,
158 (1 << AHB_RESET_SPI0_SHIFT));
161 static int spi0_init(void)
163 unsigned int pin_function = SUNXI_GPC_SPI0;
164 if (IS_ENABLED(CONFIG_MACH_SUN50I))
165 pin_function = SUN50I_GPC_SPI0;
167 spi0_pinmux_setup(pin_function);
171 static void spi0_deinit(void)
173 /* New SoCs can disable pins, older could only set them as input */
174 unsigned int pin_function = SUNXI_GPIO_INPUT;
175 if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I))
176 pin_function = SUNXI_GPIO_DISABLE;
178 spi0_disable_clock();
179 spi0_pinmux_setup(pin_function);
182 /*****************************************************************************/
184 #define SPI_READ_MAX_SIZE 60 /* FIFO size, minus 4 bytes of the header */
186 static void sunxi_spi0_read_data(u8 *buf, u32 addr, u32 bufsize,
188 u32 spi_ctl_xch_bitmask,
196 writel(4 + bufsize, spi_bc_reg); /* Burst counter (total bytes) */
197 writel(4, spi_tc_reg); /* Transfer counter (bytes to send) */
199 writel(4, spi_bcc_reg); /* SUN6I also needs this */
201 /* Send the Read Data Bytes (03h) command header */
202 writeb(0x03, spi_tx_reg);
203 writeb((u8)(addr >> 16), spi_tx_reg);
204 writeb((u8)(addr >> 8), spi_tx_reg);
205 writeb((u8)(addr), spi_tx_reg);
207 /* Start the data transfer */
208 setbits_le32(spi_ctl_reg, spi_ctl_xch_bitmask);
210 /* Wait until everything is received in the RX FIFO */
211 while ((readl(spi_fifo_reg) & 0x7F) < 4 + bufsize)
218 while (bufsize-- > 0)
219 *buf++ = readb(spi_rx_reg);
221 /* tSHSL time is up to 100 ns in various SPI flash datasheets */
225 static void spi0_read_data(void *buf, u32 addr, u32 len)
232 if (chunk_len > SPI_READ_MAX_SIZE)
233 chunk_len = SPI_READ_MAX_SIZE;
235 if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I)) {
236 sunxi_spi0_read_data(buf8, addr, chunk_len,
246 sunxi_spi0_read_data(buf8, addr, chunk_len,
263 /*****************************************************************************/
265 int spl_spi_load_image(void)
268 struct image_header *header;
269 header = (struct image_header *)(CONFIG_SYS_TEXT_BASE);
273 spi0_read_data((void *)header, CONFIG_SYS_SPI_U_BOOT_OFFS, 0x40);
274 err = spl_parse_image_header(&spl_image, header);
278 spi0_read_data((void *)spl_image.load_addr, CONFIG_SYS_SPI_U_BOOT_OFFS,