4 * Copyright (C) 2015 Jagan Teki <jteki@openedev.com>
5 * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc.
6 * Copyright (C) 2010 Reinhard Meyer, EMK Elektronik
7 * Copyright (C) 2008 Atmel Corporation
9 * SPDX-License-Identifier: GPL-2.0+
17 #include <spi_flash.h>
18 #include <linux/log2.h>
21 #include "sf_internal.h"
23 DECLARE_GLOBAL_DATA_PTR;
25 static void spi_flash_addr(u32 addr, u8 *cmd)
27 /* cmd[0] is actual command */
33 static int read_sr(struct spi_flash *flash, u8 *rs)
38 cmd = CMD_READ_STATUS;
39 ret = spi_flash_read_common(flash, &cmd, 1, rs, 1);
41 debug("SF: fail to read status register\n");
48 static int read_fsr(struct spi_flash *flash, u8 *fsr)
51 const u8 cmd = CMD_FLAG_STATUS;
53 ret = spi_flash_read_common(flash, &cmd, 1, fsr, 1);
55 debug("SF: fail to read flag status register\n");
62 static int write_sr(struct spi_flash *flash, u8 ws)
67 cmd = CMD_WRITE_STATUS;
68 ret = spi_flash_write_common(flash, &cmd, 1, &ws, 1);
70 debug("SF: fail to write status register\n");
77 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
78 static int read_cr(struct spi_flash *flash, u8 *rc)
83 cmd = CMD_READ_CONFIG;
84 ret = spi_flash_read_common(flash, &cmd, 1, rc, 1);
86 debug("SF: fail to read config register\n");
93 static int write_cr(struct spi_flash *flash, u8 wc)
99 ret = read_sr(flash, &data[0]);
103 cmd = CMD_WRITE_STATUS;
105 ret = spi_flash_write_common(flash, &cmd, 1, &data, 2);
107 debug("SF: fail to write config register\n");
115 #ifdef CONFIG_SPI_FLASH_BAR
116 static int write_bar(struct spi_flash *flash, u32 offset)
121 bank_sel = offset / (SPI_FLASH_16MB_BOUN << flash->shift);
122 if (bank_sel == flash->bank_curr)
125 cmd = flash->bank_write_cmd;
126 ret = spi_flash_write_common(flash, &cmd, 1, &bank_sel, 1);
128 debug("SF: fail to write bank register\n");
133 flash->bank_curr = bank_sel;
134 return flash->bank_curr;
137 static int read_bar(struct spi_flash *flash, const struct spi_flash_info *info)
142 if (flash->size <= SPI_FLASH_16MB_BOUN)
145 switch (JEDEC_MFR(info)) {
146 case SPI_FLASH_CFI_MFR_SPANSION:
147 flash->bank_read_cmd = CMD_BANKADDR_BRRD;
148 flash->bank_write_cmd = CMD_BANKADDR_BRWR;
151 flash->bank_read_cmd = CMD_EXTNADDR_RDEAR;
152 flash->bank_write_cmd = CMD_EXTNADDR_WREAR;
155 ret = spi_flash_read_common(flash, &flash->bank_read_cmd, 1,
158 debug("SF: fail to read bank addr register\n");
163 flash->bank_curr = curr_bank;
168 #ifdef CONFIG_SF_DUAL_FLASH
169 static void spi_flash_dual(struct spi_flash *flash, u32 *addr)
171 switch (flash->dual_flash) {
172 case SF_DUAL_STACKED_FLASH:
173 if (*addr >= (flash->size >> 1)) {
174 *addr -= flash->size >> 1;
175 flash->flags |= SNOR_F_USE_UPAGE;
177 flash->flags &= ~SNOR_F_USE_UPAGE;
180 case SF_DUAL_PARALLEL_FLASH:
181 *addr >>= flash->shift;
184 debug("SF: Unsupported dual_flash=%d\n", flash->dual_flash);
190 static int spi_flash_sr_ready(struct spi_flash *flash)
195 ret = read_sr(flash, &sr);
199 return !(sr & STATUS_WIP);
202 static int spi_flash_fsr_ready(struct spi_flash *flash)
207 ret = read_fsr(flash, &fsr);
211 return fsr & STATUS_PEC;
214 static int spi_flash_ready(struct spi_flash *flash)
218 sr = spi_flash_sr_ready(flash);
223 if (flash->flags & SNOR_F_USE_FSR) {
224 fsr = spi_flash_fsr_ready(flash);
232 static int spi_flash_wait_till_ready(struct spi_flash *flash,
233 unsigned long timeout)
235 unsigned long timebase;
238 timebase = get_timer(0);
240 while (get_timer(timebase) < timeout) {
241 ret = spi_flash_ready(flash);
248 printf("SF: Timeout!\n");
253 int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd,
254 size_t cmd_len, const void *buf, size_t buf_len)
256 struct spi_slave *spi = flash->spi;
257 unsigned long timeout = SPI_FLASH_PROG_TIMEOUT;
261 timeout = SPI_FLASH_PAGE_ERASE_TIMEOUT;
263 ret = spi_claim_bus(spi);
265 debug("SF: unable to claim SPI bus\n");
269 ret = spi_flash_cmd_write_enable(flash);
271 debug("SF: enabling write failed\n");
275 ret = spi_flash_cmd_write(spi, cmd, cmd_len, buf, buf_len);
277 debug("SF: write cmd failed\n");
281 ret = spi_flash_wait_till_ready(flash, timeout);
283 debug("SF: write %s timed out\n",
284 timeout == SPI_FLASH_PROG_TIMEOUT ?
285 "program" : "page erase");
289 spi_release_bus(spi);
294 int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len)
296 u32 erase_size, erase_addr;
297 u8 cmd[SPI_FLASH_CMD_LEN];
300 erase_size = flash->erase_size;
301 if (offset % erase_size || len % erase_size) {
302 debug("SF: Erase offset/length not multiple of erase size\n");
306 if (flash->flash_is_locked) {
307 if (flash->flash_is_locked(flash, offset, len) > 0) {
308 printf("offset 0x%x is protected and cannot be erased\n",
314 cmd[0] = flash->erase_cmd;
318 #ifdef CONFIG_SF_DUAL_FLASH
319 if (flash->dual_flash > SF_SINGLE_FLASH)
320 spi_flash_dual(flash, &erase_addr);
322 #ifdef CONFIG_SPI_FLASH_BAR
323 ret = write_bar(flash, erase_addr);
327 spi_flash_addr(erase_addr, cmd);
329 debug("SF: erase %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1],
330 cmd[2], cmd[3], erase_addr);
332 ret = spi_flash_write_common(flash, cmd, sizeof(cmd), NULL, 0);
334 debug("SF: erase failed\n");
338 offset += erase_size;
345 int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,
346 size_t len, const void *buf)
348 struct spi_slave *spi = flash->spi;
349 unsigned long byte_addr, page_size;
351 size_t chunk_len, actual;
352 u8 cmd[SPI_FLASH_CMD_LEN];
355 page_size = flash->page_size;
357 if (flash->flash_is_locked) {
358 if (flash->flash_is_locked(flash, offset, len) > 0) {
359 printf("offset 0x%x is protected and cannot be written\n",
365 cmd[0] = flash->write_cmd;
366 for (actual = 0; actual < len; actual += chunk_len) {
369 #ifdef CONFIG_SF_DUAL_FLASH
370 if (flash->dual_flash > SF_SINGLE_FLASH)
371 spi_flash_dual(flash, &write_addr);
373 #ifdef CONFIG_SPI_FLASH_BAR
374 ret = write_bar(flash, write_addr);
378 byte_addr = offset % page_size;
379 chunk_len = min(len - actual, (size_t)(page_size - byte_addr));
381 if (spi->max_write_size)
382 chunk_len = min(chunk_len,
383 (size_t)spi->max_write_size);
385 spi_flash_addr(write_addr, cmd);
387 debug("SF: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu\n",
388 buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len);
390 ret = spi_flash_write_common(flash, cmd, sizeof(cmd),
391 buf + actual, chunk_len);
393 debug("SF: write failed\n");
403 int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd,
404 size_t cmd_len, void *data, size_t data_len)
406 struct spi_slave *spi = flash->spi;
409 ret = spi_claim_bus(spi);
411 debug("SF: unable to claim SPI bus\n");
415 ret = spi_flash_cmd_read(spi, cmd, cmd_len, data, data_len);
417 debug("SF: read cmd failed\n");
421 spi_release_bus(spi);
427 * TODO: remove the weak after all the other spi_flash_copy_mmap
428 * implementations removed from drivers
430 void __weak spi_flash_copy_mmap(void *data, void *offset, size_t len)
433 if (!dma_memcpy(data, offset, len))
436 memcpy(data, offset, len);
439 int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
440 size_t len, void *data)
442 struct spi_slave *spi = flash->spi;
444 u32 remain_len, read_len, read_addr;
448 /* Handle memory-mapped SPI */
449 if (flash->memory_map) {
450 ret = spi_claim_bus(spi);
452 debug("SF: unable to claim SPI bus\n");
455 spi_xfer(spi, 0, NULL, NULL, SPI_XFER_MMAP);
456 spi_flash_copy_mmap(data, flash->memory_map + offset, len);
457 spi_xfer(spi, 0, NULL, NULL, SPI_XFER_MMAP_END);
458 spi_release_bus(spi);
462 cmdsz = SPI_FLASH_CMD_LEN + flash->dummy_byte;
463 cmd = calloc(1, cmdsz);
465 debug("SF: Failed to allocate cmd\n");
469 cmd[0] = flash->read_cmd;
473 #ifdef CONFIG_SF_DUAL_FLASH
474 if (flash->dual_flash > SF_SINGLE_FLASH)
475 spi_flash_dual(flash, &read_addr);
477 #ifdef CONFIG_SPI_FLASH_BAR
478 ret = write_bar(flash, read_addr);
481 bank_sel = flash->bank_curr;
483 remain_len = ((SPI_FLASH_16MB_BOUN << flash->shift) *
484 (bank_sel + 1)) - offset;
485 if (len < remain_len)
488 read_len = remain_len;
490 spi_flash_addr(read_addr, cmd);
492 ret = spi_flash_read_common(flash, cmd, cmdsz, data, read_len);
494 debug("SF: read failed\n");
507 #ifdef CONFIG_SPI_FLASH_SST
508 static int sst_byte_write(struct spi_flash *flash, u32 offset, const void *buf)
510 struct spi_slave *spi = flash->spi;
519 debug("BP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x }\n",
520 spi_w8r8(spi, CMD_READ_STATUS), buf, cmd[0], offset);
522 ret = spi_flash_cmd_write_enable(flash);
526 ret = spi_flash_cmd_write(spi, cmd, sizeof(cmd), buf, 1);
530 return spi_flash_wait_till_ready(flash, SPI_FLASH_PROG_TIMEOUT);
533 int sst_write_wp(struct spi_flash *flash, u32 offset, size_t len,
536 struct spi_slave *spi = flash->spi;
537 size_t actual, cmd_len;
541 ret = spi_claim_bus(spi);
543 debug("SF: Unable to claim SPI bus\n");
547 /* If the data is not word aligned, write out leading single byte */
550 ret = sst_byte_write(flash, offset, buf);
556 ret = spi_flash_cmd_write_enable(flash);
561 cmd[0] = CMD_SST_AAI_WP;
562 cmd[1] = offset >> 16;
563 cmd[2] = offset >> 8;
566 for (; actual < len - 1; actual += 2) {
567 debug("WP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x }\n",
568 spi_w8r8(spi, CMD_READ_STATUS), buf + actual,
571 ret = spi_flash_cmd_write(spi, cmd, cmd_len,
574 debug("SF: sst word program failed\n");
578 ret = spi_flash_wait_till_ready(flash, SPI_FLASH_PROG_TIMEOUT);
587 ret = spi_flash_cmd_write_disable(flash);
589 /* If there is a single trailing byte, write it out */
590 if (!ret && actual != len)
591 ret = sst_byte_write(flash, offset, buf + actual);
594 debug("SF: sst: program %s %zu bytes @ 0x%zx\n",
595 ret ? "failure" : "success", len, offset - actual);
597 spi_release_bus(spi);
601 int sst_write_bp(struct spi_flash *flash, u32 offset, size_t len,
604 struct spi_slave *spi = flash->spi;
608 ret = spi_claim_bus(spi);
610 debug("SF: Unable to claim SPI bus\n");
614 for (actual = 0; actual < len; actual++) {
615 ret = sst_byte_write(flash, offset, buf + actual);
617 debug("SF: sst byte program failed\n");
624 ret = spi_flash_cmd_write_disable(flash);
626 debug("SF: sst: program %s %zu bytes @ 0x%zx\n",
627 ret ? "failure" : "success", len, offset - actual);
629 spi_release_bus(spi);
634 #if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST)
635 static void stm_get_locked_range(struct spi_flash *flash, u8 sr, loff_t *ofs,
638 u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
639 int shift = ffs(mask) - 1;
647 pow = ((sr & mask) ^ mask) >> shift;
648 *len = flash->size >> pow;
649 *ofs = flash->size - *len;
654 * Return 1 if the entire region is locked, 0 otherwise
656 static int stm_is_locked_sr(struct spi_flash *flash, loff_t ofs, u64 len,
662 stm_get_locked_range(flash, sr, &lock_offs, &lock_len);
664 return (ofs + len <= lock_offs + lock_len) && (ofs >= lock_offs);
668 * Check if a region of the flash is (completely) locked. See stm_lock() for
671 * Returns 1 if entire region is locked, 0 if any portion is unlocked, and
672 * negative on errors.
674 int stm_is_locked(struct spi_flash *flash, u32 ofs, size_t len)
679 status = read_sr(flash, &sr);
683 return stm_is_locked_sr(flash, ofs, len, sr);
687 * Lock a region of the flash. Compatible with ST Micro and similar flash.
688 * Supports only the block protection bits BP{0,1,2} in the status register
689 * (SR). Does not support these features found in newer SR bitfields:
690 * - TB: top/bottom protect - only handle TB=0 (top protect)
691 * - SEC: sector/block protect - only handle SEC=0 (block protect)
692 * - CMP: complement protect - only support CMP=0 (range is not complemented)
694 * Sample table portion for 8MB flash (Winbond w25q64fw):
696 * SEC | TB | BP2 | BP1 | BP0 | Prot Length | Protected Portion
697 * --------------------------------------------------------------------------
698 * X | X | 0 | 0 | 0 | NONE | NONE
699 * 0 | 0 | 0 | 0 | 1 | 128 KB | Upper 1/64
700 * 0 | 0 | 0 | 1 | 0 | 256 KB | Upper 1/32
701 * 0 | 0 | 0 | 1 | 1 | 512 KB | Upper 1/16
702 * 0 | 0 | 1 | 0 | 0 | 1 MB | Upper 1/8
703 * 0 | 0 | 1 | 0 | 1 | 2 MB | Upper 1/4
704 * 0 | 0 | 1 | 1 | 0 | 4 MB | Upper 1/2
705 * X | X | 1 | 1 | 1 | 8 MB | ALL
707 * Returns negative on errors, 0 on success.
709 int stm_lock(struct spi_flash *flash, u32 ofs, size_t len)
711 u8 status_old, status_new;
712 u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
713 u8 shift = ffs(mask) - 1, pow, val;
716 ret = read_sr(flash, &status_old);
720 /* SPI NOR always locks to the end */
721 if (ofs + len != flash->size) {
722 /* Does combined region extend to end? */
723 if (!stm_is_locked_sr(flash, ofs + len, flash->size - ofs - len,
726 len = flash->size - ofs;
730 * Need smallest pow such that:
732 * 1 / (2^pow) <= (len / size)
734 * so (assuming power-of-2 size) we do:
736 * pow = ceil(log2(size / len)) = log2(size) - floor(log2(len))
738 pow = ilog2(flash->size) - ilog2(len);
739 val = mask - (pow << shift);
743 /* Don't "lock" with no region! */
747 status_new = (status_old & ~mask) | val;
749 /* Only modify protection if it will not unlock other areas */
750 if ((status_new & mask) <= (status_old & mask))
753 write_sr(flash, status_new);
759 * Unlock a region of the flash. See stm_lock() for more info
761 * Returns negative on errors, 0 on success.
763 int stm_unlock(struct spi_flash *flash, u32 ofs, size_t len)
765 uint8_t status_old, status_new;
766 u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
767 u8 shift = ffs(mask) - 1, pow, val;
770 ret = read_sr(flash, &status_old);
774 /* Cannot unlock; would unlock larger region than requested */
775 if (stm_is_locked_sr(flash, ofs - flash->erase_size, flash->erase_size,
779 * Need largest pow such that:
781 * 1 / (2^pow) >= (len / size)
783 * so (assuming power-of-2 size) we do:
785 * pow = floor(log2(size / len)) = log2(size) - ceil(log2(len))
787 pow = ilog2(flash->size) - order_base_2(flash->size - (ofs + len));
788 if (ofs + len == flash->size) {
789 val = 0; /* fully unlocked */
791 val = mask - (pow << shift);
792 /* Some power-of-two sizes are not supported */
797 status_new = (status_old & ~mask) | val;
799 /* Only modify protection if it will not lock other areas */
800 if ((status_new & mask) >= (status_old & mask))
803 write_sr(flash, status_new);
810 #ifdef CONFIG_SPI_FLASH_MACRONIX
811 static int macronix_quad_enable(struct spi_flash *flash)
816 ret = read_sr(flash, &qeb_status);
820 if (qeb_status & STATUS_QEB_MXIC)
823 ret = write_sr(flash, qeb_status | STATUS_QEB_MXIC);
827 /* read SR and check it */
828 ret = read_sr(flash, &qeb_status);
829 if (!(ret >= 0 && (qeb_status & STATUS_QEB_MXIC))) {
830 printf("SF: Macronix SR Quad bit not clear\n");
838 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
839 static int spansion_quad_enable(struct spi_flash *flash)
844 ret = read_cr(flash, &qeb_status);
848 if (qeb_status & STATUS_QEB_WINSPAN)
851 ret = write_cr(flash, qeb_status | STATUS_QEB_WINSPAN);
855 /* read CR and check it */
856 ret = read_cr(flash, &qeb_status);
857 if (!(ret >= 0 && (qeb_status & STATUS_QEB_WINSPAN))) {
858 printf("SF: Spansion CR Quad bit not clear\n");
866 static const struct spi_flash_info *spi_flash_read_id(struct spi_flash *flash)
869 u8 id[SPI_FLASH_MAX_ID_LEN];
870 const struct spi_flash_info *info;
872 tmp = spi_flash_cmd(flash->spi, CMD_READ_ID, id, SPI_FLASH_MAX_ID_LEN);
874 printf("SF: error %d reading JEDEC ID\n", tmp);
878 info = spi_flash_ids;
879 for (; info->name != NULL; info++) {
881 if (!memcmp(info->id, id, info->id_len))
886 printf("SF: unrecognized JEDEC id bytes: %02x, %02x, %02x\n",
887 id[0], id[1], id[2]);
888 return ERR_PTR(-ENODEV);
891 static int set_quad_mode(struct spi_flash *flash,
892 const struct spi_flash_info *info)
894 switch (JEDEC_MFR(info)) {
895 #ifdef CONFIG_SPI_FLASH_MACRONIX
896 case SPI_FLASH_CFI_MFR_MACRONIX:
897 return macronix_quad_enable(flash);
899 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
900 case SPI_FLASH_CFI_MFR_SPANSION:
901 case SPI_FLASH_CFI_MFR_WINBOND:
902 return spansion_quad_enable(flash);
904 #ifdef CONFIG_SPI_FLASH_STMICRO
905 case SPI_FLASH_CFI_MFR_STMICRO:
906 debug("SF: QEB is volatile for %02x flash\n", JEDEC_MFR(info));
910 printf("SF: Need set QEB func for %02x flash\n",
916 #if CONFIG_IS_ENABLED(OF_CONTROL)
917 int spi_flash_decode_fdt(struct spi_flash *flash)
919 #ifdef CONFIG_DM_SPI_FLASH
923 addr = dev_read_addr_size(flash->dev, "memory-map", &size);
924 if (addr == FDT_ADDR_T_NONE) {
925 debug("%s: Cannot decode address\n", __func__);
929 if (flash->size > size) {
930 debug("%s: Memory map must cover entire device\n", __func__);
933 flash->memory_map = map_sysmem(addr, size);
938 #endif /* CONFIG_IS_ENABLED(OF_CONTROL) */
940 int spi_flash_scan(struct spi_flash *flash)
942 struct spi_slave *spi = flash->spi;
943 const struct spi_flash_info *info = NULL;
946 info = spi_flash_read_id(flash);
947 if (IS_ERR_OR_NULL(info))
951 * Flash powers up read-only, so clear BP# bits.
953 * Note on some flash (like Macronix), QE (quad enable) bit is in the
954 * same status register as BP# bits, and we need preserve its original
955 * value during a reboot cycle as this is required by some platforms
956 * (like Intel ICH SPI controller working under descriptor mode).
958 if (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_ATMEL ||
959 (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_SST) ||
960 (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_MACRONIX)) {
963 if (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_MACRONIX) {
965 sr &= STATUS_QEB_MXIC;
970 flash->name = info->name;
971 flash->memory_map = spi->memory_map;
973 if (info->flags & SST_WR)
974 flash->flags |= SNOR_F_SST_WR;
976 #ifndef CONFIG_DM_SPI_FLASH
977 flash->write = spi_flash_cmd_write_ops;
978 #if defined(CONFIG_SPI_FLASH_SST)
979 if (flash->flags & SNOR_F_SST_WR) {
980 if (spi->mode & SPI_TX_BYTE)
981 flash->write = sst_write_bp;
983 flash->write = sst_write_wp;
986 flash->erase = spi_flash_cmd_erase_ops;
987 flash->read = spi_flash_cmd_read_ops;
990 #if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST)
991 /* NOR protection support for STmicro/Micron chips and similar */
992 if (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_STMICRO ||
993 JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_SST) {
994 flash->flash_lock = stm_lock;
995 flash->flash_unlock = stm_unlock;
996 flash->flash_is_locked = stm_is_locked;
1000 /* Compute the flash size */
1001 flash->shift = (flash->dual_flash & SF_DUAL_PARALLEL_FLASH) ? 1 : 0;
1002 flash->page_size = info->page_size;
1004 * The Spansion S25FL032P and S25FL064P have 256b pages, yet use the
1005 * 0x4d00 Extended JEDEC code. The rest of the Spansion flashes with
1006 * the 0x4d00 Extended JEDEC code have 512b pages. All of the others
1009 if (JEDEC_EXT(info) == 0x4d00) {
1010 if ((JEDEC_ID(info) != 0x0215) &&
1011 (JEDEC_ID(info) != 0x0216))
1012 flash->page_size = 512;
1014 flash->page_size <<= flash->shift;
1015 flash->sector_size = info->sector_size << flash->shift;
1016 flash->size = flash->sector_size * info->n_sectors << flash->shift;
1017 #ifdef CONFIG_SF_DUAL_FLASH
1018 if (flash->dual_flash & SF_DUAL_STACKED_FLASH)
1022 #ifdef CONFIG_SPI_FLASH_USE_4K_SECTORS
1023 /* Compute erase sector and command */
1024 if (info->flags & SECT_4K) {
1025 flash->erase_cmd = CMD_ERASE_4K;
1026 flash->erase_size = 4096 << flash->shift;
1030 flash->erase_cmd = CMD_ERASE_64K;
1031 flash->erase_size = flash->sector_size;
1034 /* Now erase size becomes valid sector size */
1035 flash->sector_size = flash->erase_size;
1037 /* Look for read commands */
1038 flash->read_cmd = CMD_READ_ARRAY_FAST;
1039 if (spi->mode & SPI_RX_SLOW)
1040 flash->read_cmd = CMD_READ_ARRAY_SLOW;
1041 else if (spi->mode & SPI_RX_QUAD && info->flags & RD_QUAD)
1042 flash->read_cmd = CMD_READ_QUAD_OUTPUT_FAST;
1043 else if (spi->mode & SPI_RX_DUAL && info->flags & RD_DUAL)
1044 flash->read_cmd = CMD_READ_DUAL_OUTPUT_FAST;
1046 /* Look for write commands */
1047 if (info->flags & WR_QPP && spi->mode & SPI_TX_QUAD)
1048 flash->write_cmd = CMD_QUAD_PAGE_PROGRAM;
1050 /* Go for default supported write cmd */
1051 flash->write_cmd = CMD_PAGE_PROGRAM;
1053 /* Set the quad enable bit - only for quad commands */
1054 if ((flash->read_cmd == CMD_READ_QUAD_OUTPUT_FAST) ||
1055 (flash->read_cmd == CMD_READ_QUAD_IO_FAST) ||
1056 (flash->write_cmd == CMD_QUAD_PAGE_PROGRAM)) {
1057 ret = set_quad_mode(flash, info);
1059 debug("SF: Fail to set QEB for %02x\n",
1065 /* Read dummy_byte: dummy byte is determined based on the
1066 * dummy cycles of a particular command.
1067 * Fast commands - dummy_byte = dummy_cycles/8
1068 * I/O commands- dummy_byte = (dummy_cycles * no.of lines)/8
1069 * For I/O commands except cmd[0] everything goes on no.of lines
1070 * based on particular command but incase of fast commands except
1071 * data all go on single line irrespective of command.
1073 switch (flash->read_cmd) {
1074 case CMD_READ_QUAD_IO_FAST:
1075 flash->dummy_byte = 2;
1077 case CMD_READ_ARRAY_SLOW:
1078 flash->dummy_byte = 0;
1081 flash->dummy_byte = 1;
1084 #ifdef CONFIG_SPI_FLASH_STMICRO
1085 if (info->flags & E_FSR)
1086 flash->flags |= SNOR_F_USE_FSR;
1089 /* Configure the BAR - discover bank cmds and read current bank */
1090 #ifdef CONFIG_SPI_FLASH_BAR
1091 ret = read_bar(flash, info);
1096 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
1097 ret = spi_flash_decode_fdt(flash);
1099 debug("SF: FDT decode error\n");
1104 #ifndef CONFIG_SPL_BUILD
1105 printf("SF: Detected %s with page size ", flash->name);
1106 print_size(flash->page_size, ", erase size ");
1107 print_size(flash->erase_size, ", total ");
1108 print_size(flash->size, "");
1109 if (flash->memory_map)
1110 printf(", mapped at %p", flash->memory_map);
1114 #ifndef CONFIG_SPI_FLASH_BAR
1115 if (((flash->dual_flash == SF_SINGLE_FLASH) &&
1116 (flash->size > SPI_FLASH_16MB_BOUN)) ||
1117 ((flash->dual_flash > SF_SINGLE_FLASH) &&
1118 (flash->size > SPI_FLASH_16MB_BOUN << 1))) {
1119 puts("SF: Warning - Only lower 16MiB accessible,");
1120 puts(" Full access #define CONFIG_SPI_FLASH_BAR\n");