1 // SPDX-License-Identifier: GPL-2.0
3 * Based on m25p80.c, by Mike Lavender (mike@steroidmicros.com), with
4 * influence from lart.c (Abraham Van Der Merwe) and mtd_dataflash.c
6 * Copyright (C) 2005, Intec Automation Inc.
7 * Copyright (C) 2014, Freescale Semiconductor, Inc.
9 * Synced from Linux v4.19
13 #include <dm/device_compat.h>
14 #include <linux/err.h>
15 #include <linux/errno.h>
16 #include <linux/log2.h>
17 #include <linux/math64.h>
18 #include <linux/sizes.h>
20 #include <linux/mtd/mtd.h>
21 #include <linux/mtd/spi-nor.h>
25 #include "sf_internal.h"
27 /* Define max times to check status register before we give up. */
30 * For everything but full-chip erase; probably could be much smaller, but kept
31 * around for safety for now
34 #define HZ CONFIG_SYS_HZ
36 #define DEFAULT_READY_WAIT_JIFFIES (40UL * HZ)
38 static int spi_nor_read_write_reg(struct spi_nor *nor, struct spi_mem_op
41 if (op->data.dir == SPI_MEM_DATA_IN)
42 op->data.buf.in = buf;
44 op->data.buf.out = buf;
45 return spi_mem_exec_op(nor->spi, op);
48 static int spi_nor_read_reg(struct spi_nor *nor, u8 code, u8 *val, int len)
50 struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(code, 1),
53 SPI_MEM_OP_DATA_IN(len, NULL, 1));
56 ret = spi_nor_read_write_reg(nor, &op, val);
58 dev_dbg(&flash->spimem->spi->dev, "error %d reading %x\n", ret,
64 static int spi_nor_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
66 struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(opcode, 1),
69 SPI_MEM_OP_DATA_OUT(len, NULL, 1));
71 return spi_nor_read_write_reg(nor, &op, buf);
74 static ssize_t spi_nor_read_data(struct spi_nor *nor, loff_t from, size_t len,
77 struct spi_mem_op op =
78 SPI_MEM_OP(SPI_MEM_OP_CMD(nor->read_opcode, 1),
79 SPI_MEM_OP_ADDR(nor->addr_width, from, 1),
80 SPI_MEM_OP_DUMMY(nor->read_dummy, 1),
81 SPI_MEM_OP_DATA_IN(len, buf, 1));
82 size_t remaining = len;
85 /* get transfer protocols. */
86 op.cmd.buswidth = spi_nor_get_protocol_inst_nbits(nor->read_proto);
87 op.addr.buswidth = spi_nor_get_protocol_addr_nbits(nor->read_proto);
88 op.dummy.buswidth = op.addr.buswidth;
89 op.data.buswidth = spi_nor_get_protocol_data_nbits(nor->read_proto);
91 /* convert the dummy cycles to the number of bytes */
92 op.dummy.nbytes = (nor->read_dummy * op.dummy.buswidth) / 8;
95 op.data.nbytes = remaining < UINT_MAX ? remaining : UINT_MAX;
96 ret = spi_mem_adjust_op_size(nor->spi, &op);
100 ret = spi_mem_exec_op(nor->spi, &op);
104 op.addr.val += op.data.nbytes;
105 remaining -= op.data.nbytes;
106 op.data.buf.in += op.data.nbytes;
112 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
114 * Read configuration register, returning its value in the
115 * location. Return the configuration register value.
116 * Returns negative if error occurred.
118 static int read_cr(struct spi_nor *nor)
123 ret = spi_nor_read_reg(nor, SPINOR_OP_RDCR, &val, 1);
125 dev_dbg(nor->dev, "error %d reading CR\n", ret);
134 * Write status register 1 byte
135 * Returns negative if error occurred.
137 static inline int write_sr(struct spi_nor *nor, u8 val)
139 nor->cmd_buf[0] = val;
140 return spi_nor_write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1);
144 * Set write enable latch with Write Enable command.
145 * Returns negative if error occurred.
147 static inline int write_enable(struct spi_nor *nor)
149 return spi_nor_write_reg(nor, SPINOR_OP_WREN, NULL, 0);
153 * Send write disable instruction to the chip.
155 static inline int write_disable(struct spi_nor *nor)
157 return spi_nor_write_reg(nor, SPINOR_OP_WRDI, NULL, 0);
160 static inline struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd)
165 static u8 spi_nor_convert_opcode(u8 opcode, const u8 table[][2], size_t size)
169 for (i = 0; i < size; i++)
170 if (table[i][0] == opcode)
173 /* No conversion found, keep input op code. */
177 static inline u8 spi_nor_convert_3to4_read(u8 opcode)
179 static const u8 spi_nor_3to4_read[][2] = {
180 { SPINOR_OP_READ, SPINOR_OP_READ_4B },
181 { SPINOR_OP_READ_FAST, SPINOR_OP_READ_FAST_4B },
182 { SPINOR_OP_READ_1_1_2, SPINOR_OP_READ_1_1_2_4B },
183 { SPINOR_OP_READ_1_2_2, SPINOR_OP_READ_1_2_2_4B },
184 { SPINOR_OP_READ_1_1_4, SPINOR_OP_READ_1_1_4_4B },
185 { SPINOR_OP_READ_1_4_4, SPINOR_OP_READ_1_4_4_4B },
188 return spi_nor_convert_opcode(opcode, spi_nor_3to4_read,
189 ARRAY_SIZE(spi_nor_3to4_read));
192 static void spi_nor_set_4byte_opcodes(struct spi_nor *nor,
193 const struct flash_info *info)
195 nor->read_opcode = spi_nor_convert_3to4_read(nor->read_opcode);
198 /* Enable/disable 4-byte addressing mode. */
199 static inline int set_4byte(struct spi_nor *nor, const struct flash_info *info,
203 bool need_wren = false;
206 switch (JEDEC_MFR(info)) {
208 case SNOR_MFR_MICRON:
209 /* Some Micron need WREN command; all will accept it */
211 case SNOR_MFR_MACRONIX:
212 case SNOR_MFR_WINBOND:
216 cmd = enable ? SPINOR_OP_EN4B : SPINOR_OP_EX4B;
217 status = spi_nor_write_reg(nor, cmd, NULL, 0);
221 if (!status && !enable &&
222 JEDEC_MFR(info) == SNOR_MFR_WINBOND) {
224 * On Winbond W25Q256FV, leaving 4byte mode causes
225 * the Extended Address Register to be set to 1, so all
226 * 3-byte-address reads come from the second 16M.
227 * We must clear the register to enable normal behavior.
231 spi_nor_write_reg(nor, SPINOR_OP_WREAR,
239 nor->cmd_buf[0] = enable << 7;
240 return spi_nor_write_reg(nor, SPINOR_OP_BRWR, nor->cmd_buf, 1);
244 #if defined(CONFIG_SPI_FLASH_SPANSION) || \
245 defined(CONFIG_SPI_FLASH_WINBOND) || \
246 defined(CONFIG_SPI_FLASH_MACRONIX)
248 * Read the status register, returning its value in the location
249 * Return the status register value.
250 * Returns negative if error occurred.
252 static int read_sr(struct spi_nor *nor)
257 ret = spi_nor_read_reg(nor, SPINOR_OP_RDSR, &val, 1);
259 pr_debug("error %d reading SR\n", (int)ret);
267 * Read the flag status register, returning its value in the location
268 * Return the status register value.
269 * Returns negative if error occurred.
271 static int read_fsr(struct spi_nor *nor)
276 ret = spi_nor_read_reg(nor, SPINOR_OP_RDFSR, &val, 1);
278 pr_debug("error %d reading FSR\n", ret);
285 static int spi_nor_sr_ready(struct spi_nor *nor)
287 int sr = read_sr(nor);
292 return !(sr & SR_WIP);
295 static int spi_nor_fsr_ready(struct spi_nor *nor)
297 int fsr = read_fsr(nor);
301 return fsr & FSR_READY;
304 static int spi_nor_ready(struct spi_nor *nor)
308 sr = spi_nor_sr_ready(nor);
311 fsr = nor->flags & SNOR_F_USE_FSR ? spi_nor_fsr_ready(nor) : 1;
318 * Service routine to read status register until ready, or timeout occurs.
319 * Returns non-zero if error.
321 static int spi_nor_wait_till_ready_with_timeout(struct spi_nor *nor,
322 unsigned long timeout)
324 unsigned long timebase;
327 timebase = get_timer(0);
329 while (get_timer(timebase) < timeout) {
330 ret = spi_nor_ready(nor);
337 dev_err(nor->dev, "flash operation timed out\n");
342 static int spi_nor_wait_till_ready(struct spi_nor *nor)
344 return spi_nor_wait_till_ready_with_timeout(nor,
345 DEFAULT_READY_WAIT_JIFFIES);
347 #endif /* CONFIG_SPI_FLASH_SPANSION */
350 * Erase an address range on the nor chip. The address range may extend
351 * one or more erase sectors. Return an error is there is a problem erasing.
353 static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
358 static const struct flash_info *spi_nor_read_id(struct spi_nor *nor)
361 u8 id[SPI_NOR_MAX_ID_LEN];
362 const struct flash_info *info;
364 tmp = spi_nor_read_reg(nor, SPINOR_OP_RDID, id, SPI_NOR_MAX_ID_LEN);
366 dev_dbg(nor->dev, "error %d reading JEDEC ID\n", tmp);
371 for (; info->sector_size != 0; info++) {
373 if (!memcmp(info->id, id, info->id_len))
377 dev_dbg(nor->dev, "unrecognized JEDEC id bytes: %02x, %02x, %02x\n",
378 id[0], id[1], id[2]);
379 return ERR_PTR(-ENODEV);
382 static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len,
383 size_t *retlen, u_char *buf)
385 struct spi_nor *nor = mtd_to_spi_nor(mtd);
388 dev_dbg(nor->dev, "from 0x%08x, len %zd\n", (u32)from, len);
393 ret = spi_nor_read_data(nor, addr, len, buf);
395 /* We shouldn't see 0-length reads */
414 * Write an address range to the nor chip. Data must be written in
415 * FLASH_PAGESIZE chunks. The address range may be any size provided
416 * it is within the physical boundaries.
418 static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len,
419 size_t *retlen, const u_char *buf)
424 #ifdef CONFIG_SPI_FLASH_MACRONIX
426 * macronix_quad_enable() - set QE bit in Status Register.
427 * @nor: pointer to a 'struct spi_nor'
429 * Set the Quad Enable (QE) bit in the Status Register.
431 * bit 6 of the Status Register is the QE bit for Macronix like QSPI memories.
433 * Return: 0 on success, -errno otherwise.
435 static int macronix_quad_enable(struct spi_nor *nor)
442 if (val & SR_QUAD_EN_MX)
447 write_sr(nor, val | SR_QUAD_EN_MX);
449 ret = spi_nor_wait_till_ready(nor);
454 if (!(ret > 0 && (ret & SR_QUAD_EN_MX))) {
455 dev_err(nor->dev, "Macronix Quad bit not set\n");
463 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
465 * Write status Register and configuration register with 2 bytes
466 * The first byte will be written to the status register, while the
467 * second byte will be written to the configuration register.
468 * Return negative if error occurred.
470 static int write_sr_cr(struct spi_nor *nor, u8 *sr_cr)
476 ret = spi_nor_write_reg(nor, SPINOR_OP_WRSR, sr_cr, 2);
479 "error while writing configuration register\n");
483 ret = spi_nor_wait_till_ready(nor);
486 "timeout while writing configuration register\n");
494 * spansion_read_cr_quad_enable() - set QE bit in Configuration Register.
495 * @nor: pointer to a 'struct spi_nor'
497 * Set the Quad Enable (QE) bit in the Configuration Register.
498 * This function should be used with QSPI memories supporting the Read
499 * Configuration Register (35h) instruction.
501 * bit 1 of the Configuration Register is the QE bit for Spansion like QSPI
504 * Return: 0 on success, -errno otherwise.
506 static int spansion_read_cr_quad_enable(struct spi_nor *nor)
511 /* Check current Quad Enable bit value. */
514 dev_dbg(dev, "error while reading configuration register\n");
518 if (ret & CR_QUAD_EN_SPAN)
521 sr_cr[1] = ret | CR_QUAD_EN_SPAN;
523 /* Keep the current value of the Status Register. */
526 dev_dbg(dev, "error while reading status register\n");
531 ret = write_sr_cr(nor, sr_cr);
535 /* Read back and check it. */
537 if (!(ret > 0 && (ret & CR_QUAD_EN_SPAN))) {
538 dev_dbg(nor->dev, "Spansion Quad bit not set\n");
544 #endif /* CONFIG_SPI_FLASH_SPANSION */
546 struct spi_nor_read_command {
550 enum spi_nor_protocol proto;
553 enum spi_nor_read_command_index {
563 struct spi_nor_flash_parameter {
564 struct spi_nor_hwcaps hwcaps;
565 struct spi_nor_read_command reads[SNOR_CMD_READ_MAX];
569 spi_nor_set_read_settings(struct spi_nor_read_command *read,
573 enum spi_nor_protocol proto)
575 read->num_mode_clocks = num_mode_clocks;
576 read->num_wait_states = num_wait_states;
577 read->opcode = opcode;
581 static int spi_nor_init_params(struct spi_nor *nor,
582 const struct flash_info *info,
583 struct spi_nor_flash_parameter *params)
585 /* (Fast) Read settings. */
586 params->hwcaps.mask = SNOR_HWCAPS_READ;
587 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ],
588 0, 0, SPINOR_OP_READ,
591 if (!(info->flags & SPI_NOR_NO_FR)) {
592 params->hwcaps.mask |= SNOR_HWCAPS_READ_FAST;
593 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_FAST],
594 0, 8, SPINOR_OP_READ_FAST,
598 if (info->flags & SPI_NOR_QUAD_READ) {
599 params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4;
600 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_4],
601 0, 8, SPINOR_OP_READ_1_1_4,
608 static int spi_nor_select_read(struct spi_nor *nor,
609 const struct spi_nor_flash_parameter *params,
612 int best_match = shared_hwcaps & SNOR_HWCAPS_READ_MASK;
614 const struct spi_nor_read_command *read;
619 if (best_match & SNOR_HWCAPS_READ_1_1_4)
620 cmd = SNOR_CMD_READ_1_1_4;
621 else if (best_match & SNOR_HWCAPS_READ_FAST)
622 cmd = SNOR_CMD_READ_FAST;
626 read = ¶ms->reads[cmd];
627 nor->read_opcode = read->opcode;
628 nor->read_proto = read->proto;
631 * In the spi-nor framework, we don't need to make the difference
632 * between mode clock cycles and wait state clock cycles.
633 * Indeed, the value of the mode clock cycles is used by a QSPI
634 * flash memory to know whether it should enter or leave its 0-4-4
635 * (Continuous Read / XIP) mode.
636 * eXecution In Place is out of the scope of the mtd sub-system.
637 * Hence we choose to merge both mode and wait state clock cycles
638 * into the so called dummy clock cycles.
640 nor->read_dummy = read->num_mode_clocks + read->num_wait_states;
644 static int spi_nor_setup(struct spi_nor *nor, const struct flash_info *info,
645 const struct spi_nor_flash_parameter *params,
646 const struct spi_nor_hwcaps *hwcaps)
652 * Keep only the hardware capabilities supported by both the SPI
653 * controller and the SPI flash memory.
655 shared_mask = hwcaps->mask & params->hwcaps.mask;
657 /* Select the (Fast) Read command. */
658 err = spi_nor_select_read(nor, params, shared_mask);
661 "can't select read settings supported by both the SPI controller and memory.\n");
665 /* Enable Quad I/O if needed. */
666 if (spi_nor_get_protocol_width(nor->read_proto) == 4) {
667 switch (JEDEC_MFR(info)) {
668 #ifdef CONFIG_SPI_FLASH_MACRONIX
669 case SNOR_MFR_MACRONIX:
670 err = macronix_quad_enable(nor);
674 case SNOR_MFR_MICRON:
678 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
679 /* Kept only for backward compatibility purpose. */
680 err = spansion_read_cr_quad_enable(nor);
686 dev_dbg(nor->dev, "quad mode not supported\n");
693 static int spi_nor_init(struct spi_nor *nor)
695 if (nor->addr_width == 4 &&
696 (JEDEC_MFR(nor->info) != SNOR_MFR_SPANSION) &&
697 !(nor->info->flags & SPI_NOR_4B_OPCODES)) {
699 * If the RESET# pin isn't hooked up properly, or the system
700 * otherwise doesn't perform a reset command in the boot
701 * sequence, it's impossible to 100% protect against unexpected
702 * reboots (e.g., crashes). Warn the user (or hopefully, system
703 * designer) that this is bad.
705 if (nor->flags & SNOR_F_BROKEN_RESET)
706 printf("enabling reset hack; may not recover from unexpected reboots\n");
707 set_4byte(nor, nor->info, 1);
713 int spi_nor_scan(struct spi_nor *nor)
715 struct spi_nor_flash_parameter params;
716 const struct flash_info *info = NULL;
717 struct mtd_info *mtd = &nor->mtd;
718 struct spi_nor_hwcaps hwcaps = {
719 .mask = SNOR_HWCAPS_READ |
720 SNOR_HWCAPS_READ_FAST
722 struct spi_slave *spi = nor->spi;
725 /* Reset SPI protocol for all commands. */
726 nor->reg_proto = SNOR_PROTO_1_1_1;
727 nor->read_proto = SNOR_PROTO_1_1_1;
728 nor->write_proto = SNOR_PROTO_1_1_1;
730 if (spi->mode & SPI_RX_QUAD)
731 hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4;
733 info = spi_nor_read_id(nor);
734 if (IS_ERR_OR_NULL(info))
736 /* Parse the Serial Flash Discoverable Parameters table. */
737 ret = spi_nor_init_params(nor, info, ¶ms);
741 mtd->name = "spi-flash";
743 mtd->type = MTD_NORFLASH;
745 mtd->flags = MTD_CAP_NORFLASH;
746 mtd->size = info->sector_size * info->n_sectors;
747 mtd->_erase = spi_nor_erase;
748 mtd->_read = spi_nor_read;
749 mtd->_write = spi_nor_write;
751 nor->size = mtd->size;
753 if (info->flags & USE_FSR)
754 nor->flags |= SNOR_F_USE_FSR;
755 if (info->flags & USE_CLSR)
756 nor->flags |= SNOR_F_USE_CLSR;
758 if (info->flags & SPI_NOR_NO_FR)
759 params.hwcaps.mask &= ~SNOR_HWCAPS_READ_FAST;
762 * Configure the SPI memory:
763 * - select op codes for (Fast) Read, Page Program and Sector Erase.
764 * - set the number of dummy cycles (mode cycles + wait states).
765 * - set the SPI protocols for register and memory accesses.
766 * - set the Quad Enable bit if needed (required by SPI x-y-4 protos).
768 ret = spi_nor_setup(nor, info, ¶ms, &hwcaps);
772 if (nor->addr_width) {
773 /* already configured from SFDP */
774 } else if (info->addr_width) {
775 nor->addr_width = info->addr_width;
776 } else if (mtd->size > 0x1000000) {
777 /* enable 4-byte addressing if the device exceeds 16MiB */
779 if (JEDEC_MFR(info) == SNOR_MFR_SPANSION ||
780 info->flags & SPI_NOR_4B_OPCODES)
781 spi_nor_set_4byte_opcodes(nor, info);
786 if (nor->addr_width > SPI_NOR_MAX_ADDR_WIDTH) {
787 dev_dbg(dev, "address width is too large: %u\n",
792 /* Send all the required SPI flash commands to initialize device */
794 ret = spi_nor_init(nor);
801 /* U-Boot specific functions, need to extend MTD to support these */
802 int spi_flash_cmd_get_sw_write_prot(struct spi_nor *nor)