1 // SPDX-License-Identifier: GPL-2.0
3 * Based on m25p80.c, by Mike Lavender (mike@steroidmicros.com), with
4 * influence from lart.c (Abraham Van Der Merwe) and mtd_dataflash.c
6 * Copyright (C) 2005, Intec Automation Inc.
7 * Copyright (C) 2014, Freescale Semiconductor, Inc.
9 * Synced from Linux v4.19
13 #include <linux/err.h>
14 #include <linux/errno.h>
15 #include <linux/log2.h>
16 #include <linux/math64.h>
17 #include <linux/sizes.h>
19 #include <linux/mtd/mtd.h>
20 #include <linux/mtd/spi-nor.h>
24 #include "sf_internal.h"
26 /* Define max times to check status register before we give up. */
29 * For everything but full-chip erase; probably could be much smaller, but kept
30 * around for safety for now
33 #define HZ CONFIG_SYS_HZ
35 #define DEFAULT_READY_WAIT_JIFFIES (40UL * HZ)
37 static int spi_nor_read_write_reg(struct spi_nor *nor, struct spi_mem_op
40 if (op->data.dir == SPI_MEM_DATA_IN)
41 op->data.buf.in = buf;
43 op->data.buf.out = buf;
44 return spi_mem_exec_op(nor->spi, op);
47 static int spi_nor_read_reg(struct spi_nor *nor, u8 code, u8 *val, int len)
49 struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(code, 1),
52 SPI_MEM_OP_DATA_IN(len, NULL, 1));
55 ret = spi_nor_read_write_reg(nor, &op, val);
57 dev_dbg(&flash->spimem->spi->dev, "error %d reading %x\n", ret,
63 static int spi_nor_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
65 struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(opcode, 1),
68 SPI_MEM_OP_DATA_OUT(len, NULL, 1));
70 return spi_nor_read_write_reg(nor, &op, buf);
73 static ssize_t spi_nor_read_data(struct spi_nor *nor, loff_t from, size_t len,
76 struct spi_mem_op op =
77 SPI_MEM_OP(SPI_MEM_OP_CMD(nor->read_opcode, 1),
78 SPI_MEM_OP_ADDR(nor->addr_width, from, 1),
79 SPI_MEM_OP_DUMMY(nor->read_dummy, 1),
80 SPI_MEM_OP_DATA_IN(len, buf, 1));
81 size_t remaining = len;
84 /* get transfer protocols. */
85 op.cmd.buswidth = spi_nor_get_protocol_inst_nbits(nor->read_proto);
86 op.addr.buswidth = spi_nor_get_protocol_addr_nbits(nor->read_proto);
87 op.dummy.buswidth = op.addr.buswidth;
88 op.data.buswidth = spi_nor_get_protocol_data_nbits(nor->read_proto);
90 /* convert the dummy cycles to the number of bytes */
91 op.dummy.nbytes = (nor->read_dummy * op.dummy.buswidth) / 8;
94 op.data.nbytes = remaining < UINT_MAX ? remaining : UINT_MAX;
95 ret = spi_mem_adjust_op_size(nor->spi, &op);
99 ret = spi_mem_exec_op(nor->spi, &op);
103 op.addr.val += op.data.nbytes;
104 remaining -= op.data.nbytes;
105 op.data.buf.in += op.data.nbytes;
111 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
113 * Read configuration register, returning its value in the
114 * location. Return the configuration register value.
115 * Returns negative if error occurred.
117 static int read_cr(struct spi_nor *nor)
122 ret = spi_nor_read_reg(nor, SPINOR_OP_RDCR, &val, 1);
124 dev_dbg(nor->dev, "error %d reading CR\n", ret);
133 * Write status register 1 byte
134 * Returns negative if error occurred.
136 static inline int write_sr(struct spi_nor *nor, u8 val)
138 nor->cmd_buf[0] = val;
139 return spi_nor_write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1);
143 * Set write enable latch with Write Enable command.
144 * Returns negative if error occurred.
146 static inline int write_enable(struct spi_nor *nor)
148 return spi_nor_write_reg(nor, SPINOR_OP_WREN, NULL, 0);
152 * Send write disable instruction to the chip.
154 static inline int write_disable(struct spi_nor *nor)
156 return spi_nor_write_reg(nor, SPINOR_OP_WRDI, NULL, 0);
159 static inline struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd)
164 static u8 spi_nor_convert_opcode(u8 opcode, const u8 table[][2], size_t size)
168 for (i = 0; i < size; i++)
169 if (table[i][0] == opcode)
172 /* No conversion found, keep input op code. */
176 static inline u8 spi_nor_convert_3to4_read(u8 opcode)
178 static const u8 spi_nor_3to4_read[][2] = {
179 { SPINOR_OP_READ, SPINOR_OP_READ_4B },
180 { SPINOR_OP_READ_FAST, SPINOR_OP_READ_FAST_4B },
181 { SPINOR_OP_READ_1_1_2, SPINOR_OP_READ_1_1_2_4B },
182 { SPINOR_OP_READ_1_2_2, SPINOR_OP_READ_1_2_2_4B },
183 { SPINOR_OP_READ_1_1_4, SPINOR_OP_READ_1_1_4_4B },
184 { SPINOR_OP_READ_1_4_4, SPINOR_OP_READ_1_4_4_4B },
187 return spi_nor_convert_opcode(opcode, spi_nor_3to4_read,
188 ARRAY_SIZE(spi_nor_3to4_read));
191 static void spi_nor_set_4byte_opcodes(struct spi_nor *nor,
192 const struct flash_info *info)
194 nor->read_opcode = spi_nor_convert_3to4_read(nor->read_opcode);
197 /* Enable/disable 4-byte addressing mode. */
198 static inline int set_4byte(struct spi_nor *nor, const struct flash_info *info,
202 bool need_wren = false;
205 switch (JEDEC_MFR(info)) {
207 case SNOR_MFR_MICRON:
208 /* Some Micron need WREN command; all will accept it */
210 case SNOR_MFR_MACRONIX:
211 case SNOR_MFR_WINBOND:
215 cmd = enable ? SPINOR_OP_EN4B : SPINOR_OP_EX4B;
216 status = spi_nor_write_reg(nor, cmd, NULL, 0);
220 if (!status && !enable &&
221 JEDEC_MFR(info) == SNOR_MFR_WINBOND) {
223 * On Winbond W25Q256FV, leaving 4byte mode causes
224 * the Extended Address Register to be set to 1, so all
225 * 3-byte-address reads come from the second 16M.
226 * We must clear the register to enable normal behavior.
230 spi_nor_write_reg(nor, SPINOR_OP_WREAR,
238 nor->cmd_buf[0] = enable << 7;
239 return spi_nor_write_reg(nor, SPINOR_OP_BRWR, nor->cmd_buf, 1);
243 #if defined(CONFIG_SPI_FLASH_SPANSION) || \
244 defined(CONFIG_SPI_FLASH_WINBOND) || \
245 defined(CONFIG_SPI_FLASH_MACRONIX)
247 * Read the status register, returning its value in the location
248 * Return the status register value.
249 * Returns negative if error occurred.
251 static int read_sr(struct spi_nor *nor)
256 ret = spi_nor_read_reg(nor, SPINOR_OP_RDSR, &val, 1);
258 pr_debug("error %d reading SR\n", (int)ret);
266 * Read the flag status register, returning its value in the location
267 * Return the status register value.
268 * Returns negative if error occurred.
270 static int read_fsr(struct spi_nor *nor)
275 ret = spi_nor_read_reg(nor, SPINOR_OP_RDFSR, &val, 1);
277 pr_debug("error %d reading FSR\n", ret);
284 static int spi_nor_sr_ready(struct spi_nor *nor)
286 int sr = read_sr(nor);
291 return !(sr & SR_WIP);
294 static int spi_nor_fsr_ready(struct spi_nor *nor)
296 int fsr = read_fsr(nor);
300 return fsr & FSR_READY;
303 static int spi_nor_ready(struct spi_nor *nor)
307 sr = spi_nor_sr_ready(nor);
310 fsr = nor->flags & SNOR_F_USE_FSR ? spi_nor_fsr_ready(nor) : 1;
317 * Service routine to read status register until ready, or timeout occurs.
318 * Returns non-zero if error.
320 static int spi_nor_wait_till_ready_with_timeout(struct spi_nor *nor,
321 unsigned long timeout)
323 unsigned long timebase;
326 timebase = get_timer(0);
328 while (get_timer(timebase) < timeout) {
329 ret = spi_nor_ready(nor);
336 dev_err(nor->dev, "flash operation timed out\n");
341 static int spi_nor_wait_till_ready(struct spi_nor *nor)
343 return spi_nor_wait_till_ready_with_timeout(nor,
344 DEFAULT_READY_WAIT_JIFFIES);
346 #endif /* CONFIG_SPI_FLASH_SPANSION */
349 * Erase an address range on the nor chip. The address range may extend
350 * one or more erase sectors. Return an error is there is a problem erasing.
352 static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
357 static const struct flash_info *spi_nor_read_id(struct spi_nor *nor)
360 u8 id[SPI_NOR_MAX_ID_LEN];
361 const struct flash_info *info;
363 tmp = spi_nor_read_reg(nor, SPINOR_OP_RDID, id, SPI_NOR_MAX_ID_LEN);
365 dev_dbg(nor->dev, "error %d reading JEDEC ID\n", tmp);
370 for (; info->sector_size != 0; info++) {
372 if (!memcmp(info->id, id, info->id_len))
376 dev_dbg(nor->dev, "unrecognized JEDEC id bytes: %02x, %02x, %02x\n",
377 id[0], id[1], id[2]);
378 return ERR_PTR(-ENODEV);
381 static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len,
382 size_t *retlen, u_char *buf)
384 struct spi_nor *nor = mtd_to_spi_nor(mtd);
387 dev_dbg(nor->dev, "from 0x%08x, len %zd\n", (u32)from, len);
392 ret = spi_nor_read_data(nor, addr, len, buf);
394 /* We shouldn't see 0-length reads */
413 * Write an address range to the nor chip. Data must be written in
414 * FLASH_PAGESIZE chunks. The address range may be any size provided
415 * it is within the physical boundaries.
417 static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len,
418 size_t *retlen, const u_char *buf)
423 #ifdef CONFIG_SPI_FLASH_MACRONIX
425 * macronix_quad_enable() - set QE bit in Status Register.
426 * @nor: pointer to a 'struct spi_nor'
428 * Set the Quad Enable (QE) bit in the Status Register.
430 * bit 6 of the Status Register is the QE bit for Macronix like QSPI memories.
432 * Return: 0 on success, -errno otherwise.
434 static int macronix_quad_enable(struct spi_nor *nor)
441 if (val & SR_QUAD_EN_MX)
446 write_sr(nor, val | SR_QUAD_EN_MX);
448 ret = spi_nor_wait_till_ready(nor);
453 if (!(ret > 0 && (ret & SR_QUAD_EN_MX))) {
454 dev_err(nor->dev, "Macronix Quad bit not set\n");
462 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
464 * Write status Register and configuration register with 2 bytes
465 * The first byte will be written to the status register, while the
466 * second byte will be written to the configuration register.
467 * Return negative if error occurred.
469 static int write_sr_cr(struct spi_nor *nor, u8 *sr_cr)
475 ret = spi_nor_write_reg(nor, SPINOR_OP_WRSR, sr_cr, 2);
478 "error while writing configuration register\n");
482 ret = spi_nor_wait_till_ready(nor);
485 "timeout while writing configuration register\n");
493 * spansion_read_cr_quad_enable() - set QE bit in Configuration Register.
494 * @nor: pointer to a 'struct spi_nor'
496 * Set the Quad Enable (QE) bit in the Configuration Register.
497 * This function should be used with QSPI memories supporting the Read
498 * Configuration Register (35h) instruction.
500 * bit 1 of the Configuration Register is the QE bit for Spansion like QSPI
503 * Return: 0 on success, -errno otherwise.
505 static int spansion_read_cr_quad_enable(struct spi_nor *nor)
510 /* Check current Quad Enable bit value. */
513 dev_dbg(dev, "error while reading configuration register\n");
517 if (ret & CR_QUAD_EN_SPAN)
520 sr_cr[1] = ret | CR_QUAD_EN_SPAN;
522 /* Keep the current value of the Status Register. */
525 dev_dbg(dev, "error while reading status register\n");
530 ret = write_sr_cr(nor, sr_cr);
534 /* Read back and check it. */
536 if (!(ret > 0 && (ret & CR_QUAD_EN_SPAN))) {
537 dev_dbg(nor->dev, "Spansion Quad bit not set\n");
543 #endif /* CONFIG_SPI_FLASH_SPANSION */
545 struct spi_nor_read_command {
549 enum spi_nor_protocol proto;
552 enum spi_nor_read_command_index {
562 struct spi_nor_flash_parameter {
563 struct spi_nor_hwcaps hwcaps;
564 struct spi_nor_read_command reads[SNOR_CMD_READ_MAX];
568 spi_nor_set_read_settings(struct spi_nor_read_command *read,
572 enum spi_nor_protocol proto)
574 read->num_mode_clocks = num_mode_clocks;
575 read->num_wait_states = num_wait_states;
576 read->opcode = opcode;
580 static int spi_nor_init_params(struct spi_nor *nor,
581 const struct flash_info *info,
582 struct spi_nor_flash_parameter *params)
584 /* (Fast) Read settings. */
585 params->hwcaps.mask = SNOR_HWCAPS_READ;
586 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ],
587 0, 0, SPINOR_OP_READ,
590 if (!(info->flags & SPI_NOR_NO_FR)) {
591 params->hwcaps.mask |= SNOR_HWCAPS_READ_FAST;
592 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_FAST],
593 0, 8, SPINOR_OP_READ_FAST,
597 if (info->flags & SPI_NOR_QUAD_READ) {
598 params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4;
599 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_4],
600 0, 8, SPINOR_OP_READ_1_1_4,
607 static int spi_nor_select_read(struct spi_nor *nor,
608 const struct spi_nor_flash_parameter *params,
611 int best_match = shared_hwcaps & SNOR_HWCAPS_READ_MASK;
613 const struct spi_nor_read_command *read;
618 if (best_match & SNOR_HWCAPS_READ_1_1_4)
619 cmd = SNOR_CMD_READ_1_1_4;
620 else if (best_match & SNOR_HWCAPS_READ_FAST)
621 cmd = SNOR_CMD_READ_FAST;
625 read = ¶ms->reads[cmd];
626 nor->read_opcode = read->opcode;
627 nor->read_proto = read->proto;
630 * In the spi-nor framework, we don't need to make the difference
631 * between mode clock cycles and wait state clock cycles.
632 * Indeed, the value of the mode clock cycles is used by a QSPI
633 * flash memory to know whether it should enter or leave its 0-4-4
634 * (Continuous Read / XIP) mode.
635 * eXecution In Place is out of the scope of the mtd sub-system.
636 * Hence we choose to merge both mode and wait state clock cycles
637 * into the so called dummy clock cycles.
639 nor->read_dummy = read->num_mode_clocks + read->num_wait_states;
643 static int spi_nor_setup(struct spi_nor *nor, const struct flash_info *info,
644 const struct spi_nor_flash_parameter *params,
645 const struct spi_nor_hwcaps *hwcaps)
651 * Keep only the hardware capabilities supported by both the SPI
652 * controller and the SPI flash memory.
654 shared_mask = hwcaps->mask & params->hwcaps.mask;
656 /* Select the (Fast) Read command. */
657 err = spi_nor_select_read(nor, params, shared_mask);
660 "can't select read settings supported by both the SPI controller and memory.\n");
664 /* Enable Quad I/O if needed. */
665 if (spi_nor_get_protocol_width(nor->read_proto) == 4) {
666 switch (JEDEC_MFR(info)) {
667 #ifdef CONFIG_SPI_FLASH_MACRONIX
668 case SNOR_MFR_MACRONIX:
669 err = macronix_quad_enable(nor);
673 case SNOR_MFR_MICRON:
677 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
678 /* Kept only for backward compatibility purpose. */
679 err = spansion_read_cr_quad_enable(nor);
685 dev_dbg(nor->dev, "quad mode not supported\n");
692 static int spi_nor_init(struct spi_nor *nor)
694 if (nor->addr_width == 4 &&
695 (JEDEC_MFR(nor->info) != SNOR_MFR_SPANSION) &&
696 !(nor->info->flags & SPI_NOR_4B_OPCODES)) {
698 * If the RESET# pin isn't hooked up properly, or the system
699 * otherwise doesn't perform a reset command in the boot
700 * sequence, it's impossible to 100% protect against unexpected
701 * reboots (e.g., crashes). Warn the user (or hopefully, system
702 * designer) that this is bad.
704 if (nor->flags & SNOR_F_BROKEN_RESET)
705 printf("enabling reset hack; may not recover from unexpected reboots\n");
706 set_4byte(nor, nor->info, 1);
712 int spi_nor_scan(struct spi_nor *nor)
714 struct spi_nor_flash_parameter params;
715 const struct flash_info *info = NULL;
716 struct mtd_info *mtd = &nor->mtd;
717 struct spi_nor_hwcaps hwcaps = {
718 .mask = SNOR_HWCAPS_READ |
719 SNOR_HWCAPS_READ_FAST
721 struct spi_slave *spi = nor->spi;
724 /* Reset SPI protocol for all commands. */
725 nor->reg_proto = SNOR_PROTO_1_1_1;
726 nor->read_proto = SNOR_PROTO_1_1_1;
727 nor->write_proto = SNOR_PROTO_1_1_1;
729 if (spi->mode & SPI_RX_QUAD)
730 hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4;
732 info = spi_nor_read_id(nor);
733 if (IS_ERR_OR_NULL(info))
735 /* Parse the Serial Flash Discoverable Parameters table. */
736 ret = spi_nor_init_params(nor, info, ¶ms);
740 mtd->name = "spi-flash";
742 mtd->type = MTD_NORFLASH;
744 mtd->flags = MTD_CAP_NORFLASH;
745 mtd->size = info->sector_size * info->n_sectors;
746 mtd->_erase = spi_nor_erase;
747 mtd->_read = spi_nor_read;
748 mtd->_write = spi_nor_write;
750 nor->size = mtd->size;
752 if (info->flags & USE_FSR)
753 nor->flags |= SNOR_F_USE_FSR;
754 if (info->flags & USE_CLSR)
755 nor->flags |= SNOR_F_USE_CLSR;
757 if (info->flags & SPI_NOR_NO_FR)
758 params.hwcaps.mask &= ~SNOR_HWCAPS_READ_FAST;
761 * Configure the SPI memory:
762 * - select op codes for (Fast) Read, Page Program and Sector Erase.
763 * - set the number of dummy cycles (mode cycles + wait states).
764 * - set the SPI protocols for register and memory accesses.
765 * - set the Quad Enable bit if needed (required by SPI x-y-4 protos).
767 ret = spi_nor_setup(nor, info, ¶ms, &hwcaps);
771 if (nor->addr_width) {
772 /* already configured from SFDP */
773 } else if (info->addr_width) {
774 nor->addr_width = info->addr_width;
775 } else if (mtd->size > 0x1000000) {
776 /* enable 4-byte addressing if the device exceeds 16MiB */
778 if (JEDEC_MFR(info) == SNOR_MFR_SPANSION ||
779 info->flags & SPI_NOR_4B_OPCODES)
780 spi_nor_set_4byte_opcodes(nor, info);
785 if (nor->addr_width > SPI_NOR_MAX_ADDR_WIDTH) {
786 dev_dbg(dev, "address width is too large: %u\n",
791 /* Send all the required SPI flash commands to initialize device */
793 ret = spi_nor_init(nor);
800 /* U-Boot specific functions, need to extend MTD to support these */
801 int spi_flash_cmd_get_sw_write_prot(struct spi_nor *nor)