1 // SPDX-License-Identifier: GPL-2.0
3 * Based on m25p80.c, by Mike Lavender (mike@steroidmicros.com), with
4 * influence from lart.c (Abraham Van Der Merwe) and mtd_dataflash.c
6 * Copyright (C) 2005, Intec Automation Inc.
7 * Copyright (C) 2014, Freescale Semiconductor, Inc.
9 * Synced from Linux v4.19
14 #include <dm/device_compat.h>
15 #include <dm/devres.h>
16 #include <linux/err.h>
17 #include <linux/errno.h>
18 #include <linux/log2.h>
19 #include <linux/math64.h>
20 #include <linux/sizes.h>
22 #include <linux/mtd/mtd.h>
23 #include <linux/mtd/spi-nor.h>
27 #include "sf_internal.h"
29 /* Define max times to check status register before we give up. */
32 * For everything but full-chip erase; probably could be much smaller, but kept
33 * around for safety for now
36 #define HZ CONFIG_SYS_HZ
38 #define DEFAULT_READY_WAIT_JIFFIES (40UL * HZ)
40 static int spi_nor_read_write_reg(struct spi_nor *nor, struct spi_mem_op
43 if (op->data.dir == SPI_MEM_DATA_IN)
44 op->data.buf.in = buf;
46 op->data.buf.out = buf;
47 return spi_mem_exec_op(nor->spi, op);
50 static int spi_nor_read_reg(struct spi_nor *nor, u8 code, u8 *val, int len)
52 struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(code, 1),
55 SPI_MEM_OP_DATA_IN(len, NULL, 1));
58 ret = spi_nor_read_write_reg(nor, &op, val);
60 dev_dbg(nor->dev, "error %d reading %x\n", ret, code);
65 static int spi_nor_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
67 struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(opcode, 1),
70 SPI_MEM_OP_DATA_OUT(len, NULL, 1));
72 return spi_nor_read_write_reg(nor, &op, buf);
75 static ssize_t spi_nor_read_data(struct spi_nor *nor, loff_t from, size_t len,
78 struct spi_mem_op op =
79 SPI_MEM_OP(SPI_MEM_OP_CMD(nor->read_opcode, 1),
80 SPI_MEM_OP_ADDR(nor->addr_width, from, 1),
81 SPI_MEM_OP_DUMMY(nor->read_dummy, 1),
82 SPI_MEM_OP_DATA_IN(len, buf, 1));
83 size_t remaining = len;
86 /* get transfer protocols. */
87 op.cmd.buswidth = spi_nor_get_protocol_inst_nbits(nor->read_proto);
88 op.addr.buswidth = spi_nor_get_protocol_addr_nbits(nor->read_proto);
89 op.dummy.buswidth = op.addr.buswidth;
90 op.data.buswidth = spi_nor_get_protocol_data_nbits(nor->read_proto);
92 /* convert the dummy cycles to the number of bytes */
93 op.dummy.nbytes = (nor->read_dummy * op.dummy.buswidth) / 8;
96 op.data.nbytes = remaining < UINT_MAX ? remaining : UINT_MAX;
97 ret = spi_mem_adjust_op_size(nor->spi, &op);
101 ret = spi_mem_exec_op(nor->spi, &op);
105 op.addr.val += op.data.nbytes;
106 remaining -= op.data.nbytes;
107 op.data.buf.in += op.data.nbytes;
113 static ssize_t spi_nor_write_data(struct spi_nor *nor, loff_t to, size_t len,
116 struct spi_mem_op op =
117 SPI_MEM_OP(SPI_MEM_OP_CMD(nor->program_opcode, 1),
118 SPI_MEM_OP_ADDR(nor->addr_width, to, 1),
120 SPI_MEM_OP_DATA_OUT(len, buf, 1));
123 /* get transfer protocols. */
124 op.cmd.buswidth = spi_nor_get_protocol_inst_nbits(nor->write_proto);
125 op.addr.buswidth = spi_nor_get_protocol_addr_nbits(nor->write_proto);
126 op.data.buswidth = spi_nor_get_protocol_data_nbits(nor->write_proto);
128 if (nor->program_opcode == SPINOR_OP_AAI_WP && nor->sst_write_second)
131 ret = spi_mem_adjust_op_size(nor->spi, &op);
134 op.data.nbytes = len < op.data.nbytes ? len : op.data.nbytes;
136 ret = spi_mem_exec_op(nor->spi, &op);
140 return op.data.nbytes;
144 * Read the status register, returning its value in the location
145 * Return the status register value.
146 * Returns negative if error occurred.
148 static int read_sr(struct spi_nor *nor)
153 ret = nor->read_reg(nor, SPINOR_OP_RDSR, &val, 1);
155 pr_debug("error %d reading SR\n", (int)ret);
163 * Read the flag status register, returning its value in the location
164 * Return the status register value.
165 * Returns negative if error occurred.
167 static int read_fsr(struct spi_nor *nor)
172 ret = nor->read_reg(nor, SPINOR_OP_RDFSR, &val, 1);
174 pr_debug("error %d reading FSR\n", ret);
182 * Read configuration register, returning its value in the
183 * location. Return the configuration register value.
184 * Returns negative if error occurred.
186 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
187 static int read_cr(struct spi_nor *nor)
192 ret = nor->read_reg(nor, SPINOR_OP_RDCR, &val, 1);
194 dev_dbg(nor->dev, "error %d reading CR\n", ret);
203 * Write status register 1 byte
204 * Returns negative if error occurred.
206 static int write_sr(struct spi_nor *nor, u8 val)
208 nor->cmd_buf[0] = val;
209 return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1);
213 * Set write enable latch with Write Enable command.
214 * Returns negative if error occurred.
216 static int write_enable(struct spi_nor *nor)
218 return nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0);
222 * Send write disable instruction to the chip.
224 static int write_disable(struct spi_nor *nor)
226 return nor->write_reg(nor, SPINOR_OP_WRDI, NULL, 0);
229 static struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd)
234 #ifndef CONFIG_SPI_FLASH_BAR
235 static u8 spi_nor_convert_opcode(u8 opcode, const u8 table[][2], size_t size)
239 for (i = 0; i < size; i++)
240 if (table[i][0] == opcode)
243 /* No conversion found, keep input op code. */
247 static u8 spi_nor_convert_3to4_read(u8 opcode)
249 static const u8 spi_nor_3to4_read[][2] = {
250 { SPINOR_OP_READ, SPINOR_OP_READ_4B },
251 { SPINOR_OP_READ_FAST, SPINOR_OP_READ_FAST_4B },
252 { SPINOR_OP_READ_1_1_2, SPINOR_OP_READ_1_1_2_4B },
253 { SPINOR_OP_READ_1_2_2, SPINOR_OP_READ_1_2_2_4B },
254 { SPINOR_OP_READ_1_1_4, SPINOR_OP_READ_1_1_4_4B },
255 { SPINOR_OP_READ_1_4_4, SPINOR_OP_READ_1_4_4_4B },
256 { SPINOR_OP_READ_1_1_8, SPINOR_OP_READ_1_1_8_4B },
257 { SPINOR_OP_READ_1_8_8, SPINOR_OP_READ_1_8_8_4B },
259 { SPINOR_OP_READ_1_1_1_DTR, SPINOR_OP_READ_1_1_1_DTR_4B },
260 { SPINOR_OP_READ_1_2_2_DTR, SPINOR_OP_READ_1_2_2_DTR_4B },
261 { SPINOR_OP_READ_1_4_4_DTR, SPINOR_OP_READ_1_4_4_DTR_4B },
264 return spi_nor_convert_opcode(opcode, spi_nor_3to4_read,
265 ARRAY_SIZE(spi_nor_3to4_read));
268 static u8 spi_nor_convert_3to4_program(u8 opcode)
270 static const u8 spi_nor_3to4_program[][2] = {
271 { SPINOR_OP_PP, SPINOR_OP_PP_4B },
272 { SPINOR_OP_PP_1_1_4, SPINOR_OP_PP_1_1_4_4B },
273 { SPINOR_OP_PP_1_4_4, SPINOR_OP_PP_1_4_4_4B },
274 { SPINOR_OP_PP_1_1_8, SPINOR_OP_PP_1_1_8_4B },
275 { SPINOR_OP_PP_1_8_8, SPINOR_OP_PP_1_8_8_4B },
278 return spi_nor_convert_opcode(opcode, spi_nor_3to4_program,
279 ARRAY_SIZE(spi_nor_3to4_program));
282 static u8 spi_nor_convert_3to4_erase(u8 opcode)
284 static const u8 spi_nor_3to4_erase[][2] = {
285 { SPINOR_OP_BE_4K, SPINOR_OP_BE_4K_4B },
286 { SPINOR_OP_BE_32K, SPINOR_OP_BE_32K_4B },
287 { SPINOR_OP_SE, SPINOR_OP_SE_4B },
290 return spi_nor_convert_opcode(opcode, spi_nor_3to4_erase,
291 ARRAY_SIZE(spi_nor_3to4_erase));
294 static void spi_nor_set_4byte_opcodes(struct spi_nor *nor,
295 const struct flash_info *info)
297 /* Do some manufacturer fixups first */
298 switch (JEDEC_MFR(info)) {
299 case SNOR_MFR_SPANSION:
300 /* No small sector erase for 4-byte command set */
301 nor->erase_opcode = SPINOR_OP_SE;
302 nor->mtd.erasesize = info->sector_size;
309 nor->read_opcode = spi_nor_convert_3to4_read(nor->read_opcode);
310 nor->program_opcode = spi_nor_convert_3to4_program(nor->program_opcode);
311 nor->erase_opcode = spi_nor_convert_3to4_erase(nor->erase_opcode);
313 #endif /* !CONFIG_SPI_FLASH_BAR */
315 /* Enable/disable 4-byte addressing mode. */
316 static int set_4byte(struct spi_nor *nor, const struct flash_info *info,
320 bool need_wren = false;
323 switch (JEDEC_MFR(info)) {
325 case SNOR_MFR_MICRON:
326 /* Some Micron need WREN command; all will accept it */
329 case SNOR_MFR_MACRONIX:
330 case SNOR_MFR_WINBOND:
334 cmd = enable ? SPINOR_OP_EN4B : SPINOR_OP_EX4B;
335 status = nor->write_reg(nor, cmd, NULL, 0);
339 if (!status && !enable &&
340 JEDEC_MFR(info) == SNOR_MFR_WINBOND) {
342 * On Winbond W25Q256FV, leaving 4byte mode causes
343 * the Extended Address Register to be set to 1, so all
344 * 3-byte-address reads come from the second 16M.
345 * We must clear the register to enable normal behavior.
349 nor->write_reg(nor, SPINOR_OP_WREAR, nor->cmd_buf, 1);
356 nor->cmd_buf[0] = enable << 7;
357 return nor->write_reg(nor, SPINOR_OP_BRWR, nor->cmd_buf, 1);
361 static int spi_nor_sr_ready(struct spi_nor *nor)
363 int sr = read_sr(nor);
368 if (nor->flags & SNOR_F_USE_CLSR && sr & (SR_E_ERR | SR_P_ERR)) {
370 dev_dbg(nor->dev, "Erase Error occurred\n");
372 dev_dbg(nor->dev, "Programming Error occurred\n");
374 nor->write_reg(nor, SPINOR_OP_CLSR, NULL, 0);
378 return !(sr & SR_WIP);
381 static int spi_nor_fsr_ready(struct spi_nor *nor)
383 int fsr = read_fsr(nor);
388 if (fsr & (FSR_E_ERR | FSR_P_ERR)) {
390 dev_err(nor->dev, "Erase operation failed.\n");
392 dev_err(nor->dev, "Program operation failed.\n");
394 if (fsr & FSR_PT_ERR)
396 "Attempted to modify a protected sector.\n");
398 nor->write_reg(nor, SPINOR_OP_CLFSR, NULL, 0);
402 return fsr & FSR_READY;
405 static int spi_nor_ready(struct spi_nor *nor)
409 sr = spi_nor_sr_ready(nor);
412 fsr = nor->flags & SNOR_F_USE_FSR ? spi_nor_fsr_ready(nor) : 1;
419 * Service routine to read status register until ready, or timeout occurs.
420 * Returns non-zero if error.
422 static int spi_nor_wait_till_ready_with_timeout(struct spi_nor *nor,
423 unsigned long timeout)
425 unsigned long timebase;
428 timebase = get_timer(0);
430 while (get_timer(timebase) < timeout) {
431 ret = spi_nor_ready(nor);
438 dev_err(nor->dev, "flash operation timed out\n");
443 static int spi_nor_wait_till_ready(struct spi_nor *nor)
445 return spi_nor_wait_till_ready_with_timeout(nor,
446 DEFAULT_READY_WAIT_JIFFIES);
449 #ifdef CONFIG_SPI_FLASH_BAR
451 * This "clean_bar" is necessary in a situation when one was accessing
452 * spi flash memory > 16 MiB by using Bank Address Register's BA24 bit.
454 * After it the BA24 bit shall be cleared to allow access to correct
455 * memory region after SW reset (by calling "reset" command).
457 * Otherwise, the BA24 bit may be left set and then after reset, the
458 * ROM would read/write/erase SPL from 16 MiB * bank_sel address.
460 static int clean_bar(struct spi_nor *nor)
462 u8 cmd, bank_sel = 0;
464 if (nor->bank_curr == 0)
466 cmd = nor->bank_write_cmd;
470 return nor->write_reg(nor, cmd, &bank_sel, 1);
473 static int write_bar(struct spi_nor *nor, u32 offset)
478 bank_sel = offset / SZ_16M;
479 if (bank_sel == nor->bank_curr)
482 cmd = nor->bank_write_cmd;
484 ret = nor->write_reg(nor, cmd, &bank_sel, 1);
486 debug("SF: fail to write bank register\n");
491 nor->bank_curr = bank_sel;
492 return nor->bank_curr;
495 static int read_bar(struct spi_nor *nor, const struct flash_info *info)
500 switch (JEDEC_MFR(info)) {
501 case SNOR_MFR_SPANSION:
502 nor->bank_read_cmd = SPINOR_OP_BRRD;
503 nor->bank_write_cmd = SPINOR_OP_BRWR;
506 nor->bank_read_cmd = SPINOR_OP_RDEAR;
507 nor->bank_write_cmd = SPINOR_OP_WREAR;
510 ret = nor->read_reg(nor, nor->bank_read_cmd,
513 debug("SF: fail to read bank addr register\n");
516 nor->bank_curr = curr_bank;
523 * Initiate the erasure of a single sector
525 static int spi_nor_erase_sector(struct spi_nor *nor, u32 addr)
527 struct spi_mem_op op =
528 SPI_MEM_OP(SPI_MEM_OP_CMD(nor->erase_opcode, 1),
529 SPI_MEM_OP_ADDR(nor->addr_width, addr, 1),
534 return nor->erase(nor, addr);
537 * Default implementation, if driver doesn't have a specialized HW
540 return spi_mem_exec_op(nor->spi, &op);
544 * Erase an address range on the nor chip. The address range may extend
545 * one or more erase sectors. Return an error is there is a problem erasing.
547 static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
549 struct spi_nor *nor = mtd_to_spi_nor(mtd);
553 dev_dbg(nor->dev, "at 0x%llx, len %lld\n", (long long)instr->addr,
554 (long long)instr->len);
559 div_u64_rem(instr->len, mtd->erasesize, &rem);
567 #ifdef CONFIG_SPI_FLASH_BAR
568 ret = write_bar(nor, addr);
574 ret = spi_nor_erase_sector(nor, addr);
578 addr += mtd->erasesize;
579 len -= mtd->erasesize;
581 ret = spi_nor_wait_till_ready(nor);
587 #ifdef CONFIG_SPI_FLASH_BAR
588 ret = clean_bar(nor);
595 #if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST)
596 /* Write status register and ensure bits in mask match written values */
597 static int write_sr_and_check(struct spi_nor *nor, u8 status_new, u8 mask)
602 ret = write_sr(nor, status_new);
606 ret = spi_nor_wait_till_ready(nor);
614 return ((ret & mask) != (status_new & mask)) ? -EIO : 0;
617 static void stm_get_locked_range(struct spi_nor *nor, u8 sr, loff_t *ofs,
620 struct mtd_info *mtd = &nor->mtd;
621 u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
622 int shift = ffs(mask) - 1;
630 pow = ((sr & mask) ^ mask) >> shift;
631 *len = mtd->size >> pow;
632 if (nor->flags & SNOR_F_HAS_SR_TB && sr & SR_TB)
635 *ofs = mtd->size - *len;
640 * Return 1 if the entire region is locked (if @locked is true) or unlocked (if
641 * @locked is false); 0 otherwise
643 static int stm_check_lock_status_sr(struct spi_nor *nor, loff_t ofs, u64 len,
652 stm_get_locked_range(nor, sr, &lock_offs, &lock_len);
655 /* Requested range is a sub-range of locked range */
656 return (ofs + len <= lock_offs + lock_len) && (ofs >= lock_offs);
658 /* Requested range does not overlap with locked range */
659 return (ofs >= lock_offs + lock_len) || (ofs + len <= lock_offs);
662 static int stm_is_locked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len,
665 return stm_check_lock_status_sr(nor, ofs, len, sr, true);
668 static int stm_is_unlocked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len,
671 return stm_check_lock_status_sr(nor, ofs, len, sr, false);
675 * Lock a region of the flash. Compatible with ST Micro and similar flash.
676 * Supports the block protection bits BP{0,1,2} in the status register
677 * (SR). Does not support these features found in newer SR bitfields:
678 * - SEC: sector/block protect - only handle SEC=0 (block protect)
679 * - CMP: complement protect - only support CMP=0 (range is not complemented)
681 * Support for the following is provided conditionally for some flash:
682 * - TB: top/bottom protect
684 * Sample table portion for 8MB flash (Winbond w25q64fw):
686 * SEC | TB | BP2 | BP1 | BP0 | Prot Length | Protected Portion
687 * --------------------------------------------------------------------------
688 * X | X | 0 | 0 | 0 | NONE | NONE
689 * 0 | 0 | 0 | 0 | 1 | 128 KB | Upper 1/64
690 * 0 | 0 | 0 | 1 | 0 | 256 KB | Upper 1/32
691 * 0 | 0 | 0 | 1 | 1 | 512 KB | Upper 1/16
692 * 0 | 0 | 1 | 0 | 0 | 1 MB | Upper 1/8
693 * 0 | 0 | 1 | 0 | 1 | 2 MB | Upper 1/4
694 * 0 | 0 | 1 | 1 | 0 | 4 MB | Upper 1/2
695 * X | X | 1 | 1 | 1 | 8 MB | ALL
696 * ------|-------|-------|-------|-------|---------------|-------------------
697 * 0 | 1 | 0 | 0 | 1 | 128 KB | Lower 1/64
698 * 0 | 1 | 0 | 1 | 0 | 256 KB | Lower 1/32
699 * 0 | 1 | 0 | 1 | 1 | 512 KB | Lower 1/16
700 * 0 | 1 | 1 | 0 | 0 | 1 MB | Lower 1/8
701 * 0 | 1 | 1 | 0 | 1 | 2 MB | Lower 1/4
702 * 0 | 1 | 1 | 1 | 0 | 4 MB | Lower 1/2
704 * Returns negative on errors, 0 on success.
706 static int stm_lock(struct spi_nor *nor, loff_t ofs, uint64_t len)
708 struct mtd_info *mtd = &nor->mtd;
709 int status_old, status_new;
710 u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
711 u8 shift = ffs(mask) - 1, pow, val;
713 bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB;
716 status_old = read_sr(nor);
720 /* If nothing in our range is unlocked, we don't need to do anything */
721 if (stm_is_locked_sr(nor, ofs, len, status_old))
724 /* If anything below us is unlocked, we can't use 'bottom' protection */
725 if (!stm_is_locked_sr(nor, 0, ofs, status_old))
726 can_be_bottom = false;
728 /* If anything above us is unlocked, we can't use 'top' protection */
729 if (!stm_is_locked_sr(nor, ofs + len, mtd->size - (ofs + len),
733 if (!can_be_bottom && !can_be_top)
736 /* Prefer top, if both are valid */
737 use_top = can_be_top;
739 /* lock_len: length of region that should end up locked */
741 lock_len = mtd->size - ofs;
743 lock_len = ofs + len;
746 * Need smallest pow such that:
748 * 1 / (2^pow) <= (len / size)
750 * so (assuming power-of-2 size) we do:
752 * pow = ceil(log2(size / len)) = log2(size) - floor(log2(len))
754 pow = ilog2(mtd->size) - ilog2(lock_len);
755 val = mask - (pow << shift);
758 /* Don't "lock" with no region! */
762 status_new = (status_old & ~mask & ~SR_TB) | val;
764 /* Disallow further writes if WP pin is asserted */
765 status_new |= SR_SRWD;
770 /* Don't bother if they're the same */
771 if (status_new == status_old)
774 /* Only modify protection if it will not unlock other areas */
775 if ((status_new & mask) < (status_old & mask))
778 return write_sr_and_check(nor, status_new, mask);
782 * Unlock a region of the flash. See stm_lock() for more info
784 * Returns negative on errors, 0 on success.
786 static int stm_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len)
788 struct mtd_info *mtd = &nor->mtd;
789 int status_old, status_new;
790 u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
791 u8 shift = ffs(mask) - 1, pow, val;
793 bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB;
796 status_old = read_sr(nor);
800 /* If nothing in our range is locked, we don't need to do anything */
801 if (stm_is_unlocked_sr(nor, ofs, len, status_old))
804 /* If anything below us is locked, we can't use 'top' protection */
805 if (!stm_is_unlocked_sr(nor, 0, ofs, status_old))
808 /* If anything above us is locked, we can't use 'bottom' protection */
809 if (!stm_is_unlocked_sr(nor, ofs + len, mtd->size - (ofs + len),
811 can_be_bottom = false;
813 if (!can_be_bottom && !can_be_top)
816 /* Prefer top, if both are valid */
817 use_top = can_be_top;
819 /* lock_len: length of region that should remain locked */
821 lock_len = mtd->size - (ofs + len);
826 * Need largest pow such that:
828 * 1 / (2^pow) >= (len / size)
830 * so (assuming power-of-2 size) we do:
832 * pow = floor(log2(size / len)) = log2(size) - ceil(log2(len))
834 pow = ilog2(mtd->size) - order_base_2(lock_len);
836 val = 0; /* fully unlocked */
838 val = mask - (pow << shift);
839 /* Some power-of-two sizes are not supported */
844 status_new = (status_old & ~mask & ~SR_TB) | val;
846 /* Don't protect status register if we're fully unlocked */
848 status_new &= ~SR_SRWD;
853 /* Don't bother if they're the same */
854 if (status_new == status_old)
857 /* Only modify protection if it will not lock other areas */
858 if ((status_new & mask) > (status_old & mask))
861 return write_sr_and_check(nor, status_new, mask);
865 * Check if a region of the flash is (completely) locked. See stm_lock() for
868 * Returns 1 if entire region is locked, 0 if any portion is unlocked, and
869 * negative on errors.
871 static int stm_is_locked(struct spi_nor *nor, loff_t ofs, uint64_t len)
875 status = read_sr(nor);
879 return stm_is_locked_sr(nor, ofs, len, status);
881 #endif /* CONFIG_SPI_FLASH_STMICRO */
883 static const struct flash_info *spi_nor_read_id(struct spi_nor *nor)
886 u8 id[SPI_NOR_MAX_ID_LEN];
887 const struct flash_info *info;
889 tmp = nor->read_reg(nor, SPINOR_OP_RDID, id, SPI_NOR_MAX_ID_LEN);
891 dev_dbg(nor->dev, "error %d reading JEDEC ID\n", tmp);
896 for (; info->name; info++) {
898 if (!memcmp(info->id, id, info->id_len))
903 dev_err(nor->dev, "unrecognized JEDEC id bytes: %02x, %02x, %02x\n",
904 id[0], id[1], id[2]);
905 return ERR_PTR(-ENODEV);
908 static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len,
909 size_t *retlen, u_char *buf)
911 struct spi_nor *nor = mtd_to_spi_nor(mtd);
914 dev_dbg(nor->dev, "from 0x%08x, len %zd\n", (u32)from, len);
918 size_t read_len = len;
920 #ifdef CONFIG_SPI_FLASH_BAR
923 ret = write_bar(nor, addr);
926 remain_len = (SZ_16M * (nor->bank_curr + 1)) - addr;
928 if (len < remain_len)
931 read_len = remain_len;
934 ret = nor->read(nor, addr, read_len, buf);
936 /* We shouldn't see 0-length reads */
951 #ifdef CONFIG_SPI_FLASH_BAR
952 ret = clean_bar(nor);
957 #ifdef CONFIG_SPI_FLASH_SST
959 * sst26 flash series has its own block protection implementation:
960 * 4x - 8 KByte blocks - read & write protection bits - upper addresses
961 * 1x - 32 KByte blocks - write protection bits
962 * rest - 64 KByte blocks - write protection bits
963 * 1x - 32 KByte blocks - write protection bits
964 * 4x - 8 KByte blocks - read & write protection bits - lower addresses
966 * We'll support only per 64k lock/unlock so lower and upper 64 KByte region
967 * will be treated as single block.
969 #define SST26_BPR_8K_NUM 4
970 #define SST26_MAX_BPR_REG_LEN (18 + 1)
971 #define SST26_BOUND_REG_SIZE ((32 + SST26_BPR_8K_NUM * 8) * SZ_1K)
979 static bool sst26_process_bpr(u32 bpr_size, u8 *cmd, u32 bit, enum lock_ctl ctl)
983 cmd[bpr_size - (bit / 8) - 1] |= BIT(bit % 8);
985 case SST26_CTL_UNLOCK:
986 cmd[bpr_size - (bit / 8) - 1] &= ~BIT(bit % 8);
988 case SST26_CTL_CHECK:
989 return !!(cmd[bpr_size - (bit / 8) - 1] & BIT(bit % 8));
996 * Lock, unlock or check lock status of the flash region of the flash (depending
997 * on the lock_ctl value)
999 static int sst26_lock_ctl(struct spi_nor *nor, loff_t ofs, uint64_t len, enum lock_ctl ctl)
1001 struct mtd_info *mtd = &nor->mtd;
1002 u32 i, bpr_ptr, rptr_64k, lptr_64k, bpr_size;
1003 bool lower_64k = false, upper_64k = false;
1004 u8 bpr_buff[SST26_MAX_BPR_REG_LEN] = {};
1007 /* Check length and offset for 64k alignment */
1008 if ((ofs & (SZ_64K - 1)) || (len & (SZ_64K - 1))) {
1009 dev_err(nor->dev, "length or offset is not 64KiB allighned\n");
1013 if (ofs + len > mtd->size) {
1014 dev_err(nor->dev, "range is more than device size: %#llx + %#llx > %#llx\n",
1015 ofs, len, mtd->size);
1019 /* SST26 family has only 16 Mbit, 32 Mbit and 64 Mbit IC */
1020 if (mtd->size != SZ_2M &&
1021 mtd->size != SZ_4M &&
1025 bpr_size = 2 + (mtd->size / SZ_64K / 8);
1027 ret = nor->read_reg(nor, SPINOR_OP_READ_BPR, bpr_buff, bpr_size);
1029 dev_err(nor->dev, "fail to read block-protection register\n");
1033 rptr_64k = min_t(u32, ofs + len, mtd->size - SST26_BOUND_REG_SIZE);
1034 lptr_64k = max_t(u32, ofs, SST26_BOUND_REG_SIZE);
1036 upper_64k = ((ofs + len) > (mtd->size - SST26_BOUND_REG_SIZE));
1037 lower_64k = (ofs < SST26_BOUND_REG_SIZE);
1039 /* Lower bits in block-protection register are about 64k region */
1040 bpr_ptr = lptr_64k / SZ_64K - 1;
1042 /* Process 64K blocks region */
1043 while (lptr_64k < rptr_64k) {
1044 if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl))
1051 /* 32K and 8K region bits in BPR are after 64k region bits */
1052 bpr_ptr = (mtd->size - 2 * SST26_BOUND_REG_SIZE) / SZ_64K;
1054 /* Process lower 32K block region */
1056 if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl))
1061 /* Process upper 32K block region */
1063 if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl))
1068 /* Process lower 8K block regions */
1069 for (i = 0; i < SST26_BPR_8K_NUM; i++) {
1071 if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl))
1074 /* In 8K area BPR has both read and write protection bits */
1078 /* Process upper 8K block regions */
1079 for (i = 0; i < SST26_BPR_8K_NUM; i++) {
1081 if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl))
1084 /* In 8K area BPR has both read and write protection bits */
1088 /* If we check region status we don't need to write BPR back */
1089 if (ctl == SST26_CTL_CHECK)
1092 ret = nor->write_reg(nor, SPINOR_OP_WRITE_BPR, bpr_buff, bpr_size);
1094 dev_err(nor->dev, "fail to write block-protection register\n");
1101 static int sst26_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len)
1103 return sst26_lock_ctl(nor, ofs, len, SST26_CTL_UNLOCK);
1106 static int sst26_lock(struct spi_nor *nor, loff_t ofs, uint64_t len)
1108 return sst26_lock_ctl(nor, ofs, len, SST26_CTL_LOCK);
1112 * Returns EACCES (positive value) if region is locked, 0 if region is unlocked,
1113 * and negative on errors.
1115 static int sst26_is_locked(struct spi_nor *nor, loff_t ofs, uint64_t len)
1118 * is_locked function is used for check before reading or erasing flash
1119 * region, so offset and length might be not 64k allighned, so adjust
1120 * them to be 64k allighned as sst26_lock_ctl works only with 64k
1121 * allighned regions.
1123 ofs -= ofs & (SZ_64K - 1);
1124 len = len & (SZ_64K - 1) ? (len & ~(SZ_64K - 1)) + SZ_64K : len;
1126 return sst26_lock_ctl(nor, ofs, len, SST26_CTL_CHECK);
1129 static int sst_write_byteprogram(struct spi_nor *nor, loff_t to, size_t len,
1130 size_t *retlen, const u_char *buf)
1135 for (actual = 0; actual < len; actual++) {
1136 nor->program_opcode = SPINOR_OP_BP;
1139 /* write one byte. */
1140 ret = nor->write(nor, to, 1, buf + actual);
1143 ret = spi_nor_wait_till_ready(nor);
1154 static int sst_write(struct mtd_info *mtd, loff_t to, size_t len,
1155 size_t *retlen, const u_char *buf)
1157 struct spi_nor *nor = mtd_to_spi_nor(mtd);
1158 struct spi_slave *spi = nor->spi;
1162 dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len);
1163 if (spi->mode & SPI_TX_BYTE)
1164 return sst_write_byteprogram(nor, to, len, retlen, buf);
1168 nor->sst_write_second = false;
1171 /* Start write from odd address. */
1173 nor->program_opcode = SPINOR_OP_BP;
1175 /* write one byte. */
1176 ret = nor->write(nor, to, 1, buf);
1179 ret = spi_nor_wait_till_ready(nor);
1185 /* Write out most of the data here. */
1186 for (; actual < len - 1; actual += 2) {
1187 nor->program_opcode = SPINOR_OP_AAI_WP;
1189 /* write two bytes. */
1190 ret = nor->write(nor, to, 2, buf + actual);
1193 ret = spi_nor_wait_till_ready(nor);
1197 nor->sst_write_second = true;
1199 nor->sst_write_second = false;
1202 ret = spi_nor_wait_till_ready(nor);
1206 /* Write out trailing byte if it exists. */
1207 if (actual != len) {
1210 nor->program_opcode = SPINOR_OP_BP;
1211 ret = nor->write(nor, to, 1, buf + actual);
1214 ret = spi_nor_wait_till_ready(nor);
1226 * Write an address range to the nor chip. Data must be written in
1227 * FLASH_PAGESIZE chunks. The address range may be any size provided
1228 * it is within the physical boundaries.
1230 static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len,
1231 size_t *retlen, const u_char *buf)
1233 struct spi_nor *nor = mtd_to_spi_nor(mtd);
1234 size_t page_offset, page_remain, i;
1237 dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len);
1242 for (i = 0; i < len; ) {
1244 loff_t addr = to + i;
1247 * If page_size is a power of two, the offset can be quickly
1248 * calculated with an AND operation. On the other cases we
1249 * need to do a modulus operation (more expensive).
1251 if (is_power_of_2(nor->page_size)) {
1252 page_offset = addr & (nor->page_size - 1);
1256 page_offset = do_div(aux, nor->page_size);
1258 /* the size of data remaining on the first page */
1259 page_remain = min_t(size_t,
1260 nor->page_size - page_offset, len - i);
1262 #ifdef CONFIG_SPI_FLASH_BAR
1263 ret = write_bar(nor, addr);
1268 ret = nor->write(nor, addr, page_remain, buf + i);
1273 ret = spi_nor_wait_till_ready(nor);
1281 #ifdef CONFIG_SPI_FLASH_BAR
1282 ret = clean_bar(nor);
1287 #ifdef CONFIG_SPI_FLASH_MACRONIX
1289 * macronix_quad_enable() - set QE bit in Status Register.
1290 * @nor: pointer to a 'struct spi_nor'
1292 * Set the Quad Enable (QE) bit in the Status Register.
1294 * bit 6 of the Status Register is the QE bit for Macronix like QSPI memories.
1296 * Return: 0 on success, -errno otherwise.
1298 static int macronix_quad_enable(struct spi_nor *nor)
1305 if (val & SR_QUAD_EN_MX)
1310 write_sr(nor, val | SR_QUAD_EN_MX);
1312 ret = spi_nor_wait_till_ready(nor);
1317 if (!(ret > 0 && (ret & SR_QUAD_EN_MX))) {
1318 dev_err(nor->dev, "Macronix Quad bit not set\n");
1326 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
1328 * Write status Register and configuration register with 2 bytes
1329 * The first byte will be written to the status register, while the
1330 * second byte will be written to the configuration register.
1331 * Return negative if error occurred.
1333 static int write_sr_cr(struct spi_nor *nor, u8 *sr_cr)
1339 ret = nor->write_reg(nor, SPINOR_OP_WRSR, sr_cr, 2);
1342 "error while writing configuration register\n");
1346 ret = spi_nor_wait_till_ready(nor);
1349 "timeout while writing configuration register\n");
1357 * spansion_read_cr_quad_enable() - set QE bit in Configuration Register.
1358 * @nor: pointer to a 'struct spi_nor'
1360 * Set the Quad Enable (QE) bit in the Configuration Register.
1361 * This function should be used with QSPI memories supporting the Read
1362 * Configuration Register (35h) instruction.
1364 * bit 1 of the Configuration Register is the QE bit for Spansion like QSPI
1367 * Return: 0 on success, -errno otherwise.
1369 static int spansion_read_cr_quad_enable(struct spi_nor *nor)
1374 /* Check current Quad Enable bit value. */
1378 "error while reading configuration register\n");
1382 if (ret & CR_QUAD_EN_SPAN)
1385 sr_cr[1] = ret | CR_QUAD_EN_SPAN;
1387 /* Keep the current value of the Status Register. */
1390 dev_dbg(nor->dev, "error while reading status register\n");
1395 ret = write_sr_cr(nor, sr_cr);
1399 /* Read back and check it. */
1401 if (!(ret > 0 && (ret & CR_QUAD_EN_SPAN))) {
1402 dev_dbg(nor->dev, "Spansion Quad bit not set\n");
1409 #if CONFIG_IS_ENABLED(SPI_FLASH_SFDP_SUPPORT)
1411 * spansion_no_read_cr_quad_enable() - set QE bit in Configuration Register.
1412 * @nor: pointer to a 'struct spi_nor'
1414 * Set the Quad Enable (QE) bit in the Configuration Register.
1415 * This function should be used with QSPI memories not supporting the Read
1416 * Configuration Register (35h) instruction.
1418 * bit 1 of the Configuration Register is the QE bit for Spansion like QSPI
1421 * Return: 0 on success, -errno otherwise.
1423 static int spansion_no_read_cr_quad_enable(struct spi_nor *nor)
1428 /* Keep the current value of the Status Register. */
1431 dev_dbg(nor->dev, "error while reading status register\n");
1435 sr_cr[1] = CR_QUAD_EN_SPAN;
1437 return write_sr_cr(nor, sr_cr);
1440 #endif /* CONFIG_SPI_FLASH_SFDP_SUPPORT */
1441 #endif /* CONFIG_SPI_FLASH_SPANSION */
1443 struct spi_nor_read_command {
1447 enum spi_nor_protocol proto;
1450 struct spi_nor_pp_command {
1452 enum spi_nor_protocol proto;
1455 enum spi_nor_read_command_index {
1458 SNOR_CMD_READ_1_1_1_DTR,
1461 SNOR_CMD_READ_1_1_2,
1462 SNOR_CMD_READ_1_2_2,
1463 SNOR_CMD_READ_2_2_2,
1464 SNOR_CMD_READ_1_2_2_DTR,
1467 SNOR_CMD_READ_1_1_4,
1468 SNOR_CMD_READ_1_4_4,
1469 SNOR_CMD_READ_4_4_4,
1470 SNOR_CMD_READ_1_4_4_DTR,
1473 SNOR_CMD_READ_1_1_8,
1474 SNOR_CMD_READ_1_8_8,
1475 SNOR_CMD_READ_8_8_8,
1476 SNOR_CMD_READ_1_8_8_DTR,
1481 enum spi_nor_pp_command_index {
1497 struct spi_nor_flash_parameter {
1501 struct spi_nor_hwcaps hwcaps;
1502 struct spi_nor_read_command reads[SNOR_CMD_READ_MAX];
1503 struct spi_nor_pp_command page_programs[SNOR_CMD_PP_MAX];
1505 int (*quad_enable)(struct spi_nor *nor);
1509 spi_nor_set_read_settings(struct spi_nor_read_command *read,
1513 enum spi_nor_protocol proto)
1515 read->num_mode_clocks = num_mode_clocks;
1516 read->num_wait_states = num_wait_states;
1517 read->opcode = opcode;
1518 read->proto = proto;
1522 spi_nor_set_pp_settings(struct spi_nor_pp_command *pp,
1524 enum spi_nor_protocol proto)
1526 pp->opcode = opcode;
1530 #if CONFIG_IS_ENABLED(SPI_FLASH_SFDP_SUPPORT)
1532 * Serial Flash Discoverable Parameters (SFDP) parsing.
1536 * spi_nor_read_sfdp() - read Serial Flash Discoverable Parameters.
1537 * @nor: pointer to a 'struct spi_nor'
1538 * @addr: offset in the SFDP area to start reading data from
1539 * @len: number of bytes to read
1540 * @buf: buffer where the SFDP data are copied into (dma-safe memory)
1542 * Whatever the actual numbers of bytes for address and dummy cycles are
1543 * for (Fast) Read commands, the Read SFDP (5Ah) instruction is always
1544 * followed by a 3-byte address and 8 dummy clock cycles.
1546 * Return: 0 on success, -errno otherwise.
1548 static int spi_nor_read_sfdp(struct spi_nor *nor, u32 addr,
1549 size_t len, void *buf)
1551 u8 addr_width, read_opcode, read_dummy;
1554 read_opcode = nor->read_opcode;
1555 addr_width = nor->addr_width;
1556 read_dummy = nor->read_dummy;
1558 nor->read_opcode = SPINOR_OP_RDSFDP;
1559 nor->addr_width = 3;
1560 nor->read_dummy = 8;
1563 ret = nor->read(nor, addr, len, (u8 *)buf);
1564 if (!ret || ret > len) {
1578 nor->read_opcode = read_opcode;
1579 nor->addr_width = addr_width;
1580 nor->read_dummy = read_dummy;
1585 struct sfdp_parameter_header {
1589 u8 length; /* in double words */
1590 u8 parameter_table_pointer[3]; /* byte address */
1594 #define SFDP_PARAM_HEADER_ID(p) (((p)->id_msb << 8) | (p)->id_lsb)
1595 #define SFDP_PARAM_HEADER_PTP(p) \
1596 (((p)->parameter_table_pointer[2] << 16) | \
1597 ((p)->parameter_table_pointer[1] << 8) | \
1598 ((p)->parameter_table_pointer[0] << 0))
1600 #define SFDP_BFPT_ID 0xff00 /* Basic Flash Parameter Table */
1601 #define SFDP_SECTOR_MAP_ID 0xff81 /* Sector Map Table */
1602 #define SFDP_SST_ID 0x01bf /* Manufacturer specific Table */
1604 #define SFDP_SIGNATURE 0x50444653U
1605 #define SFDP_JESD216_MAJOR 1
1606 #define SFDP_JESD216_MINOR 0
1607 #define SFDP_JESD216A_MINOR 5
1608 #define SFDP_JESD216B_MINOR 6
1610 struct sfdp_header {
1611 u32 signature; /* Ox50444653U <=> "SFDP" */
1614 u8 nph; /* 0-base number of parameter headers */
1617 /* Basic Flash Parameter Table. */
1618 struct sfdp_parameter_header bfpt_header;
1621 /* Basic Flash Parameter Table */
1624 * JESD216 rev B defines a Basic Flash Parameter Table of 16 DWORDs.
1625 * They are indexed from 1 but C arrays are indexed from 0.
1627 #define BFPT_DWORD(i) ((i) - 1)
1628 #define BFPT_DWORD_MAX 16
1630 /* The first version of JESB216 defined only 9 DWORDs. */
1631 #define BFPT_DWORD_MAX_JESD216 9
1634 #define BFPT_DWORD1_FAST_READ_1_1_2 BIT(16)
1635 #define BFPT_DWORD1_ADDRESS_BYTES_MASK GENMASK(18, 17)
1636 #define BFPT_DWORD1_ADDRESS_BYTES_3_ONLY (0x0UL << 17)
1637 #define BFPT_DWORD1_ADDRESS_BYTES_3_OR_4 (0x1UL << 17)
1638 #define BFPT_DWORD1_ADDRESS_BYTES_4_ONLY (0x2UL << 17)
1639 #define BFPT_DWORD1_DTR BIT(19)
1640 #define BFPT_DWORD1_FAST_READ_1_2_2 BIT(20)
1641 #define BFPT_DWORD1_FAST_READ_1_4_4 BIT(21)
1642 #define BFPT_DWORD1_FAST_READ_1_1_4 BIT(22)
1645 #define BFPT_DWORD5_FAST_READ_2_2_2 BIT(0)
1646 #define BFPT_DWORD5_FAST_READ_4_4_4 BIT(4)
1649 #define BFPT_DWORD11_PAGE_SIZE_SHIFT 4
1650 #define BFPT_DWORD11_PAGE_SIZE_MASK GENMASK(7, 4)
1655 * (from JESD216 rev B)
1656 * Quad Enable Requirements (QER):
1657 * - 000b: Device does not have a QE bit. Device detects 1-1-4 and 1-4-4
1658 * reads based on instruction. DQ3/HOLD# functions are hold during
1659 * instruction phase.
1660 * - 001b: QE is bit 1 of status register 2. It is set via Write Status with
1661 * two data bytes where bit 1 of the second byte is one.
1663 * Writing only one byte to the status register has the side-effect of
1664 * clearing status register 2, including the QE bit. The 100b code is
1665 * used if writing one byte to the status register does not modify
1666 * status register 2.
1667 * - 010b: QE is bit 6 of status register 1. It is set via Write Status with
1668 * one data byte where bit 6 is one.
1670 * - 011b: QE is bit 7 of status register 2. It is set via Write status
1671 * register 2 instruction 3Eh with one data byte where bit 7 is one.
1673 * The status register 2 is read using instruction 3Fh.
1674 * - 100b: QE is bit 1 of status register 2. It is set via Write Status with
1675 * two data bytes where bit 1 of the second byte is one.
1677 * In contrast to the 001b code, writing one byte to the status
1678 * register does not modify status register 2.
1679 * - 101b: QE is bit 1 of status register 2. Status register 1 is read using
1680 * Read Status instruction 05h. Status register2 is read using
1681 * instruction 35h. QE is set via Writ Status instruction 01h with
1682 * two data bytes where bit 1 of the second byte is one.
1685 #define BFPT_DWORD15_QER_MASK GENMASK(22, 20)
1686 #define BFPT_DWORD15_QER_NONE (0x0UL << 20) /* Micron */
1687 #define BFPT_DWORD15_QER_SR2_BIT1_BUGGY (0x1UL << 20)
1688 #define BFPT_DWORD15_QER_SR1_BIT6 (0x2UL << 20) /* Macronix */
1689 #define BFPT_DWORD15_QER_SR2_BIT7 (0x3UL << 20)
1690 #define BFPT_DWORD15_QER_SR2_BIT1_NO_RD (0x4UL << 20)
1691 #define BFPT_DWORD15_QER_SR2_BIT1 (0x5UL << 20) /* Spansion */
1694 u32 dwords[BFPT_DWORD_MAX];
1697 /* Fast Read settings. */
1700 spi_nor_set_read_settings_from_bfpt(struct spi_nor_read_command *read,
1702 enum spi_nor_protocol proto)
1704 read->num_mode_clocks = (half >> 5) & 0x07;
1705 read->num_wait_states = (half >> 0) & 0x1f;
1706 read->opcode = (half >> 8) & 0xff;
1707 read->proto = proto;
1710 struct sfdp_bfpt_read {
1711 /* The Fast Read x-y-z hardware capability in params->hwcaps.mask. */
1715 * The <supported_bit> bit in <supported_dword> BFPT DWORD tells us
1716 * whether the Fast Read x-y-z command is supported.
1718 u32 supported_dword;
1722 * The half-word at offset <setting_shift> in <setting_dword> BFPT DWORD
1723 * encodes the op code, the number of mode clocks and the number of wait
1724 * states to be used by Fast Read x-y-z command.
1729 /* The SPI protocol for this Fast Read x-y-z command. */
1730 enum spi_nor_protocol proto;
1733 static const struct sfdp_bfpt_read sfdp_bfpt_reads[] = {
1734 /* Fast Read 1-1-2 */
1736 SNOR_HWCAPS_READ_1_1_2,
1737 BFPT_DWORD(1), BIT(16), /* Supported bit */
1738 BFPT_DWORD(4), 0, /* Settings */
1742 /* Fast Read 1-2-2 */
1744 SNOR_HWCAPS_READ_1_2_2,
1745 BFPT_DWORD(1), BIT(20), /* Supported bit */
1746 BFPT_DWORD(4), 16, /* Settings */
1750 /* Fast Read 2-2-2 */
1752 SNOR_HWCAPS_READ_2_2_2,
1753 BFPT_DWORD(5), BIT(0), /* Supported bit */
1754 BFPT_DWORD(6), 16, /* Settings */
1758 /* Fast Read 1-1-4 */
1760 SNOR_HWCAPS_READ_1_1_4,
1761 BFPT_DWORD(1), BIT(22), /* Supported bit */
1762 BFPT_DWORD(3), 16, /* Settings */
1766 /* Fast Read 1-4-4 */
1768 SNOR_HWCAPS_READ_1_4_4,
1769 BFPT_DWORD(1), BIT(21), /* Supported bit */
1770 BFPT_DWORD(3), 0, /* Settings */
1774 /* Fast Read 4-4-4 */
1776 SNOR_HWCAPS_READ_4_4_4,
1777 BFPT_DWORD(5), BIT(4), /* Supported bit */
1778 BFPT_DWORD(7), 16, /* Settings */
1783 struct sfdp_bfpt_erase {
1785 * The half-word at offset <shift> in DWORD <dwoard> encodes the
1786 * op code and erase sector size to be used by Sector Erase commands.
1792 static const struct sfdp_bfpt_erase sfdp_bfpt_erases[] = {
1793 /* Erase Type 1 in DWORD8 bits[15:0] */
1796 /* Erase Type 2 in DWORD8 bits[31:16] */
1797 {BFPT_DWORD(8), 16},
1799 /* Erase Type 3 in DWORD9 bits[15:0] */
1802 /* Erase Type 4 in DWORD9 bits[31:16] */
1803 {BFPT_DWORD(9), 16},
1806 static int spi_nor_hwcaps_read2cmd(u32 hwcaps);
1809 * spi_nor_parse_bfpt() - read and parse the Basic Flash Parameter Table.
1810 * @nor: pointer to a 'struct spi_nor'
1811 * @bfpt_header: pointer to the 'struct sfdp_parameter_header' describing
1812 * the Basic Flash Parameter Table length and version
1813 * @params: pointer to the 'struct spi_nor_flash_parameter' to be
1816 * The Basic Flash Parameter Table is the main and only mandatory table as
1817 * defined by the SFDP (JESD216) specification.
1818 * It provides us with the total size (memory density) of the data array and
1819 * the number of address bytes for Fast Read, Page Program and Sector Erase
1821 * For Fast READ commands, it also gives the number of mode clock cycles and
1822 * wait states (regrouped in the number of dummy clock cycles) for each
1823 * supported instruction op code.
1824 * For Page Program, the page size is now available since JESD216 rev A, however
1825 * the supported instruction op codes are still not provided.
1826 * For Sector Erase commands, this table stores the supported instruction op
1827 * codes and the associated sector sizes.
1828 * Finally, the Quad Enable Requirements (QER) are also available since JESD216
1829 * rev A. The QER bits encode the manufacturer dependent procedure to be
1830 * executed to set the Quad Enable (QE) bit in some internal register of the
1831 * Quad SPI memory. Indeed the QE bit, when it exists, must be set before
1832 * sending any Quad SPI command to the memory. Actually, setting the QE bit
1833 * tells the memory to reassign its WP# and HOLD#/RESET# pins to functions IO2
1834 * and IO3 hence enabling 4 (Quad) I/O lines.
1836 * Return: 0 on success, -errno otherwise.
1838 static int spi_nor_parse_bfpt(struct spi_nor *nor,
1839 const struct sfdp_parameter_header *bfpt_header,
1840 struct spi_nor_flash_parameter *params)
1842 struct mtd_info *mtd = &nor->mtd;
1843 struct sfdp_bfpt bfpt;
1849 /* JESD216 Basic Flash Parameter Table length is at least 9 DWORDs. */
1850 if (bfpt_header->length < BFPT_DWORD_MAX_JESD216)
1853 /* Read the Basic Flash Parameter Table. */
1854 len = min_t(size_t, sizeof(bfpt),
1855 bfpt_header->length * sizeof(u32));
1856 addr = SFDP_PARAM_HEADER_PTP(bfpt_header);
1857 memset(&bfpt, 0, sizeof(bfpt));
1858 err = spi_nor_read_sfdp(nor, addr, len, &bfpt);
1862 /* Fix endianness of the BFPT DWORDs. */
1863 for (i = 0; i < BFPT_DWORD_MAX; i++)
1864 bfpt.dwords[i] = le32_to_cpu(bfpt.dwords[i]);
1866 /* Number of address bytes. */
1867 switch (bfpt.dwords[BFPT_DWORD(1)] & BFPT_DWORD1_ADDRESS_BYTES_MASK) {
1868 case BFPT_DWORD1_ADDRESS_BYTES_3_ONLY:
1869 nor->addr_width = 3;
1872 case BFPT_DWORD1_ADDRESS_BYTES_4_ONLY:
1873 nor->addr_width = 4;
1880 /* Flash Memory Density (in bits). */
1881 params->size = bfpt.dwords[BFPT_DWORD(2)];
1882 if (params->size & BIT(31)) {
1883 params->size &= ~BIT(31);
1886 * Prevent overflows on params->size. Anyway, a NOR of 2^64
1887 * bits is unlikely to exist so this error probably means
1888 * the BFPT we are reading is corrupted/wrong.
1890 if (params->size > 63)
1893 params->size = 1ULL << params->size;
1897 params->size >>= 3; /* Convert to bytes. */
1899 /* Fast Read settings. */
1900 for (i = 0; i < ARRAY_SIZE(sfdp_bfpt_reads); i++) {
1901 const struct sfdp_bfpt_read *rd = &sfdp_bfpt_reads[i];
1902 struct spi_nor_read_command *read;
1904 if (!(bfpt.dwords[rd->supported_dword] & rd->supported_bit)) {
1905 params->hwcaps.mask &= ~rd->hwcaps;
1909 params->hwcaps.mask |= rd->hwcaps;
1910 cmd = spi_nor_hwcaps_read2cmd(rd->hwcaps);
1911 read = ¶ms->reads[cmd];
1912 half = bfpt.dwords[rd->settings_dword] >> rd->settings_shift;
1913 spi_nor_set_read_settings_from_bfpt(read, half, rd->proto);
1916 /* Sector Erase settings. */
1917 for (i = 0; i < ARRAY_SIZE(sfdp_bfpt_erases); i++) {
1918 const struct sfdp_bfpt_erase *er = &sfdp_bfpt_erases[i];
1922 half = bfpt.dwords[er->dword] >> er->shift;
1923 erasesize = half & 0xff;
1925 /* erasesize == 0 means this Erase Type is not supported. */
1929 erasesize = 1U << erasesize;
1930 opcode = (half >> 8) & 0xff;
1931 #ifdef CONFIG_SPI_FLASH_USE_4K_SECTORS
1932 if (erasesize == SZ_4K) {
1933 nor->erase_opcode = opcode;
1934 mtd->erasesize = erasesize;
1938 if (!mtd->erasesize || mtd->erasesize < erasesize) {
1939 nor->erase_opcode = opcode;
1940 mtd->erasesize = erasesize;
1944 /* Stop here if not JESD216 rev A or later. */
1945 if (bfpt_header->length < BFPT_DWORD_MAX)
1948 /* Page size: this field specifies 'N' so the page size = 2^N bytes. */
1949 params->page_size = bfpt.dwords[BFPT_DWORD(11)];
1950 params->page_size &= BFPT_DWORD11_PAGE_SIZE_MASK;
1951 params->page_size >>= BFPT_DWORD11_PAGE_SIZE_SHIFT;
1952 params->page_size = 1U << params->page_size;
1954 /* Quad Enable Requirements. */
1955 switch (bfpt.dwords[BFPT_DWORD(15)] & BFPT_DWORD15_QER_MASK) {
1956 case BFPT_DWORD15_QER_NONE:
1957 params->quad_enable = NULL;
1959 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
1960 case BFPT_DWORD15_QER_SR2_BIT1_BUGGY:
1961 case BFPT_DWORD15_QER_SR2_BIT1_NO_RD:
1962 params->quad_enable = spansion_no_read_cr_quad_enable;
1965 #ifdef CONFIG_SPI_FLASH_MACRONIX
1966 case BFPT_DWORD15_QER_SR1_BIT6:
1967 params->quad_enable = macronix_quad_enable;
1970 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
1971 case BFPT_DWORD15_QER_SR2_BIT1:
1972 params->quad_enable = spansion_read_cr_quad_enable;
1983 * spi_nor_parse_microchip_sfdp() - parse the Microchip manufacturer specific
1985 * @nor: pointer to a 'struct spi_nor'.
1986 * @param_header: pointer to the SFDP parameter header.
1988 * Return: 0 on success, -errno otherwise.
1991 spi_nor_parse_microchip_sfdp(struct spi_nor *nor,
1992 const struct sfdp_parameter_header *param_header)
1998 size = param_header->length * sizeof(u32);
1999 addr = SFDP_PARAM_HEADER_PTP(param_header);
2001 nor->manufacturer_sfdp = devm_kmalloc(nor->dev, size, GFP_KERNEL);
2002 if (!nor->manufacturer_sfdp)
2005 ret = spi_nor_read_sfdp(nor, addr, size, nor->manufacturer_sfdp);
2011 * spi_nor_parse_sfdp() - parse the Serial Flash Discoverable Parameters.
2012 * @nor: pointer to a 'struct spi_nor'
2013 * @params: pointer to the 'struct spi_nor_flash_parameter' to be
2016 * The Serial Flash Discoverable Parameters are described by the JEDEC JESD216
2017 * specification. This is a standard which tends to supported by almost all
2018 * (Q)SPI memory manufacturers. Those hard-coded tables allow us to learn at
2019 * runtime the main parameters needed to perform basic SPI flash operations such
2020 * as Fast Read, Page Program or Sector Erase commands.
2022 * Return: 0 on success, -errno otherwise.
2024 static int spi_nor_parse_sfdp(struct spi_nor *nor,
2025 struct spi_nor_flash_parameter *params)
2027 const struct sfdp_parameter_header *param_header, *bfpt_header;
2028 struct sfdp_parameter_header *param_headers = NULL;
2029 struct sfdp_header header;
2033 /* Get the SFDP header. */
2034 err = spi_nor_read_sfdp(nor, 0, sizeof(header), &header);
2038 /* Check the SFDP header version. */
2039 if (le32_to_cpu(header.signature) != SFDP_SIGNATURE ||
2040 header.major != SFDP_JESD216_MAJOR)
2044 * Verify that the first and only mandatory parameter header is a
2045 * Basic Flash Parameter Table header as specified in JESD216.
2047 bfpt_header = &header.bfpt_header;
2048 if (SFDP_PARAM_HEADER_ID(bfpt_header) != SFDP_BFPT_ID ||
2049 bfpt_header->major != SFDP_JESD216_MAJOR)
2053 * Allocate memory then read all parameter headers with a single
2054 * Read SFDP command. These parameter headers will actually be parsed
2055 * twice: a first time to get the latest revision of the basic flash
2056 * parameter table, then a second time to handle the supported optional
2058 * Hence we read the parameter headers once for all to reduce the
2059 * processing time. Also we use kmalloc() instead of devm_kmalloc()
2060 * because we don't need to keep these parameter headers: the allocated
2061 * memory is always released with kfree() before exiting this function.
2064 psize = header.nph * sizeof(*param_headers);
2066 param_headers = kmalloc(psize, GFP_KERNEL);
2070 err = spi_nor_read_sfdp(nor, sizeof(header),
2071 psize, param_headers);
2074 "failed to read SFDP parameter headers\n");
2080 * Check other parameter headers to get the latest revision of
2081 * the basic flash parameter table.
2083 for (i = 0; i < header.nph; i++) {
2084 param_header = ¶m_headers[i];
2086 if (SFDP_PARAM_HEADER_ID(param_header) == SFDP_BFPT_ID &&
2087 param_header->major == SFDP_JESD216_MAJOR &&
2088 (param_header->minor > bfpt_header->minor ||
2089 (param_header->minor == bfpt_header->minor &&
2090 param_header->length > bfpt_header->length)))
2091 bfpt_header = param_header;
2094 err = spi_nor_parse_bfpt(nor, bfpt_header, params);
2098 /* Parse other parameter headers. */
2099 for (i = 0; i < header.nph; i++) {
2100 param_header = ¶m_headers[i];
2102 switch (SFDP_PARAM_HEADER_ID(param_header)) {
2103 case SFDP_SECTOR_MAP_ID:
2105 "non-uniform erase sector maps are not supported yet.\n");
2109 err = spi_nor_parse_microchip_sfdp(nor, param_header);
2118 "Failed to parse optional parameter table: %04x\n",
2119 SFDP_PARAM_HEADER_ID(param_header));
2121 * Let's not drop all information we extracted so far
2122 * if optional table parsers fail. In case of failing,
2123 * each optional parser is responsible to roll back to
2124 * the previously known spi_nor data.
2131 kfree(param_headers);
2135 static int spi_nor_parse_sfdp(struct spi_nor *nor,
2136 struct spi_nor_flash_parameter *params)
2140 #endif /* SPI_FLASH_SFDP_SUPPORT */
2142 static int spi_nor_init_params(struct spi_nor *nor,
2143 const struct flash_info *info,
2144 struct spi_nor_flash_parameter *params)
2146 /* Set legacy flash parameters as default. */
2147 memset(params, 0, sizeof(*params));
2149 /* Set SPI NOR sizes. */
2150 params->size = info->sector_size * info->n_sectors;
2151 params->page_size = info->page_size;
2153 /* (Fast) Read settings. */
2154 params->hwcaps.mask |= SNOR_HWCAPS_READ;
2155 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ],
2156 0, 0, SPINOR_OP_READ,
2159 if (!(info->flags & SPI_NOR_NO_FR)) {
2160 params->hwcaps.mask |= SNOR_HWCAPS_READ_FAST;
2161 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_FAST],
2162 0, 8, SPINOR_OP_READ_FAST,
2166 if (info->flags & SPI_NOR_DUAL_READ) {
2167 params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_2;
2168 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_2],
2169 0, 8, SPINOR_OP_READ_1_1_2,
2173 if (info->flags & SPI_NOR_QUAD_READ) {
2174 params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4;
2175 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_4],
2176 0, 8, SPINOR_OP_READ_1_1_4,
2180 if (info->flags & SPI_NOR_OCTAL_READ) {
2181 params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_8;
2182 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_8],
2183 0, 8, SPINOR_OP_READ_1_1_8,
2187 /* Page Program settings. */
2188 params->hwcaps.mask |= SNOR_HWCAPS_PP;
2189 spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP],
2190 SPINOR_OP_PP, SNOR_PROTO_1_1_1);
2192 if (info->flags & SPI_NOR_QUAD_READ) {
2193 params->hwcaps.mask |= SNOR_HWCAPS_PP_1_1_4;
2194 spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP_1_1_4],
2195 SPINOR_OP_PP_1_1_4, SNOR_PROTO_1_1_4);
2198 /* Select the procedure to set the Quad Enable bit. */
2199 if (params->hwcaps.mask & (SNOR_HWCAPS_READ_QUAD |
2200 SNOR_HWCAPS_PP_QUAD)) {
2201 switch (JEDEC_MFR(info)) {
2202 #ifdef CONFIG_SPI_FLASH_MACRONIX
2203 case SNOR_MFR_MACRONIX:
2204 params->quad_enable = macronix_quad_enable;
2208 case SNOR_MFR_MICRON:
2212 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
2213 /* Kept only for backward compatibility purpose. */
2214 params->quad_enable = spansion_read_cr_quad_enable;
2220 /* Override the parameters with data read from SFDP tables. */
2221 nor->addr_width = 0;
2222 nor->mtd.erasesize = 0;
2223 if ((info->flags & (SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)) &&
2224 !(info->flags & SPI_NOR_SKIP_SFDP)) {
2225 struct spi_nor_flash_parameter sfdp_params;
2227 memcpy(&sfdp_params, params, sizeof(sfdp_params));
2228 if (spi_nor_parse_sfdp(nor, &sfdp_params)) {
2229 nor->addr_width = 0;
2230 nor->mtd.erasesize = 0;
2232 memcpy(params, &sfdp_params, sizeof(*params));
2239 static int spi_nor_hwcaps2cmd(u32 hwcaps, const int table[][2], size_t size)
2243 for (i = 0; i < size; i++)
2244 if (table[i][0] == (int)hwcaps)
2250 static int spi_nor_hwcaps_read2cmd(u32 hwcaps)
2252 static const int hwcaps_read2cmd[][2] = {
2253 { SNOR_HWCAPS_READ, SNOR_CMD_READ },
2254 { SNOR_HWCAPS_READ_FAST, SNOR_CMD_READ_FAST },
2255 { SNOR_HWCAPS_READ_1_1_1_DTR, SNOR_CMD_READ_1_1_1_DTR },
2256 { SNOR_HWCAPS_READ_1_1_2, SNOR_CMD_READ_1_1_2 },
2257 { SNOR_HWCAPS_READ_1_2_2, SNOR_CMD_READ_1_2_2 },
2258 { SNOR_HWCAPS_READ_2_2_2, SNOR_CMD_READ_2_2_2 },
2259 { SNOR_HWCAPS_READ_1_2_2_DTR, SNOR_CMD_READ_1_2_2_DTR },
2260 { SNOR_HWCAPS_READ_1_1_4, SNOR_CMD_READ_1_1_4 },
2261 { SNOR_HWCAPS_READ_1_4_4, SNOR_CMD_READ_1_4_4 },
2262 { SNOR_HWCAPS_READ_4_4_4, SNOR_CMD_READ_4_4_4 },
2263 { SNOR_HWCAPS_READ_1_4_4_DTR, SNOR_CMD_READ_1_4_4_DTR },
2264 { SNOR_HWCAPS_READ_1_1_8, SNOR_CMD_READ_1_1_8 },
2265 { SNOR_HWCAPS_READ_1_8_8, SNOR_CMD_READ_1_8_8 },
2266 { SNOR_HWCAPS_READ_8_8_8, SNOR_CMD_READ_8_8_8 },
2267 { SNOR_HWCAPS_READ_1_8_8_DTR, SNOR_CMD_READ_1_8_8_DTR },
2270 return spi_nor_hwcaps2cmd(hwcaps, hwcaps_read2cmd,
2271 ARRAY_SIZE(hwcaps_read2cmd));
2274 static int spi_nor_hwcaps_pp2cmd(u32 hwcaps)
2276 static const int hwcaps_pp2cmd[][2] = {
2277 { SNOR_HWCAPS_PP, SNOR_CMD_PP },
2278 { SNOR_HWCAPS_PP_1_1_4, SNOR_CMD_PP_1_1_4 },
2279 { SNOR_HWCAPS_PP_1_4_4, SNOR_CMD_PP_1_4_4 },
2280 { SNOR_HWCAPS_PP_4_4_4, SNOR_CMD_PP_4_4_4 },
2281 { SNOR_HWCAPS_PP_1_1_8, SNOR_CMD_PP_1_1_8 },
2282 { SNOR_HWCAPS_PP_1_8_8, SNOR_CMD_PP_1_8_8 },
2283 { SNOR_HWCAPS_PP_8_8_8, SNOR_CMD_PP_8_8_8 },
2286 return spi_nor_hwcaps2cmd(hwcaps, hwcaps_pp2cmd,
2287 ARRAY_SIZE(hwcaps_pp2cmd));
2290 static int spi_nor_select_read(struct spi_nor *nor,
2291 const struct spi_nor_flash_parameter *params,
2294 int cmd, best_match = fls(shared_hwcaps & SNOR_HWCAPS_READ_MASK) - 1;
2295 const struct spi_nor_read_command *read;
2300 cmd = spi_nor_hwcaps_read2cmd(BIT(best_match));
2304 read = ¶ms->reads[cmd];
2305 nor->read_opcode = read->opcode;
2306 nor->read_proto = read->proto;
2309 * In the spi-nor framework, we don't need to make the difference
2310 * between mode clock cycles and wait state clock cycles.
2311 * Indeed, the value of the mode clock cycles is used by a QSPI
2312 * flash memory to know whether it should enter or leave its 0-4-4
2313 * (Continuous Read / XIP) mode.
2314 * eXecution In Place is out of the scope of the mtd sub-system.
2315 * Hence we choose to merge both mode and wait state clock cycles
2316 * into the so called dummy clock cycles.
2318 nor->read_dummy = read->num_mode_clocks + read->num_wait_states;
2322 static int spi_nor_select_pp(struct spi_nor *nor,
2323 const struct spi_nor_flash_parameter *params,
2326 int cmd, best_match = fls(shared_hwcaps & SNOR_HWCAPS_PP_MASK) - 1;
2327 const struct spi_nor_pp_command *pp;
2332 cmd = spi_nor_hwcaps_pp2cmd(BIT(best_match));
2336 pp = ¶ms->page_programs[cmd];
2337 nor->program_opcode = pp->opcode;
2338 nor->write_proto = pp->proto;
2342 static int spi_nor_select_erase(struct spi_nor *nor,
2343 const struct flash_info *info)
2345 struct mtd_info *mtd = &nor->mtd;
2347 /* Do nothing if already configured from SFDP. */
2351 #ifdef CONFIG_SPI_FLASH_USE_4K_SECTORS
2352 /* prefer "small sector" erase if possible */
2353 if (info->flags & SECT_4K) {
2354 nor->erase_opcode = SPINOR_OP_BE_4K;
2355 mtd->erasesize = 4096;
2356 } else if (info->flags & SECT_4K_PMC) {
2357 nor->erase_opcode = SPINOR_OP_BE_4K_PMC;
2358 mtd->erasesize = 4096;
2362 nor->erase_opcode = SPINOR_OP_SE;
2363 mtd->erasesize = info->sector_size;
2368 static int spi_nor_setup(struct spi_nor *nor, const struct flash_info *info,
2369 const struct spi_nor_flash_parameter *params,
2370 const struct spi_nor_hwcaps *hwcaps)
2372 u32 ignored_mask, shared_mask;
2373 bool enable_quad_io;
2377 * Keep only the hardware capabilities supported by both the SPI
2378 * controller and the SPI flash memory.
2380 shared_mask = hwcaps->mask & params->hwcaps.mask;
2382 /* SPI n-n-n protocols are not supported yet. */
2383 ignored_mask = (SNOR_HWCAPS_READ_2_2_2 |
2384 SNOR_HWCAPS_READ_4_4_4 |
2385 SNOR_HWCAPS_READ_8_8_8 |
2386 SNOR_HWCAPS_PP_4_4_4 |
2387 SNOR_HWCAPS_PP_8_8_8);
2388 if (shared_mask & ignored_mask) {
2390 "SPI n-n-n protocols are not supported yet.\n");
2391 shared_mask &= ~ignored_mask;
2394 /* Select the (Fast) Read command. */
2395 err = spi_nor_select_read(nor, params, shared_mask);
2398 "can't select read settings supported by both the SPI controller and memory.\n");
2402 /* Select the Page Program command. */
2403 err = spi_nor_select_pp(nor, params, shared_mask);
2406 "can't select write settings supported by both the SPI controller and memory.\n");
2410 /* Select the Sector Erase command. */
2411 err = spi_nor_select_erase(nor, info);
2414 "can't select erase settings supported by both the SPI controller and memory.\n");
2418 /* Enable Quad I/O if needed. */
2419 enable_quad_io = (spi_nor_get_protocol_width(nor->read_proto) == 4 ||
2420 spi_nor_get_protocol_width(nor->write_proto) == 4);
2421 if (enable_quad_io && params->quad_enable)
2422 nor->quad_enable = params->quad_enable;
2424 nor->quad_enable = NULL;
2429 static int spi_nor_init(struct spi_nor *nor)
2434 * Atmel, SST, Intel/Numonyx, and others serial NOR tend to power up
2435 * with the software protection bits set
2437 if (JEDEC_MFR(nor->info) == SNOR_MFR_ATMEL ||
2438 JEDEC_MFR(nor->info) == SNOR_MFR_INTEL ||
2439 JEDEC_MFR(nor->info) == SNOR_MFR_SST ||
2440 nor->info->flags & SPI_NOR_HAS_LOCK) {
2443 spi_nor_wait_till_ready(nor);
2446 if (nor->quad_enable) {
2447 err = nor->quad_enable(nor);
2449 dev_dbg(nor->dev, "quad mode not supported\n");
2454 if (nor->addr_width == 4 &&
2455 (JEDEC_MFR(nor->info) != SNOR_MFR_SPANSION) &&
2456 !(nor->info->flags & SPI_NOR_4B_OPCODES)) {
2458 * If the RESET# pin isn't hooked up properly, or the system
2459 * otherwise doesn't perform a reset command in the boot
2460 * sequence, it's impossible to 100% protect against unexpected
2461 * reboots (e.g., crashes). Warn the user (or hopefully, system
2462 * designer) that this is bad.
2464 if (nor->flags & SNOR_F_BROKEN_RESET)
2465 printf("enabling reset hack; may not recover from unexpected reboots\n");
2466 set_4byte(nor, nor->info, 1);
2472 int spi_nor_scan(struct spi_nor *nor)
2474 struct spi_nor_flash_parameter params;
2475 const struct flash_info *info = NULL;
2476 struct mtd_info *mtd = &nor->mtd;
2477 struct spi_nor_hwcaps hwcaps = {
2478 .mask = SNOR_HWCAPS_READ |
2479 SNOR_HWCAPS_READ_FAST |
2482 struct spi_slave *spi = nor->spi;
2485 /* Reset SPI protocol for all commands. */
2486 nor->reg_proto = SNOR_PROTO_1_1_1;
2487 nor->read_proto = SNOR_PROTO_1_1_1;
2488 nor->write_proto = SNOR_PROTO_1_1_1;
2489 nor->read = spi_nor_read_data;
2490 nor->write = spi_nor_write_data;
2491 nor->read_reg = spi_nor_read_reg;
2492 nor->write_reg = spi_nor_write_reg;
2494 if (spi->mode & SPI_RX_OCTAL) {
2495 hwcaps.mask |= SNOR_HWCAPS_READ_1_1_8;
2497 if (spi->mode & SPI_TX_OCTAL)
2498 hwcaps.mask |= (SNOR_HWCAPS_READ_1_8_8 |
2499 SNOR_HWCAPS_PP_1_1_8 |
2500 SNOR_HWCAPS_PP_1_8_8);
2501 } else if (spi->mode & SPI_RX_QUAD) {
2502 hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4;
2504 if (spi->mode & SPI_TX_QUAD)
2505 hwcaps.mask |= (SNOR_HWCAPS_READ_1_4_4 |
2506 SNOR_HWCAPS_PP_1_1_4 |
2507 SNOR_HWCAPS_PP_1_4_4);
2508 } else if (spi->mode & SPI_RX_DUAL) {
2509 hwcaps.mask |= SNOR_HWCAPS_READ_1_1_2;
2511 if (spi->mode & SPI_TX_DUAL)
2512 hwcaps.mask |= SNOR_HWCAPS_READ_1_2_2;
2515 info = spi_nor_read_id(nor);
2516 if (IS_ERR_OR_NULL(info))
2518 /* Parse the Serial Flash Discoverable Parameters table. */
2519 ret = spi_nor_init_params(nor, info, ¶ms);
2524 mtd->name = info->name;
2526 mtd->type = MTD_NORFLASH;
2528 mtd->flags = MTD_CAP_NORFLASH;
2529 mtd->size = params.size;
2530 mtd->_erase = spi_nor_erase;
2531 mtd->_read = spi_nor_read;
2533 #if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST)
2534 /* NOR protection support for STmicro/Micron chips and similar */
2535 if (JEDEC_MFR(info) == SNOR_MFR_ST ||
2536 JEDEC_MFR(info) == SNOR_MFR_MICRON ||
2537 JEDEC_MFR(info) == SNOR_MFR_SST ||
2538 info->flags & SPI_NOR_HAS_LOCK) {
2539 nor->flash_lock = stm_lock;
2540 nor->flash_unlock = stm_unlock;
2541 nor->flash_is_locked = stm_is_locked;
2545 #ifdef CONFIG_SPI_FLASH_SST
2547 * sst26 series block protection implementation differs from other
2550 if (info->flags & SPI_NOR_HAS_SST26LOCK) {
2551 nor->flash_lock = sst26_lock;
2552 nor->flash_unlock = sst26_unlock;
2553 nor->flash_is_locked = sst26_is_locked;
2556 /* sst nor chips use AAI word program */
2557 if (info->flags & SST_WRITE)
2558 mtd->_write = sst_write;
2561 mtd->_write = spi_nor_write;
2563 if (info->flags & USE_FSR)
2564 nor->flags |= SNOR_F_USE_FSR;
2565 if (info->flags & SPI_NOR_HAS_TB)
2566 nor->flags |= SNOR_F_HAS_SR_TB;
2567 if (info->flags & NO_CHIP_ERASE)
2568 nor->flags |= SNOR_F_NO_OP_CHIP_ERASE;
2569 if (info->flags & USE_CLSR)
2570 nor->flags |= SNOR_F_USE_CLSR;
2572 if (info->flags & SPI_NOR_NO_ERASE)
2573 mtd->flags |= MTD_NO_ERASE;
2575 nor->page_size = params.page_size;
2576 mtd->writebufsize = nor->page_size;
2578 /* Some devices cannot do fast-read, no matter what DT tells us */
2579 if ((info->flags & SPI_NOR_NO_FR) || (spi->mode & SPI_RX_SLOW))
2580 params.hwcaps.mask &= ~SNOR_HWCAPS_READ_FAST;
2583 * Configure the SPI memory:
2584 * - select op codes for (Fast) Read, Page Program and Sector Erase.
2585 * - set the number of dummy cycles (mode cycles + wait states).
2586 * - set the SPI protocols for register and memory accesses.
2587 * - set the Quad Enable bit if needed (required by SPI x-y-4 protos).
2589 ret = spi_nor_setup(nor, info, ¶ms, &hwcaps);
2593 if (nor->addr_width) {
2594 /* already configured from SFDP */
2595 } else if (info->addr_width) {
2596 nor->addr_width = info->addr_width;
2597 } else if (mtd->size > SZ_16M) {
2598 #ifndef CONFIG_SPI_FLASH_BAR
2599 /* enable 4-byte addressing if the device exceeds 16MiB */
2600 nor->addr_width = 4;
2601 if (JEDEC_MFR(info) == SNOR_MFR_SPANSION ||
2602 info->flags & SPI_NOR_4B_OPCODES)
2603 spi_nor_set_4byte_opcodes(nor, info);
2605 /* Configure the BAR - discover bank cmds and read current bank */
2606 nor->addr_width = 3;
2607 ret = read_bar(nor, info);
2612 nor->addr_width = 3;
2615 if (nor->addr_width > SPI_NOR_MAX_ADDR_WIDTH) {
2616 dev_dbg(nor->dev, "address width is too large: %u\n",
2621 /* Send all the required SPI flash commands to initialize device */
2623 ret = spi_nor_init(nor);
2627 nor->name = mtd->name;
2628 nor->size = mtd->size;
2629 nor->erase_size = mtd->erasesize;
2630 nor->sector_size = mtd->erasesize;
2632 #ifndef CONFIG_SPL_BUILD
2633 printf("SF: Detected %s with page size ", nor->name);
2634 print_size(nor->page_size, ", erase size ");
2635 print_size(nor->erase_size, ", total ");
2636 print_size(nor->size, "");
2643 /* U-Boot specific functions, need to extend MTD to support these */
2644 int spi_flash_cmd_get_sw_write_prot(struct spi_nor *nor)
2646 int sr = read_sr(nor);
2651 return (sr >> 2) & 7;