1 // SPDX-License-Identifier: GPL-2.0
3 * Based on m25p80.c, by Mike Lavender (mike@steroidmicros.com), with
4 * influence from lart.c (Abraham Van Der Merwe) and mtd_dataflash.c
6 * Copyright (C) 2005, Intec Automation Inc.
7 * Copyright (C) 2014, Freescale Semiconductor, Inc.
9 * Synced from Linux v4.19
13 #include <linux/err.h>
14 #include <linux/errno.h>
15 #include <linux/log2.h>
16 #include <linux/math64.h>
17 #include <linux/sizes.h>
19 #include <linux/mtd/mtd.h>
20 #include <linux/mtd/spi-nor.h>
24 #include "sf_internal.h"
26 /* Define max times to check status register before we give up. */
29 * For everything but full-chip erase; probably could be much smaller, but kept
30 * around for safety for now
33 #define HZ CONFIG_SYS_HZ
35 #define DEFAULT_READY_WAIT_JIFFIES (40UL * HZ)
37 static int spi_nor_read_write_reg(struct spi_nor *nor, struct spi_mem_op
40 if (op->data.dir == SPI_MEM_DATA_IN)
41 op->data.buf.in = buf;
43 op->data.buf.out = buf;
44 return spi_mem_exec_op(nor->spi, op);
47 static int spi_nor_read_reg(struct spi_nor *nor, u8 code, u8 *val, int len)
49 struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(code, 1),
52 SPI_MEM_OP_DATA_IN(len, NULL, 1));
55 ret = spi_nor_read_write_reg(nor, &op, val);
57 dev_dbg(&flash->spimem->spi->dev, "error %d reading %x\n", ret,
63 static int spi_nor_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
65 struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(opcode, 1),
68 SPI_MEM_OP_DATA_OUT(len, NULL, 1));
70 return spi_nor_read_write_reg(nor, &op, buf);
73 static ssize_t spi_nor_read_data(struct spi_nor *nor, loff_t from, size_t len,
76 struct spi_mem_op op =
77 SPI_MEM_OP(SPI_MEM_OP_CMD(nor->read_opcode, 1),
78 SPI_MEM_OP_ADDR(nor->addr_width, from, 1),
79 SPI_MEM_OP_DUMMY(nor->read_dummy, 1),
80 SPI_MEM_OP_DATA_IN(len, buf, 1));
81 size_t remaining = len;
84 /* get transfer protocols. */
85 op.cmd.buswidth = spi_nor_get_protocol_inst_nbits(nor->read_proto);
86 op.addr.buswidth = spi_nor_get_protocol_addr_nbits(nor->read_proto);
87 op.dummy.buswidth = op.addr.buswidth;
88 op.data.buswidth = spi_nor_get_protocol_data_nbits(nor->read_proto);
90 /* convert the dummy cycles to the number of bytes */
91 op.dummy.nbytes = (nor->read_dummy * op.dummy.buswidth) / 8;
94 op.data.nbytes = remaining < UINT_MAX ? remaining : UINT_MAX;
95 ret = spi_mem_adjust_op_size(nor->spi, &op);
99 ret = spi_mem_exec_op(nor->spi, &op);
103 op.addr.val += op.data.nbytes;
104 remaining -= op.data.nbytes;
105 op.data.buf.in += op.data.nbytes;
111 static ssize_t spi_nor_write_data(struct spi_nor *nor, loff_t to, size_t len,
114 struct spi_mem_op op =
115 SPI_MEM_OP(SPI_MEM_OP_CMD(nor->program_opcode, 1),
116 SPI_MEM_OP_ADDR(nor->addr_width, to, 1),
118 SPI_MEM_OP_DATA_OUT(len, buf, 1));
121 /* get transfer protocols. */
122 op.cmd.buswidth = spi_nor_get_protocol_inst_nbits(nor->write_proto);
123 op.addr.buswidth = spi_nor_get_protocol_addr_nbits(nor->write_proto);
124 op.data.buswidth = spi_nor_get_protocol_data_nbits(nor->write_proto);
126 if (nor->program_opcode == SPINOR_OP_AAI_WP && nor->sst_write_second)
129 ret = spi_mem_adjust_op_size(nor->spi, &op);
132 op.data.nbytes = len < op.data.nbytes ? len : op.data.nbytes;
134 ret = spi_mem_exec_op(nor->spi, &op);
138 return op.data.nbytes;
142 * Read the status register, returning its value in the location
143 * Return the status register value.
144 * Returns negative if error occurred.
146 static int read_sr(struct spi_nor *nor)
151 ret = nor->read_reg(nor, SPINOR_OP_RDSR, &val, 1);
153 pr_debug("error %d reading SR\n", (int)ret);
161 * Read the flag status register, returning its value in the location
162 * Return the status register value.
163 * Returns negative if error occurred.
165 static int read_fsr(struct spi_nor *nor)
170 ret = nor->read_reg(nor, SPINOR_OP_RDFSR, &val, 1);
172 pr_debug("error %d reading FSR\n", ret);
180 * Read configuration register, returning its value in the
181 * location. Return the configuration register value.
182 * Returns negative if error occurred.
184 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
185 static int read_cr(struct spi_nor *nor)
190 ret = nor->read_reg(nor, SPINOR_OP_RDCR, &val, 1);
192 dev_dbg(nor->dev, "error %d reading CR\n", ret);
201 * Write status register 1 byte
202 * Returns negative if error occurred.
204 static int write_sr(struct spi_nor *nor, u8 val)
206 nor->cmd_buf[0] = val;
207 return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1);
211 * Set write enable latch with Write Enable command.
212 * Returns negative if error occurred.
214 static int write_enable(struct spi_nor *nor)
216 return nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0);
220 * Send write disable instruction to the chip.
222 static int write_disable(struct spi_nor *nor)
224 return nor->write_reg(nor, SPINOR_OP_WRDI, NULL, 0);
227 static struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd)
232 #ifndef CONFIG_SPI_FLASH_BAR
233 static u8 spi_nor_convert_opcode(u8 opcode, const u8 table[][2], size_t size)
237 for (i = 0; i < size; i++)
238 if (table[i][0] == opcode)
241 /* No conversion found, keep input op code. */
245 static u8 spi_nor_convert_3to4_read(u8 opcode)
247 static const u8 spi_nor_3to4_read[][2] = {
248 { SPINOR_OP_READ, SPINOR_OP_READ_4B },
249 { SPINOR_OP_READ_FAST, SPINOR_OP_READ_FAST_4B },
250 { SPINOR_OP_READ_1_1_2, SPINOR_OP_READ_1_1_2_4B },
251 { SPINOR_OP_READ_1_2_2, SPINOR_OP_READ_1_2_2_4B },
252 { SPINOR_OP_READ_1_1_4, SPINOR_OP_READ_1_1_4_4B },
253 { SPINOR_OP_READ_1_4_4, SPINOR_OP_READ_1_4_4_4B },
255 { SPINOR_OP_READ_1_1_1_DTR, SPINOR_OP_READ_1_1_1_DTR_4B },
256 { SPINOR_OP_READ_1_2_2_DTR, SPINOR_OP_READ_1_2_2_DTR_4B },
257 { SPINOR_OP_READ_1_4_4_DTR, SPINOR_OP_READ_1_4_4_DTR_4B },
260 return spi_nor_convert_opcode(opcode, spi_nor_3to4_read,
261 ARRAY_SIZE(spi_nor_3to4_read));
264 static u8 spi_nor_convert_3to4_program(u8 opcode)
266 static const u8 spi_nor_3to4_program[][2] = {
267 { SPINOR_OP_PP, SPINOR_OP_PP_4B },
268 { SPINOR_OP_PP_1_1_4, SPINOR_OP_PP_1_1_4_4B },
269 { SPINOR_OP_PP_1_4_4, SPINOR_OP_PP_1_4_4_4B },
272 return spi_nor_convert_opcode(opcode, spi_nor_3to4_program,
273 ARRAY_SIZE(spi_nor_3to4_program));
276 static u8 spi_nor_convert_3to4_erase(u8 opcode)
278 static const u8 spi_nor_3to4_erase[][2] = {
279 { SPINOR_OP_BE_4K, SPINOR_OP_BE_4K_4B },
280 { SPINOR_OP_BE_32K, SPINOR_OP_BE_32K_4B },
281 { SPINOR_OP_SE, SPINOR_OP_SE_4B },
284 return spi_nor_convert_opcode(opcode, spi_nor_3to4_erase,
285 ARRAY_SIZE(spi_nor_3to4_erase));
288 static void spi_nor_set_4byte_opcodes(struct spi_nor *nor,
289 const struct flash_info *info)
291 /* Do some manufacturer fixups first */
292 switch (JEDEC_MFR(info)) {
293 case SNOR_MFR_SPANSION:
294 /* No small sector erase for 4-byte command set */
295 nor->erase_opcode = SPINOR_OP_SE;
296 nor->mtd.erasesize = info->sector_size;
303 nor->read_opcode = spi_nor_convert_3to4_read(nor->read_opcode);
304 nor->program_opcode = spi_nor_convert_3to4_program(nor->program_opcode);
305 nor->erase_opcode = spi_nor_convert_3to4_erase(nor->erase_opcode);
307 #endif /* !CONFIG_SPI_FLASH_BAR */
309 /* Enable/disable 4-byte addressing mode. */
310 static int set_4byte(struct spi_nor *nor, const struct flash_info *info,
314 bool need_wren = false;
317 switch (JEDEC_MFR(info)) {
319 case SNOR_MFR_MICRON:
320 /* Some Micron need WREN command; all will accept it */
322 case SNOR_MFR_MACRONIX:
323 case SNOR_MFR_WINBOND:
327 cmd = enable ? SPINOR_OP_EN4B : SPINOR_OP_EX4B;
328 status = nor->write_reg(nor, cmd, NULL, 0);
332 if (!status && !enable &&
333 JEDEC_MFR(info) == SNOR_MFR_WINBOND) {
335 * On Winbond W25Q256FV, leaving 4byte mode causes
336 * the Extended Address Register to be set to 1, so all
337 * 3-byte-address reads come from the second 16M.
338 * We must clear the register to enable normal behavior.
342 nor->write_reg(nor, SPINOR_OP_WREAR, nor->cmd_buf, 1);
349 nor->cmd_buf[0] = enable << 7;
350 return nor->write_reg(nor, SPINOR_OP_BRWR, nor->cmd_buf, 1);
354 static int spi_nor_sr_ready(struct spi_nor *nor)
356 int sr = read_sr(nor);
361 if (nor->flags & SNOR_F_USE_CLSR && sr & (SR_E_ERR | SR_P_ERR)) {
363 dev_dbg(nor->dev, "Erase Error occurred\n");
365 dev_dbg(nor->dev, "Programming Error occurred\n");
367 nor->write_reg(nor, SPINOR_OP_CLSR, NULL, 0);
371 return !(sr & SR_WIP);
374 static int spi_nor_fsr_ready(struct spi_nor *nor)
376 int fsr = read_fsr(nor);
381 if (fsr & (FSR_E_ERR | FSR_P_ERR)) {
383 dev_err(nor->dev, "Erase operation failed.\n");
385 dev_err(nor->dev, "Program operation failed.\n");
387 if (fsr & FSR_PT_ERR)
389 "Attempted to modify a protected sector.\n");
391 nor->write_reg(nor, SPINOR_OP_CLFSR, NULL, 0);
395 return fsr & FSR_READY;
398 static int spi_nor_ready(struct spi_nor *nor)
402 sr = spi_nor_sr_ready(nor);
405 fsr = nor->flags & SNOR_F_USE_FSR ? spi_nor_fsr_ready(nor) : 1;
412 * Service routine to read status register until ready, or timeout occurs.
413 * Returns non-zero if error.
415 static int spi_nor_wait_till_ready_with_timeout(struct spi_nor *nor,
416 unsigned long timeout)
418 unsigned long timebase;
421 timebase = get_timer(0);
423 while (get_timer(timebase) < timeout) {
424 ret = spi_nor_ready(nor);
431 dev_err(nor->dev, "flash operation timed out\n");
436 static int spi_nor_wait_till_ready(struct spi_nor *nor)
438 return spi_nor_wait_till_ready_with_timeout(nor,
439 DEFAULT_READY_WAIT_JIFFIES);
442 #ifdef CONFIG_SPI_FLASH_BAR
444 * This "clean_bar" is necessary in a situation when one was accessing
445 * spi flash memory > 16 MiB by using Bank Address Register's BA24 bit.
447 * After it the BA24 bit shall be cleared to allow access to correct
448 * memory region after SW reset (by calling "reset" command).
450 * Otherwise, the BA24 bit may be left set and then after reset, the
451 * ROM would read/write/erase SPL from 16 MiB * bank_sel address.
453 static int clean_bar(struct spi_nor *nor)
455 u8 cmd, bank_sel = 0;
457 if (nor->bank_curr == 0)
459 cmd = nor->bank_write_cmd;
463 return nor->write_reg(nor, cmd, &bank_sel, 1);
466 static int write_bar(struct spi_nor *nor, u32 offset)
471 bank_sel = offset / SZ_16M;
472 if (bank_sel == nor->bank_curr)
475 cmd = nor->bank_write_cmd;
477 ret = nor->write_reg(nor, cmd, &bank_sel, 1);
479 debug("SF: fail to write bank register\n");
484 nor->bank_curr = bank_sel;
485 return nor->bank_curr;
488 static int read_bar(struct spi_nor *nor, const struct flash_info *info)
493 switch (JEDEC_MFR(info)) {
494 case SNOR_MFR_SPANSION:
495 nor->bank_read_cmd = SPINOR_OP_BRRD;
496 nor->bank_write_cmd = SPINOR_OP_BRWR;
499 nor->bank_read_cmd = SPINOR_OP_RDEAR;
500 nor->bank_write_cmd = SPINOR_OP_WREAR;
503 ret = nor->read_reg(nor, nor->bank_read_cmd,
506 debug("SF: fail to read bank addr register\n");
509 nor->bank_curr = curr_bank;
516 * Initiate the erasure of a single sector
518 static int spi_nor_erase_sector(struct spi_nor *nor, u32 addr)
520 struct spi_mem_op op =
521 SPI_MEM_OP(SPI_MEM_OP_CMD(nor->erase_opcode, 1),
522 SPI_MEM_OP_ADDR(nor->addr_width, addr, 1),
527 return nor->erase(nor, addr);
530 * Default implementation, if driver doesn't have a specialized HW
533 return spi_mem_exec_op(nor->spi, &op);
537 * Erase an address range on the nor chip. The address range may extend
538 * one or more erase sectors. Return an error is there is a problem erasing.
540 static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
542 struct spi_nor *nor = mtd_to_spi_nor(mtd);
546 dev_dbg(nor->dev, "at 0x%llx, len %lld\n", (long long)instr->addr,
547 (long long)instr->len);
552 div_u64_rem(instr->len, mtd->erasesize, &rem);
560 #ifdef CONFIG_SPI_FLASH_BAR
561 ret = write_bar(nor, addr);
567 ret = spi_nor_erase_sector(nor, addr);
571 addr += mtd->erasesize;
572 len -= mtd->erasesize;
574 ret = spi_nor_wait_till_ready(nor);
580 #ifdef CONFIG_SPI_FLASH_BAR
581 ret = clean_bar(nor);
588 #if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST)
589 /* Write status register and ensure bits in mask match written values */
590 static int write_sr_and_check(struct spi_nor *nor, u8 status_new, u8 mask)
595 ret = write_sr(nor, status_new);
599 ret = spi_nor_wait_till_ready(nor);
607 return ((ret & mask) != (status_new & mask)) ? -EIO : 0;
610 static void stm_get_locked_range(struct spi_nor *nor, u8 sr, loff_t *ofs,
613 struct mtd_info *mtd = &nor->mtd;
614 u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
615 int shift = ffs(mask) - 1;
623 pow = ((sr & mask) ^ mask) >> shift;
624 *len = mtd->size >> pow;
625 if (nor->flags & SNOR_F_HAS_SR_TB && sr & SR_TB)
628 *ofs = mtd->size - *len;
633 * Return 1 if the entire region is locked (if @locked is true) or unlocked (if
634 * @locked is false); 0 otherwise
636 static int stm_check_lock_status_sr(struct spi_nor *nor, loff_t ofs, u64 len,
645 stm_get_locked_range(nor, sr, &lock_offs, &lock_len);
648 /* Requested range is a sub-range of locked range */
649 return (ofs + len <= lock_offs + lock_len) && (ofs >= lock_offs);
651 /* Requested range does not overlap with locked range */
652 return (ofs >= lock_offs + lock_len) || (ofs + len <= lock_offs);
655 static int stm_is_locked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len,
658 return stm_check_lock_status_sr(nor, ofs, len, sr, true);
661 static int stm_is_unlocked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len,
664 return stm_check_lock_status_sr(nor, ofs, len, sr, false);
668 * Lock a region of the flash. Compatible with ST Micro and similar flash.
669 * Supports the block protection bits BP{0,1,2} in the status register
670 * (SR). Does not support these features found in newer SR bitfields:
671 * - SEC: sector/block protect - only handle SEC=0 (block protect)
672 * - CMP: complement protect - only support CMP=0 (range is not complemented)
674 * Support for the following is provided conditionally for some flash:
675 * - TB: top/bottom protect
677 * Sample table portion for 8MB flash (Winbond w25q64fw):
679 * SEC | TB | BP2 | BP1 | BP0 | Prot Length | Protected Portion
680 * --------------------------------------------------------------------------
681 * X | X | 0 | 0 | 0 | NONE | NONE
682 * 0 | 0 | 0 | 0 | 1 | 128 KB | Upper 1/64
683 * 0 | 0 | 0 | 1 | 0 | 256 KB | Upper 1/32
684 * 0 | 0 | 0 | 1 | 1 | 512 KB | Upper 1/16
685 * 0 | 0 | 1 | 0 | 0 | 1 MB | Upper 1/8
686 * 0 | 0 | 1 | 0 | 1 | 2 MB | Upper 1/4
687 * 0 | 0 | 1 | 1 | 0 | 4 MB | Upper 1/2
688 * X | X | 1 | 1 | 1 | 8 MB | ALL
689 * ------|-------|-------|-------|-------|---------------|-------------------
690 * 0 | 1 | 0 | 0 | 1 | 128 KB | Lower 1/64
691 * 0 | 1 | 0 | 1 | 0 | 256 KB | Lower 1/32
692 * 0 | 1 | 0 | 1 | 1 | 512 KB | Lower 1/16
693 * 0 | 1 | 1 | 0 | 0 | 1 MB | Lower 1/8
694 * 0 | 1 | 1 | 0 | 1 | 2 MB | Lower 1/4
695 * 0 | 1 | 1 | 1 | 0 | 4 MB | Lower 1/2
697 * Returns negative on errors, 0 on success.
699 static int stm_lock(struct spi_nor *nor, loff_t ofs, uint64_t len)
701 struct mtd_info *mtd = &nor->mtd;
702 int status_old, status_new;
703 u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
704 u8 shift = ffs(mask) - 1, pow, val;
706 bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB;
709 status_old = read_sr(nor);
713 /* If nothing in our range is unlocked, we don't need to do anything */
714 if (stm_is_locked_sr(nor, ofs, len, status_old))
717 /* If anything below us is unlocked, we can't use 'bottom' protection */
718 if (!stm_is_locked_sr(nor, 0, ofs, status_old))
719 can_be_bottom = false;
721 /* If anything above us is unlocked, we can't use 'top' protection */
722 if (!stm_is_locked_sr(nor, ofs + len, mtd->size - (ofs + len),
726 if (!can_be_bottom && !can_be_top)
729 /* Prefer top, if both are valid */
730 use_top = can_be_top;
732 /* lock_len: length of region that should end up locked */
734 lock_len = mtd->size - ofs;
736 lock_len = ofs + len;
739 * Need smallest pow such that:
741 * 1 / (2^pow) <= (len / size)
743 * so (assuming power-of-2 size) we do:
745 * pow = ceil(log2(size / len)) = log2(size) - floor(log2(len))
747 pow = ilog2(mtd->size) - ilog2(lock_len);
748 val = mask - (pow << shift);
751 /* Don't "lock" with no region! */
755 status_new = (status_old & ~mask & ~SR_TB) | val;
757 /* Disallow further writes if WP pin is asserted */
758 status_new |= SR_SRWD;
763 /* Don't bother if they're the same */
764 if (status_new == status_old)
767 /* Only modify protection if it will not unlock other areas */
768 if ((status_new & mask) < (status_old & mask))
771 return write_sr_and_check(nor, status_new, mask);
775 * Unlock a region of the flash. See stm_lock() for more info
777 * Returns negative on errors, 0 on success.
779 static int stm_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len)
781 struct mtd_info *mtd = &nor->mtd;
782 int status_old, status_new;
783 u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
784 u8 shift = ffs(mask) - 1, pow, val;
786 bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB;
789 status_old = read_sr(nor);
793 /* If nothing in our range is locked, we don't need to do anything */
794 if (stm_is_unlocked_sr(nor, ofs, len, status_old))
797 /* If anything below us is locked, we can't use 'top' protection */
798 if (!stm_is_unlocked_sr(nor, 0, ofs, status_old))
801 /* If anything above us is locked, we can't use 'bottom' protection */
802 if (!stm_is_unlocked_sr(nor, ofs + len, mtd->size - (ofs + len),
804 can_be_bottom = false;
806 if (!can_be_bottom && !can_be_top)
809 /* Prefer top, if both are valid */
810 use_top = can_be_top;
812 /* lock_len: length of region that should remain locked */
814 lock_len = mtd->size - (ofs + len);
819 * Need largest pow such that:
821 * 1 / (2^pow) >= (len / size)
823 * so (assuming power-of-2 size) we do:
825 * pow = floor(log2(size / len)) = log2(size) - ceil(log2(len))
827 pow = ilog2(mtd->size) - order_base_2(lock_len);
829 val = 0; /* fully unlocked */
831 val = mask - (pow << shift);
832 /* Some power-of-two sizes are not supported */
837 status_new = (status_old & ~mask & ~SR_TB) | val;
839 /* Don't protect status register if we're fully unlocked */
841 status_new &= ~SR_SRWD;
846 /* Don't bother if they're the same */
847 if (status_new == status_old)
850 /* Only modify protection if it will not lock other areas */
851 if ((status_new & mask) > (status_old & mask))
854 return write_sr_and_check(nor, status_new, mask);
858 * Check if a region of the flash is (completely) locked. See stm_lock() for
861 * Returns 1 if entire region is locked, 0 if any portion is unlocked, and
862 * negative on errors.
864 static int stm_is_locked(struct spi_nor *nor, loff_t ofs, uint64_t len)
868 status = read_sr(nor);
872 return stm_is_locked_sr(nor, ofs, len, status);
874 #endif /* CONFIG_SPI_FLASH_STMICRO */
876 static const struct flash_info *spi_nor_read_id(struct spi_nor *nor)
879 u8 id[SPI_NOR_MAX_ID_LEN];
880 const struct flash_info *info;
882 tmp = nor->read_reg(nor, SPINOR_OP_RDID, id, SPI_NOR_MAX_ID_LEN);
884 dev_dbg(nor->dev, "error %d reading JEDEC ID\n", tmp);
889 for (; info->name; info++) {
891 if (!memcmp(info->id, id, info->id_len))
896 dev_err(nor->dev, "unrecognized JEDEC id bytes: %02x, %02x, %02x\n",
897 id[0], id[1], id[2]);
898 return ERR_PTR(-ENODEV);
901 static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len,
902 size_t *retlen, u_char *buf)
904 struct spi_nor *nor = mtd_to_spi_nor(mtd);
907 dev_dbg(nor->dev, "from 0x%08x, len %zd\n", (u32)from, len);
911 size_t read_len = len;
913 #ifdef CONFIG_SPI_FLASH_BAR
916 ret = write_bar(nor, addr);
919 remain_len = (SZ_16M * (nor->bank_curr + 1)) - addr;
921 if (len < remain_len)
924 read_len = remain_len;
927 ret = nor->read(nor, addr, read_len, buf);
929 /* We shouldn't see 0-length reads */
944 #ifdef CONFIG_SPI_FLASH_BAR
945 ret = clean_bar(nor);
950 #ifdef CONFIG_SPI_FLASH_SST
952 * sst26 flash series has its own block protection implementation:
953 * 4x - 8 KByte blocks - read & write protection bits - upper addresses
954 * 1x - 32 KByte blocks - write protection bits
955 * rest - 64 KByte blocks - write protection bits
956 * 1x - 32 KByte blocks - write protection bits
957 * 4x - 8 KByte blocks - read & write protection bits - lower addresses
959 * We'll support only per 64k lock/unlock so lower and upper 64 KByte region
960 * will be treated as single block.
962 #define SST26_BPR_8K_NUM 4
963 #define SST26_MAX_BPR_REG_LEN (18 + 1)
964 #define SST26_BOUND_REG_SIZE ((32 + SST26_BPR_8K_NUM * 8) * SZ_1K)
972 static bool sst26_process_bpr(u32 bpr_size, u8 *cmd, u32 bit, enum lock_ctl ctl)
976 cmd[bpr_size - (bit / 8) - 1] |= BIT(bit % 8);
978 case SST26_CTL_UNLOCK:
979 cmd[bpr_size - (bit / 8) - 1] &= ~BIT(bit % 8);
981 case SST26_CTL_CHECK:
982 return !!(cmd[bpr_size - (bit / 8) - 1] & BIT(bit % 8));
989 * Lock, unlock or check lock status of the flash region of the flash (depending
990 * on the lock_ctl value)
992 static int sst26_lock_ctl(struct spi_nor *nor, loff_t ofs, uint64_t len, enum lock_ctl ctl)
994 struct mtd_info *mtd = &nor->mtd;
995 u32 i, bpr_ptr, rptr_64k, lptr_64k, bpr_size;
996 bool lower_64k = false, upper_64k = false;
997 u8 bpr_buff[SST26_MAX_BPR_REG_LEN] = {};
1000 /* Check length and offset for 64k alignment */
1001 if ((ofs & (SZ_64K - 1)) || (len & (SZ_64K - 1))) {
1002 dev_err(nor->dev, "length or offset is not 64KiB allighned\n");
1006 if (ofs + len > mtd->size) {
1007 dev_err(nor->dev, "range is more than device size: %#llx + %#llx > %#llx\n",
1008 ofs, len, mtd->size);
1012 /* SST26 family has only 16 Mbit, 32 Mbit and 64 Mbit IC */
1013 if (mtd->size != SZ_2M &&
1014 mtd->size != SZ_4M &&
1018 bpr_size = 2 + (mtd->size / SZ_64K / 8);
1020 ret = nor->read_reg(nor, SPINOR_OP_READ_BPR, bpr_buff, bpr_size);
1022 dev_err(nor->dev, "fail to read block-protection register\n");
1026 rptr_64k = min_t(u32, ofs + len, mtd->size - SST26_BOUND_REG_SIZE);
1027 lptr_64k = max_t(u32, ofs, SST26_BOUND_REG_SIZE);
1029 upper_64k = ((ofs + len) > (mtd->size - SST26_BOUND_REG_SIZE));
1030 lower_64k = (ofs < SST26_BOUND_REG_SIZE);
1032 /* Lower bits in block-protection register are about 64k region */
1033 bpr_ptr = lptr_64k / SZ_64K - 1;
1035 /* Process 64K blocks region */
1036 while (lptr_64k < rptr_64k) {
1037 if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl))
1044 /* 32K and 8K region bits in BPR are after 64k region bits */
1045 bpr_ptr = (mtd->size - 2 * SST26_BOUND_REG_SIZE) / SZ_64K;
1047 /* Process lower 32K block region */
1049 if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl))
1054 /* Process upper 32K block region */
1056 if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl))
1061 /* Process lower 8K block regions */
1062 for (i = 0; i < SST26_BPR_8K_NUM; i++) {
1064 if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl))
1067 /* In 8K area BPR has both read and write protection bits */
1071 /* Process upper 8K block regions */
1072 for (i = 0; i < SST26_BPR_8K_NUM; i++) {
1074 if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl))
1077 /* In 8K area BPR has both read and write protection bits */
1081 /* If we check region status we don't need to write BPR back */
1082 if (ctl == SST26_CTL_CHECK)
1085 ret = nor->write_reg(nor, SPINOR_OP_WRITE_BPR, bpr_buff, bpr_size);
1087 dev_err(nor->dev, "fail to write block-protection register\n");
1094 static int sst26_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len)
1096 return sst26_lock_ctl(nor, ofs, len, SST26_CTL_UNLOCK);
1099 static int sst26_lock(struct spi_nor *nor, loff_t ofs, uint64_t len)
1101 return sst26_lock_ctl(nor, ofs, len, SST26_CTL_LOCK);
1105 * Returns EACCES (positive value) if region is locked, 0 if region is unlocked,
1106 * and negative on errors.
1108 static int sst26_is_locked(struct spi_nor *nor, loff_t ofs, uint64_t len)
1111 * is_locked function is used for check before reading or erasing flash
1112 * region, so offset and length might be not 64k allighned, so adjust
1113 * them to be 64k allighned as sst26_lock_ctl works only with 64k
1114 * allighned regions.
1116 ofs -= ofs & (SZ_64K - 1);
1117 len = len & (SZ_64K - 1) ? (len & ~(SZ_64K - 1)) + SZ_64K : len;
1119 return sst26_lock_ctl(nor, ofs, len, SST26_CTL_CHECK);
1122 static int sst_write_byteprogram(struct spi_nor *nor, loff_t to, size_t len,
1123 size_t *retlen, const u_char *buf)
1128 for (actual = 0; actual < len; actual++) {
1129 nor->program_opcode = SPINOR_OP_BP;
1132 /* write one byte. */
1133 ret = nor->write(nor, to, 1, buf + actual);
1136 ret = spi_nor_wait_till_ready(nor);
1147 static int sst_write(struct mtd_info *mtd, loff_t to, size_t len,
1148 size_t *retlen, const u_char *buf)
1150 struct spi_nor *nor = mtd_to_spi_nor(mtd);
1151 struct spi_slave *spi = nor->spi;
1155 dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len);
1156 if (spi->mode & SPI_TX_BYTE)
1157 return sst_write_byteprogram(nor, to, len, retlen, buf);
1161 nor->sst_write_second = false;
1164 /* Start write from odd address. */
1166 nor->program_opcode = SPINOR_OP_BP;
1168 /* write one byte. */
1169 ret = nor->write(nor, to, 1, buf);
1172 ret = spi_nor_wait_till_ready(nor);
1178 /* Write out most of the data here. */
1179 for (; actual < len - 1; actual += 2) {
1180 nor->program_opcode = SPINOR_OP_AAI_WP;
1182 /* write two bytes. */
1183 ret = nor->write(nor, to, 2, buf + actual);
1186 ret = spi_nor_wait_till_ready(nor);
1190 nor->sst_write_second = true;
1192 nor->sst_write_second = false;
1195 ret = spi_nor_wait_till_ready(nor);
1199 /* Write out trailing byte if it exists. */
1200 if (actual != len) {
1203 nor->program_opcode = SPINOR_OP_BP;
1204 ret = nor->write(nor, to, 1, buf + actual);
1207 ret = spi_nor_wait_till_ready(nor);
1219 * Write an address range to the nor chip. Data must be written in
1220 * FLASH_PAGESIZE chunks. The address range may be any size provided
1221 * it is within the physical boundaries.
1223 static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len,
1224 size_t *retlen, const u_char *buf)
1226 struct spi_nor *nor = mtd_to_spi_nor(mtd);
1227 size_t page_offset, page_remain, i;
1230 dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len);
1235 for (i = 0; i < len; ) {
1237 loff_t addr = to + i;
1240 * If page_size is a power of two, the offset can be quickly
1241 * calculated with an AND operation. On the other cases we
1242 * need to do a modulus operation (more expensive).
1243 * Power of two numbers have only one bit set and we can use
1244 * the instruction hweight32 to detect if we need to do a
1245 * modulus (do_div()) or not.
1247 if (hweight32(nor->page_size) == 1) {
1248 page_offset = addr & (nor->page_size - 1);
1252 page_offset = do_div(aux, nor->page_size);
1254 /* the size of data remaining on the first page */
1255 page_remain = min_t(size_t,
1256 nor->page_size - page_offset, len - i);
1258 #ifdef CONFIG_SPI_FLASH_BAR
1259 ret = write_bar(nor, addr);
1264 ret = nor->write(nor, addr, page_remain, buf + i);
1269 ret = spi_nor_wait_till_ready(nor);
1277 #ifdef CONFIG_SPI_FLASH_BAR
1278 ret = clean_bar(nor);
1283 #ifdef CONFIG_SPI_FLASH_MACRONIX
1285 * macronix_quad_enable() - set QE bit in Status Register.
1286 * @nor: pointer to a 'struct spi_nor'
1288 * Set the Quad Enable (QE) bit in the Status Register.
1290 * bit 6 of the Status Register is the QE bit for Macronix like QSPI memories.
1292 * Return: 0 on success, -errno otherwise.
1294 static int macronix_quad_enable(struct spi_nor *nor)
1301 if (val & SR_QUAD_EN_MX)
1306 write_sr(nor, val | SR_QUAD_EN_MX);
1308 ret = spi_nor_wait_till_ready(nor);
1313 if (!(ret > 0 && (ret & SR_QUAD_EN_MX))) {
1314 dev_err(nor->dev, "Macronix Quad bit not set\n");
1322 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
1324 * Write status Register and configuration register with 2 bytes
1325 * The first byte will be written to the status register, while the
1326 * second byte will be written to the configuration register.
1327 * Return negative if error occurred.
1329 static int write_sr_cr(struct spi_nor *nor, u8 *sr_cr)
1335 ret = nor->write_reg(nor, SPINOR_OP_WRSR, sr_cr, 2);
1338 "error while writing configuration register\n");
1342 ret = spi_nor_wait_till_ready(nor);
1345 "timeout while writing configuration register\n");
1353 * spansion_read_cr_quad_enable() - set QE bit in Configuration Register.
1354 * @nor: pointer to a 'struct spi_nor'
1356 * Set the Quad Enable (QE) bit in the Configuration Register.
1357 * This function should be used with QSPI memories supporting the Read
1358 * Configuration Register (35h) instruction.
1360 * bit 1 of the Configuration Register is the QE bit for Spansion like QSPI
1363 * Return: 0 on success, -errno otherwise.
1365 static int spansion_read_cr_quad_enable(struct spi_nor *nor)
1370 /* Check current Quad Enable bit value. */
1373 dev_dbg(dev, "error while reading configuration register\n");
1377 if (ret & CR_QUAD_EN_SPAN)
1380 sr_cr[1] = ret | CR_QUAD_EN_SPAN;
1382 /* Keep the current value of the Status Register. */
1385 dev_dbg(dev, "error while reading status register\n");
1390 ret = write_sr_cr(nor, sr_cr);
1394 /* Read back and check it. */
1396 if (!(ret > 0 && (ret & CR_QUAD_EN_SPAN))) {
1397 dev_dbg(nor->dev, "Spansion Quad bit not set\n");
1404 #if CONFIG_IS_ENABLED(SPI_FLASH_SFDP_SUPPORT)
1406 * spansion_no_read_cr_quad_enable() - set QE bit in Configuration Register.
1407 * @nor: pointer to a 'struct spi_nor'
1409 * Set the Quad Enable (QE) bit in the Configuration Register.
1410 * This function should be used with QSPI memories not supporting the Read
1411 * Configuration Register (35h) instruction.
1413 * bit 1 of the Configuration Register is the QE bit for Spansion like QSPI
1416 * Return: 0 on success, -errno otherwise.
1418 static int spansion_no_read_cr_quad_enable(struct spi_nor *nor)
1423 /* Keep the current value of the Status Register. */
1426 dev_dbg(nor->dev, "error while reading status register\n");
1430 sr_cr[1] = CR_QUAD_EN_SPAN;
1432 return write_sr_cr(nor, sr_cr);
1435 #endif /* CONFIG_SPI_FLASH_SFDP_SUPPORT */
1436 #endif /* CONFIG_SPI_FLASH_SPANSION */
1438 struct spi_nor_read_command {
1442 enum spi_nor_protocol proto;
1445 struct spi_nor_pp_command {
1447 enum spi_nor_protocol proto;
1450 enum spi_nor_read_command_index {
1453 SNOR_CMD_READ_1_1_1_DTR,
1456 SNOR_CMD_READ_1_1_2,
1457 SNOR_CMD_READ_1_2_2,
1458 SNOR_CMD_READ_2_2_2,
1459 SNOR_CMD_READ_1_2_2_DTR,
1462 SNOR_CMD_READ_1_1_4,
1463 SNOR_CMD_READ_1_4_4,
1464 SNOR_CMD_READ_4_4_4,
1465 SNOR_CMD_READ_1_4_4_DTR,
1468 SNOR_CMD_READ_1_1_8,
1469 SNOR_CMD_READ_1_8_8,
1470 SNOR_CMD_READ_8_8_8,
1471 SNOR_CMD_READ_1_8_8_DTR,
1476 enum spi_nor_pp_command_index {
1492 struct spi_nor_flash_parameter {
1496 struct spi_nor_hwcaps hwcaps;
1497 struct spi_nor_read_command reads[SNOR_CMD_READ_MAX];
1498 struct spi_nor_pp_command page_programs[SNOR_CMD_PP_MAX];
1500 int (*quad_enable)(struct spi_nor *nor);
1504 spi_nor_set_read_settings(struct spi_nor_read_command *read,
1508 enum spi_nor_protocol proto)
1510 read->num_mode_clocks = num_mode_clocks;
1511 read->num_wait_states = num_wait_states;
1512 read->opcode = opcode;
1513 read->proto = proto;
1517 spi_nor_set_pp_settings(struct spi_nor_pp_command *pp,
1519 enum spi_nor_protocol proto)
1521 pp->opcode = opcode;
1525 #if CONFIG_IS_ENABLED(SPI_FLASH_SFDP_SUPPORT)
1527 * Serial Flash Discoverable Parameters (SFDP) parsing.
1531 * spi_nor_read_sfdp() - read Serial Flash Discoverable Parameters.
1532 * @nor: pointer to a 'struct spi_nor'
1533 * @addr: offset in the SFDP area to start reading data from
1534 * @len: number of bytes to read
1535 * @buf: buffer where the SFDP data are copied into (dma-safe memory)
1537 * Whatever the actual numbers of bytes for address and dummy cycles are
1538 * for (Fast) Read commands, the Read SFDP (5Ah) instruction is always
1539 * followed by a 3-byte address and 8 dummy clock cycles.
1541 * Return: 0 on success, -errno otherwise.
1543 static int spi_nor_read_sfdp(struct spi_nor *nor, u32 addr,
1544 size_t len, void *buf)
1546 u8 addr_width, read_opcode, read_dummy;
1549 read_opcode = nor->read_opcode;
1550 addr_width = nor->addr_width;
1551 read_dummy = nor->read_dummy;
1553 nor->read_opcode = SPINOR_OP_RDSFDP;
1554 nor->addr_width = 3;
1555 nor->read_dummy = 8;
1558 ret = nor->read(nor, addr, len, (u8 *)buf);
1559 if (!ret || ret > len) {
1573 nor->read_opcode = read_opcode;
1574 nor->addr_width = addr_width;
1575 nor->read_dummy = read_dummy;
1580 struct sfdp_parameter_header {
1584 u8 length; /* in double words */
1585 u8 parameter_table_pointer[3]; /* byte address */
1589 #define SFDP_PARAM_HEADER_ID(p) (((p)->id_msb << 8) | (p)->id_lsb)
1590 #define SFDP_PARAM_HEADER_PTP(p) \
1591 (((p)->parameter_table_pointer[2] << 16) | \
1592 ((p)->parameter_table_pointer[1] << 8) | \
1593 ((p)->parameter_table_pointer[0] << 0))
1595 #define SFDP_BFPT_ID 0xff00 /* Basic Flash Parameter Table */
1596 #define SFDP_SECTOR_MAP_ID 0xff81 /* Sector Map Table */
1597 #define SFDP_SST_ID 0x01bf /* Manufacturer specific Table */
1599 #define SFDP_SIGNATURE 0x50444653U
1600 #define SFDP_JESD216_MAJOR 1
1601 #define SFDP_JESD216_MINOR 0
1602 #define SFDP_JESD216A_MINOR 5
1603 #define SFDP_JESD216B_MINOR 6
1605 struct sfdp_header {
1606 u32 signature; /* Ox50444653U <=> "SFDP" */
1609 u8 nph; /* 0-base number of parameter headers */
1612 /* Basic Flash Parameter Table. */
1613 struct sfdp_parameter_header bfpt_header;
1616 /* Basic Flash Parameter Table */
1619 * JESD216 rev B defines a Basic Flash Parameter Table of 16 DWORDs.
1620 * They are indexed from 1 but C arrays are indexed from 0.
1622 #define BFPT_DWORD(i) ((i) - 1)
1623 #define BFPT_DWORD_MAX 16
1625 /* The first version of JESB216 defined only 9 DWORDs. */
1626 #define BFPT_DWORD_MAX_JESD216 9
1629 #define BFPT_DWORD1_FAST_READ_1_1_2 BIT(16)
1630 #define BFPT_DWORD1_ADDRESS_BYTES_MASK GENMASK(18, 17)
1631 #define BFPT_DWORD1_ADDRESS_BYTES_3_ONLY (0x0UL << 17)
1632 #define BFPT_DWORD1_ADDRESS_BYTES_3_OR_4 (0x1UL << 17)
1633 #define BFPT_DWORD1_ADDRESS_BYTES_4_ONLY (0x2UL << 17)
1634 #define BFPT_DWORD1_DTR BIT(19)
1635 #define BFPT_DWORD1_FAST_READ_1_2_2 BIT(20)
1636 #define BFPT_DWORD1_FAST_READ_1_4_4 BIT(21)
1637 #define BFPT_DWORD1_FAST_READ_1_1_4 BIT(22)
1640 #define BFPT_DWORD5_FAST_READ_2_2_2 BIT(0)
1641 #define BFPT_DWORD5_FAST_READ_4_4_4 BIT(4)
1644 #define BFPT_DWORD11_PAGE_SIZE_SHIFT 4
1645 #define BFPT_DWORD11_PAGE_SIZE_MASK GENMASK(7, 4)
1650 * (from JESD216 rev B)
1651 * Quad Enable Requirements (QER):
1652 * - 000b: Device does not have a QE bit. Device detects 1-1-4 and 1-4-4
1653 * reads based on instruction. DQ3/HOLD# functions are hold during
1654 * instruction phase.
1655 * - 001b: QE is bit 1 of status register 2. It is set via Write Status with
1656 * two data bytes where bit 1 of the second byte is one.
1658 * Writing only one byte to the status register has the side-effect of
1659 * clearing status register 2, including the QE bit. The 100b code is
1660 * used if writing one byte to the status register does not modify
1661 * status register 2.
1662 * - 010b: QE is bit 6 of status register 1. It is set via Write Status with
1663 * one data byte where bit 6 is one.
1665 * - 011b: QE is bit 7 of status register 2. It is set via Write status
1666 * register 2 instruction 3Eh with one data byte where bit 7 is one.
1668 * The status register 2 is read using instruction 3Fh.
1669 * - 100b: QE is bit 1 of status register 2. It is set via Write Status with
1670 * two data bytes where bit 1 of the second byte is one.
1672 * In contrast to the 001b code, writing one byte to the status
1673 * register does not modify status register 2.
1674 * - 101b: QE is bit 1 of status register 2. Status register 1 is read using
1675 * Read Status instruction 05h. Status register2 is read using
1676 * instruction 35h. QE is set via Writ Status instruction 01h with
1677 * two data bytes where bit 1 of the second byte is one.
1680 #define BFPT_DWORD15_QER_MASK GENMASK(22, 20)
1681 #define BFPT_DWORD15_QER_NONE (0x0UL << 20) /* Micron */
1682 #define BFPT_DWORD15_QER_SR2_BIT1_BUGGY (0x1UL << 20)
1683 #define BFPT_DWORD15_QER_SR1_BIT6 (0x2UL << 20) /* Macronix */
1684 #define BFPT_DWORD15_QER_SR2_BIT7 (0x3UL << 20)
1685 #define BFPT_DWORD15_QER_SR2_BIT1_NO_RD (0x4UL << 20)
1686 #define BFPT_DWORD15_QER_SR2_BIT1 (0x5UL << 20) /* Spansion */
1689 u32 dwords[BFPT_DWORD_MAX];
1692 /* Fast Read settings. */
1695 spi_nor_set_read_settings_from_bfpt(struct spi_nor_read_command *read,
1697 enum spi_nor_protocol proto)
1699 read->num_mode_clocks = (half >> 5) & 0x07;
1700 read->num_wait_states = (half >> 0) & 0x1f;
1701 read->opcode = (half >> 8) & 0xff;
1702 read->proto = proto;
1705 struct sfdp_bfpt_read {
1706 /* The Fast Read x-y-z hardware capability in params->hwcaps.mask. */
1710 * The <supported_bit> bit in <supported_dword> BFPT DWORD tells us
1711 * whether the Fast Read x-y-z command is supported.
1713 u32 supported_dword;
1717 * The half-word at offset <setting_shift> in <setting_dword> BFPT DWORD
1718 * encodes the op code, the number of mode clocks and the number of wait
1719 * states to be used by Fast Read x-y-z command.
1724 /* The SPI protocol for this Fast Read x-y-z command. */
1725 enum spi_nor_protocol proto;
1728 static const struct sfdp_bfpt_read sfdp_bfpt_reads[] = {
1729 /* Fast Read 1-1-2 */
1731 SNOR_HWCAPS_READ_1_1_2,
1732 BFPT_DWORD(1), BIT(16), /* Supported bit */
1733 BFPT_DWORD(4), 0, /* Settings */
1737 /* Fast Read 1-2-2 */
1739 SNOR_HWCAPS_READ_1_2_2,
1740 BFPT_DWORD(1), BIT(20), /* Supported bit */
1741 BFPT_DWORD(4), 16, /* Settings */
1745 /* Fast Read 2-2-2 */
1747 SNOR_HWCAPS_READ_2_2_2,
1748 BFPT_DWORD(5), BIT(0), /* Supported bit */
1749 BFPT_DWORD(6), 16, /* Settings */
1753 /* Fast Read 1-1-4 */
1755 SNOR_HWCAPS_READ_1_1_4,
1756 BFPT_DWORD(1), BIT(22), /* Supported bit */
1757 BFPT_DWORD(3), 16, /* Settings */
1761 /* Fast Read 1-4-4 */
1763 SNOR_HWCAPS_READ_1_4_4,
1764 BFPT_DWORD(1), BIT(21), /* Supported bit */
1765 BFPT_DWORD(3), 0, /* Settings */
1769 /* Fast Read 4-4-4 */
1771 SNOR_HWCAPS_READ_4_4_4,
1772 BFPT_DWORD(5), BIT(4), /* Supported bit */
1773 BFPT_DWORD(7), 16, /* Settings */
1778 struct sfdp_bfpt_erase {
1780 * The half-word at offset <shift> in DWORD <dwoard> encodes the
1781 * op code and erase sector size to be used by Sector Erase commands.
1787 static const struct sfdp_bfpt_erase sfdp_bfpt_erases[] = {
1788 /* Erase Type 1 in DWORD8 bits[15:0] */
1791 /* Erase Type 2 in DWORD8 bits[31:16] */
1792 {BFPT_DWORD(8), 16},
1794 /* Erase Type 3 in DWORD9 bits[15:0] */
1797 /* Erase Type 4 in DWORD9 bits[31:16] */
1798 {BFPT_DWORD(9), 16},
1801 static int spi_nor_hwcaps_read2cmd(u32 hwcaps);
1804 * spi_nor_parse_bfpt() - read and parse the Basic Flash Parameter Table.
1805 * @nor: pointer to a 'struct spi_nor'
1806 * @bfpt_header: pointer to the 'struct sfdp_parameter_header' describing
1807 * the Basic Flash Parameter Table length and version
1808 * @params: pointer to the 'struct spi_nor_flash_parameter' to be
1811 * The Basic Flash Parameter Table is the main and only mandatory table as
1812 * defined by the SFDP (JESD216) specification.
1813 * It provides us with the total size (memory density) of the data array and
1814 * the number of address bytes for Fast Read, Page Program and Sector Erase
1816 * For Fast READ commands, it also gives the number of mode clock cycles and
1817 * wait states (regrouped in the number of dummy clock cycles) for each
1818 * supported instruction op code.
1819 * For Page Program, the page size is now available since JESD216 rev A, however
1820 * the supported instruction op codes are still not provided.
1821 * For Sector Erase commands, this table stores the supported instruction op
1822 * codes and the associated sector sizes.
1823 * Finally, the Quad Enable Requirements (QER) are also available since JESD216
1824 * rev A. The QER bits encode the manufacturer dependent procedure to be
1825 * executed to set the Quad Enable (QE) bit in some internal register of the
1826 * Quad SPI memory. Indeed the QE bit, when it exists, must be set before
1827 * sending any Quad SPI command to the memory. Actually, setting the QE bit
1828 * tells the memory to reassign its WP# and HOLD#/RESET# pins to functions IO2
1829 * and IO3 hence enabling 4 (Quad) I/O lines.
1831 * Return: 0 on success, -errno otherwise.
1833 static int spi_nor_parse_bfpt(struct spi_nor *nor,
1834 const struct sfdp_parameter_header *bfpt_header,
1835 struct spi_nor_flash_parameter *params)
1837 struct mtd_info *mtd = &nor->mtd;
1838 struct sfdp_bfpt bfpt;
1844 /* JESD216 Basic Flash Parameter Table length is at least 9 DWORDs. */
1845 if (bfpt_header->length < BFPT_DWORD_MAX_JESD216)
1848 /* Read the Basic Flash Parameter Table. */
1849 len = min_t(size_t, sizeof(bfpt),
1850 bfpt_header->length * sizeof(u32));
1851 addr = SFDP_PARAM_HEADER_PTP(bfpt_header);
1852 memset(&bfpt, 0, sizeof(bfpt));
1853 err = spi_nor_read_sfdp(nor, addr, len, &bfpt);
1857 /* Fix endianness of the BFPT DWORDs. */
1858 for (i = 0; i < BFPT_DWORD_MAX; i++)
1859 bfpt.dwords[i] = le32_to_cpu(bfpt.dwords[i]);
1861 /* Number of address bytes. */
1862 switch (bfpt.dwords[BFPT_DWORD(1)] & BFPT_DWORD1_ADDRESS_BYTES_MASK) {
1863 case BFPT_DWORD1_ADDRESS_BYTES_3_ONLY:
1864 nor->addr_width = 3;
1867 case BFPT_DWORD1_ADDRESS_BYTES_4_ONLY:
1868 nor->addr_width = 4;
1875 /* Flash Memory Density (in bits). */
1876 params->size = bfpt.dwords[BFPT_DWORD(2)];
1877 if (params->size & BIT(31)) {
1878 params->size &= ~BIT(31);
1881 * Prevent overflows on params->size. Anyway, a NOR of 2^64
1882 * bits is unlikely to exist so this error probably means
1883 * the BFPT we are reading is corrupted/wrong.
1885 if (params->size > 63)
1888 params->size = 1ULL << params->size;
1892 params->size >>= 3; /* Convert to bytes. */
1894 /* Fast Read settings. */
1895 for (i = 0; i < ARRAY_SIZE(sfdp_bfpt_reads); i++) {
1896 const struct sfdp_bfpt_read *rd = &sfdp_bfpt_reads[i];
1897 struct spi_nor_read_command *read;
1899 if (!(bfpt.dwords[rd->supported_dword] & rd->supported_bit)) {
1900 params->hwcaps.mask &= ~rd->hwcaps;
1904 params->hwcaps.mask |= rd->hwcaps;
1905 cmd = spi_nor_hwcaps_read2cmd(rd->hwcaps);
1906 read = ¶ms->reads[cmd];
1907 half = bfpt.dwords[rd->settings_dword] >> rd->settings_shift;
1908 spi_nor_set_read_settings_from_bfpt(read, half, rd->proto);
1911 /* Sector Erase settings. */
1912 for (i = 0; i < ARRAY_SIZE(sfdp_bfpt_erases); i++) {
1913 const struct sfdp_bfpt_erase *er = &sfdp_bfpt_erases[i];
1917 half = bfpt.dwords[er->dword] >> er->shift;
1918 erasesize = half & 0xff;
1920 /* erasesize == 0 means this Erase Type is not supported. */
1924 erasesize = 1U << erasesize;
1925 opcode = (half >> 8) & 0xff;
1926 #ifdef CONFIG_SPI_FLASH_USE_4K_SECTORS
1927 if (erasesize == SZ_4K) {
1928 nor->erase_opcode = opcode;
1929 mtd->erasesize = erasesize;
1933 if (!mtd->erasesize || mtd->erasesize < erasesize) {
1934 nor->erase_opcode = opcode;
1935 mtd->erasesize = erasesize;
1939 /* Stop here if not JESD216 rev A or later. */
1940 if (bfpt_header->length < BFPT_DWORD_MAX)
1943 /* Page size: this field specifies 'N' so the page size = 2^N bytes. */
1944 params->page_size = bfpt.dwords[BFPT_DWORD(11)];
1945 params->page_size &= BFPT_DWORD11_PAGE_SIZE_MASK;
1946 params->page_size >>= BFPT_DWORD11_PAGE_SIZE_SHIFT;
1947 params->page_size = 1U << params->page_size;
1949 /* Quad Enable Requirements. */
1950 switch (bfpt.dwords[BFPT_DWORD(15)] & BFPT_DWORD15_QER_MASK) {
1951 case BFPT_DWORD15_QER_NONE:
1952 params->quad_enable = NULL;
1954 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
1955 case BFPT_DWORD15_QER_SR2_BIT1_BUGGY:
1956 case BFPT_DWORD15_QER_SR2_BIT1_NO_RD:
1957 params->quad_enable = spansion_no_read_cr_quad_enable;
1960 #ifdef CONFIG_SPI_FLASH_MACRONIX
1961 case BFPT_DWORD15_QER_SR1_BIT6:
1962 params->quad_enable = macronix_quad_enable;
1965 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
1966 case BFPT_DWORD15_QER_SR2_BIT1:
1967 params->quad_enable = spansion_read_cr_quad_enable;
1978 * spi_nor_parse_microchip_sfdp() - parse the Microchip manufacturer specific
1980 * @nor: pointer to a 'struct spi_nor'.
1981 * @param_header: pointer to the SFDP parameter header.
1983 * Return: 0 on success, -errno otherwise.
1986 spi_nor_parse_microchip_sfdp(struct spi_nor *nor,
1987 const struct sfdp_parameter_header *param_header)
1993 size = param_header->length * sizeof(u32);
1994 addr = SFDP_PARAM_HEADER_PTP(param_header);
1996 nor->manufacturer_sfdp = devm_kmalloc(nor->dev, size, GFP_KERNEL);
1997 if (!nor->manufacturer_sfdp)
2000 ret = spi_nor_read_sfdp(nor, addr, size, nor->manufacturer_sfdp);
2006 * spi_nor_parse_sfdp() - parse the Serial Flash Discoverable Parameters.
2007 * @nor: pointer to a 'struct spi_nor'
2008 * @params: pointer to the 'struct spi_nor_flash_parameter' to be
2011 * The Serial Flash Discoverable Parameters are described by the JEDEC JESD216
2012 * specification. This is a standard which tends to supported by almost all
2013 * (Q)SPI memory manufacturers. Those hard-coded tables allow us to learn at
2014 * runtime the main parameters needed to perform basic SPI flash operations such
2015 * as Fast Read, Page Program or Sector Erase commands.
2017 * Return: 0 on success, -errno otherwise.
2019 static int spi_nor_parse_sfdp(struct spi_nor *nor,
2020 struct spi_nor_flash_parameter *params)
2022 const struct sfdp_parameter_header *param_header, *bfpt_header;
2023 struct sfdp_parameter_header *param_headers = NULL;
2024 struct sfdp_header header;
2028 /* Get the SFDP header. */
2029 err = spi_nor_read_sfdp(nor, 0, sizeof(header), &header);
2033 /* Check the SFDP header version. */
2034 if (le32_to_cpu(header.signature) != SFDP_SIGNATURE ||
2035 header.major != SFDP_JESD216_MAJOR)
2039 * Verify that the first and only mandatory parameter header is a
2040 * Basic Flash Parameter Table header as specified in JESD216.
2042 bfpt_header = &header.bfpt_header;
2043 if (SFDP_PARAM_HEADER_ID(bfpt_header) != SFDP_BFPT_ID ||
2044 bfpt_header->major != SFDP_JESD216_MAJOR)
2048 * Allocate memory then read all parameter headers with a single
2049 * Read SFDP command. These parameter headers will actually be parsed
2050 * twice: a first time to get the latest revision of the basic flash
2051 * parameter table, then a second time to handle the supported optional
2053 * Hence we read the parameter headers once for all to reduce the
2054 * processing time. Also we use kmalloc() instead of devm_kmalloc()
2055 * because we don't need to keep these parameter headers: the allocated
2056 * memory is always released with kfree() before exiting this function.
2059 psize = header.nph * sizeof(*param_headers);
2061 param_headers = kmalloc(psize, GFP_KERNEL);
2065 err = spi_nor_read_sfdp(nor, sizeof(header),
2066 psize, param_headers);
2068 dev_err(dev, "failed to read SFDP parameter headers\n");
2074 * Check other parameter headers to get the latest revision of
2075 * the basic flash parameter table.
2077 for (i = 0; i < header.nph; i++) {
2078 param_header = ¶m_headers[i];
2080 if (SFDP_PARAM_HEADER_ID(param_header) == SFDP_BFPT_ID &&
2081 param_header->major == SFDP_JESD216_MAJOR &&
2082 (param_header->minor > bfpt_header->minor ||
2083 (param_header->minor == bfpt_header->minor &&
2084 param_header->length > bfpt_header->length)))
2085 bfpt_header = param_header;
2088 err = spi_nor_parse_bfpt(nor, bfpt_header, params);
2092 /* Parse other parameter headers. */
2093 for (i = 0; i < header.nph; i++) {
2094 param_header = ¶m_headers[i];
2096 switch (SFDP_PARAM_HEADER_ID(param_header)) {
2097 case SFDP_SECTOR_MAP_ID:
2098 dev_info(dev, "non-uniform erase sector maps are not supported yet.\n");
2102 err = spi_nor_parse_microchip_sfdp(nor, param_header);
2110 dev_warn(dev, "Failed to parse optional parameter table: %04x\n",
2111 SFDP_PARAM_HEADER_ID(param_header));
2113 * Let's not drop all information we extracted so far
2114 * if optional table parsers fail. In case of failing,
2115 * each optional parser is responsible to roll back to
2116 * the previously known spi_nor data.
2123 kfree(param_headers);
2127 static int spi_nor_parse_sfdp(struct spi_nor *nor,
2128 struct spi_nor_flash_parameter *params)
2132 #endif /* SPI_FLASH_SFDP_SUPPORT */
2134 static int spi_nor_init_params(struct spi_nor *nor,
2135 const struct flash_info *info,
2136 struct spi_nor_flash_parameter *params)
2138 /* Set legacy flash parameters as default. */
2139 memset(params, 0, sizeof(*params));
2141 /* Set SPI NOR sizes. */
2142 params->size = info->sector_size * info->n_sectors;
2143 params->page_size = info->page_size;
2145 /* (Fast) Read settings. */
2146 params->hwcaps.mask |= SNOR_HWCAPS_READ;
2147 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ],
2148 0, 0, SPINOR_OP_READ,
2151 if (!(info->flags & SPI_NOR_NO_FR)) {
2152 params->hwcaps.mask |= SNOR_HWCAPS_READ_FAST;
2153 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_FAST],
2154 0, 8, SPINOR_OP_READ_FAST,
2158 if (info->flags & SPI_NOR_DUAL_READ) {
2159 params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_2;
2160 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_2],
2161 0, 8, SPINOR_OP_READ_1_1_2,
2165 if (info->flags & SPI_NOR_QUAD_READ) {
2166 params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4;
2167 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_4],
2168 0, 8, SPINOR_OP_READ_1_1_4,
2172 /* Page Program settings. */
2173 params->hwcaps.mask |= SNOR_HWCAPS_PP;
2174 spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP],
2175 SPINOR_OP_PP, SNOR_PROTO_1_1_1);
2177 if (info->flags & SPI_NOR_QUAD_READ) {
2178 params->hwcaps.mask |= SNOR_HWCAPS_PP_1_1_4;
2179 spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP_1_1_4],
2180 SPINOR_OP_PP_1_1_4, SNOR_PROTO_1_1_4);
2183 /* Select the procedure to set the Quad Enable bit. */
2184 if (params->hwcaps.mask & (SNOR_HWCAPS_READ_QUAD |
2185 SNOR_HWCAPS_PP_QUAD)) {
2186 switch (JEDEC_MFR(info)) {
2187 #ifdef CONFIG_SPI_FLASH_MACRONIX
2188 case SNOR_MFR_MACRONIX:
2189 params->quad_enable = macronix_quad_enable;
2193 case SNOR_MFR_MICRON:
2197 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
2198 /* Kept only for backward compatibility purpose. */
2199 params->quad_enable = spansion_read_cr_quad_enable;
2205 /* Override the parameters with data read from SFDP tables. */
2206 nor->addr_width = 0;
2207 nor->mtd.erasesize = 0;
2208 if ((info->flags & (SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)) &&
2209 !(info->flags & SPI_NOR_SKIP_SFDP)) {
2210 struct spi_nor_flash_parameter sfdp_params;
2212 memcpy(&sfdp_params, params, sizeof(sfdp_params));
2213 if (spi_nor_parse_sfdp(nor, &sfdp_params)) {
2214 nor->addr_width = 0;
2215 nor->mtd.erasesize = 0;
2217 memcpy(params, &sfdp_params, sizeof(*params));
2224 static int spi_nor_hwcaps2cmd(u32 hwcaps, const int table[][2], size_t size)
2228 for (i = 0; i < size; i++)
2229 if (table[i][0] == (int)hwcaps)
2235 static int spi_nor_hwcaps_read2cmd(u32 hwcaps)
2237 static const int hwcaps_read2cmd[][2] = {
2238 { SNOR_HWCAPS_READ, SNOR_CMD_READ },
2239 { SNOR_HWCAPS_READ_FAST, SNOR_CMD_READ_FAST },
2240 { SNOR_HWCAPS_READ_1_1_1_DTR, SNOR_CMD_READ_1_1_1_DTR },
2241 { SNOR_HWCAPS_READ_1_1_2, SNOR_CMD_READ_1_1_2 },
2242 { SNOR_HWCAPS_READ_1_2_2, SNOR_CMD_READ_1_2_2 },
2243 { SNOR_HWCAPS_READ_2_2_2, SNOR_CMD_READ_2_2_2 },
2244 { SNOR_HWCAPS_READ_1_2_2_DTR, SNOR_CMD_READ_1_2_2_DTR },
2245 { SNOR_HWCAPS_READ_1_1_4, SNOR_CMD_READ_1_1_4 },
2246 { SNOR_HWCAPS_READ_1_4_4, SNOR_CMD_READ_1_4_4 },
2247 { SNOR_HWCAPS_READ_4_4_4, SNOR_CMD_READ_4_4_4 },
2248 { SNOR_HWCAPS_READ_1_4_4_DTR, SNOR_CMD_READ_1_4_4_DTR },
2249 { SNOR_HWCAPS_READ_1_1_8, SNOR_CMD_READ_1_1_8 },
2250 { SNOR_HWCAPS_READ_1_8_8, SNOR_CMD_READ_1_8_8 },
2251 { SNOR_HWCAPS_READ_8_8_8, SNOR_CMD_READ_8_8_8 },
2252 { SNOR_HWCAPS_READ_1_8_8_DTR, SNOR_CMD_READ_1_8_8_DTR },
2255 return spi_nor_hwcaps2cmd(hwcaps, hwcaps_read2cmd,
2256 ARRAY_SIZE(hwcaps_read2cmd));
2259 static int spi_nor_hwcaps_pp2cmd(u32 hwcaps)
2261 static const int hwcaps_pp2cmd[][2] = {
2262 { SNOR_HWCAPS_PP, SNOR_CMD_PP },
2263 { SNOR_HWCAPS_PP_1_1_4, SNOR_CMD_PP_1_1_4 },
2264 { SNOR_HWCAPS_PP_1_4_4, SNOR_CMD_PP_1_4_4 },
2265 { SNOR_HWCAPS_PP_4_4_4, SNOR_CMD_PP_4_4_4 },
2266 { SNOR_HWCAPS_PP_1_1_8, SNOR_CMD_PP_1_1_8 },
2267 { SNOR_HWCAPS_PP_1_8_8, SNOR_CMD_PP_1_8_8 },
2268 { SNOR_HWCAPS_PP_8_8_8, SNOR_CMD_PP_8_8_8 },
2271 return spi_nor_hwcaps2cmd(hwcaps, hwcaps_pp2cmd,
2272 ARRAY_SIZE(hwcaps_pp2cmd));
2275 static int spi_nor_select_read(struct spi_nor *nor,
2276 const struct spi_nor_flash_parameter *params,
2279 int cmd, best_match = fls(shared_hwcaps & SNOR_HWCAPS_READ_MASK) - 1;
2280 const struct spi_nor_read_command *read;
2285 cmd = spi_nor_hwcaps_read2cmd(BIT(best_match));
2289 read = ¶ms->reads[cmd];
2290 nor->read_opcode = read->opcode;
2291 nor->read_proto = read->proto;
2294 * In the spi-nor framework, we don't need to make the difference
2295 * between mode clock cycles and wait state clock cycles.
2296 * Indeed, the value of the mode clock cycles is used by a QSPI
2297 * flash memory to know whether it should enter or leave its 0-4-4
2298 * (Continuous Read / XIP) mode.
2299 * eXecution In Place is out of the scope of the mtd sub-system.
2300 * Hence we choose to merge both mode and wait state clock cycles
2301 * into the so called dummy clock cycles.
2303 nor->read_dummy = read->num_mode_clocks + read->num_wait_states;
2307 static int spi_nor_select_pp(struct spi_nor *nor,
2308 const struct spi_nor_flash_parameter *params,
2311 int cmd, best_match = fls(shared_hwcaps & SNOR_HWCAPS_PP_MASK) - 1;
2312 const struct spi_nor_pp_command *pp;
2317 cmd = spi_nor_hwcaps_pp2cmd(BIT(best_match));
2321 pp = ¶ms->page_programs[cmd];
2322 nor->program_opcode = pp->opcode;
2323 nor->write_proto = pp->proto;
2327 static int spi_nor_select_erase(struct spi_nor *nor,
2328 const struct flash_info *info)
2330 struct mtd_info *mtd = &nor->mtd;
2332 /* Do nothing if already configured from SFDP. */
2336 #ifdef CONFIG_SPI_FLASH_USE_4K_SECTORS
2337 /* prefer "small sector" erase if possible */
2338 if (info->flags & SECT_4K) {
2339 nor->erase_opcode = SPINOR_OP_BE_4K;
2340 mtd->erasesize = 4096;
2341 } else if (info->flags & SECT_4K_PMC) {
2342 nor->erase_opcode = SPINOR_OP_BE_4K_PMC;
2343 mtd->erasesize = 4096;
2347 nor->erase_opcode = SPINOR_OP_SE;
2348 mtd->erasesize = info->sector_size;
2353 static int spi_nor_setup(struct spi_nor *nor, const struct flash_info *info,
2354 const struct spi_nor_flash_parameter *params,
2355 const struct spi_nor_hwcaps *hwcaps)
2357 u32 ignored_mask, shared_mask;
2358 bool enable_quad_io;
2362 * Keep only the hardware capabilities supported by both the SPI
2363 * controller and the SPI flash memory.
2365 shared_mask = hwcaps->mask & params->hwcaps.mask;
2367 /* SPI n-n-n protocols are not supported yet. */
2368 ignored_mask = (SNOR_HWCAPS_READ_2_2_2 |
2369 SNOR_HWCAPS_READ_4_4_4 |
2370 SNOR_HWCAPS_READ_8_8_8 |
2371 SNOR_HWCAPS_PP_4_4_4 |
2372 SNOR_HWCAPS_PP_8_8_8);
2373 if (shared_mask & ignored_mask) {
2375 "SPI n-n-n protocols are not supported yet.\n");
2376 shared_mask &= ~ignored_mask;
2379 /* Select the (Fast) Read command. */
2380 err = spi_nor_select_read(nor, params, shared_mask);
2383 "can't select read settings supported by both the SPI controller and memory.\n");
2387 /* Select the Page Program command. */
2388 err = spi_nor_select_pp(nor, params, shared_mask);
2391 "can't select write settings supported by both the SPI controller and memory.\n");
2395 /* Select the Sector Erase command. */
2396 err = spi_nor_select_erase(nor, info);
2399 "can't select erase settings supported by both the SPI controller and memory.\n");
2403 /* Enable Quad I/O if needed. */
2404 enable_quad_io = (spi_nor_get_protocol_width(nor->read_proto) == 4 ||
2405 spi_nor_get_protocol_width(nor->write_proto) == 4);
2406 if (enable_quad_io && params->quad_enable)
2407 nor->quad_enable = params->quad_enable;
2409 nor->quad_enable = NULL;
2414 static int spi_nor_init(struct spi_nor *nor)
2419 * Atmel, SST, Intel/Numonyx, and others serial NOR tend to power up
2420 * with the software protection bits set
2422 if (JEDEC_MFR(nor->info) == SNOR_MFR_ATMEL ||
2423 JEDEC_MFR(nor->info) == SNOR_MFR_INTEL ||
2424 JEDEC_MFR(nor->info) == SNOR_MFR_SST ||
2425 nor->info->flags & SPI_NOR_HAS_LOCK) {
2428 spi_nor_wait_till_ready(nor);
2431 if (nor->quad_enable) {
2432 err = nor->quad_enable(nor);
2434 dev_dbg(nor->dev, "quad mode not supported\n");
2439 if (nor->addr_width == 4 &&
2440 (JEDEC_MFR(nor->info) != SNOR_MFR_SPANSION) &&
2441 !(nor->info->flags & SPI_NOR_4B_OPCODES)) {
2443 * If the RESET# pin isn't hooked up properly, or the system
2444 * otherwise doesn't perform a reset command in the boot
2445 * sequence, it's impossible to 100% protect against unexpected
2446 * reboots (e.g., crashes). Warn the user (or hopefully, system
2447 * designer) that this is bad.
2449 if (nor->flags & SNOR_F_BROKEN_RESET)
2450 printf("enabling reset hack; may not recover from unexpected reboots\n");
2451 set_4byte(nor, nor->info, 1);
2457 int spi_nor_scan(struct spi_nor *nor)
2459 struct spi_nor_flash_parameter params;
2460 const struct flash_info *info = NULL;
2461 struct mtd_info *mtd = &nor->mtd;
2462 struct spi_nor_hwcaps hwcaps = {
2463 .mask = SNOR_HWCAPS_READ |
2464 SNOR_HWCAPS_READ_FAST |
2467 struct spi_slave *spi = nor->spi;
2470 /* Reset SPI protocol for all commands. */
2471 nor->reg_proto = SNOR_PROTO_1_1_1;
2472 nor->read_proto = SNOR_PROTO_1_1_1;
2473 nor->write_proto = SNOR_PROTO_1_1_1;
2474 nor->read = spi_nor_read_data;
2475 nor->write = spi_nor_write_data;
2476 nor->read_reg = spi_nor_read_reg;
2477 nor->write_reg = spi_nor_write_reg;
2479 if (spi->mode & SPI_RX_QUAD) {
2480 hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4;
2482 if (spi->mode & SPI_TX_QUAD)
2483 hwcaps.mask |= (SNOR_HWCAPS_READ_1_4_4 |
2484 SNOR_HWCAPS_PP_1_1_4 |
2485 SNOR_HWCAPS_PP_1_4_4);
2486 } else if (spi->mode & SPI_RX_DUAL) {
2487 hwcaps.mask |= SNOR_HWCAPS_READ_1_1_2;
2489 if (spi->mode & SPI_TX_DUAL)
2490 hwcaps.mask |= SNOR_HWCAPS_READ_1_2_2;
2493 info = spi_nor_read_id(nor);
2494 if (IS_ERR_OR_NULL(info))
2496 /* Parse the Serial Flash Discoverable Parameters table. */
2497 ret = spi_nor_init_params(nor, info, ¶ms);
2502 mtd->name = info->name;
2504 mtd->type = MTD_NORFLASH;
2506 mtd->flags = MTD_CAP_NORFLASH;
2507 mtd->size = params.size;
2508 mtd->_erase = spi_nor_erase;
2509 mtd->_read = spi_nor_read;
2511 #if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST)
2512 /* NOR protection support for STmicro/Micron chips and similar */
2513 if (JEDEC_MFR(info) == SNOR_MFR_ST ||
2514 JEDEC_MFR(info) == SNOR_MFR_MICRON ||
2515 JEDEC_MFR(info) == SNOR_MFR_SST ||
2516 info->flags & SPI_NOR_HAS_LOCK) {
2517 nor->flash_lock = stm_lock;
2518 nor->flash_unlock = stm_unlock;
2519 nor->flash_is_locked = stm_is_locked;
2523 #ifdef CONFIG_SPI_FLASH_SST
2525 * sst26 series block protection implementation differs from other
2528 if (info->flags & SPI_NOR_HAS_SST26LOCK) {
2529 nor->flash_lock = sst26_lock;
2530 nor->flash_unlock = sst26_unlock;
2531 nor->flash_is_locked = sst26_is_locked;
2534 /* sst nor chips use AAI word program */
2535 if (info->flags & SST_WRITE)
2536 mtd->_write = sst_write;
2539 mtd->_write = spi_nor_write;
2541 if (info->flags & USE_FSR)
2542 nor->flags |= SNOR_F_USE_FSR;
2543 if (info->flags & SPI_NOR_HAS_TB)
2544 nor->flags |= SNOR_F_HAS_SR_TB;
2545 if (info->flags & NO_CHIP_ERASE)
2546 nor->flags |= SNOR_F_NO_OP_CHIP_ERASE;
2547 if (info->flags & USE_CLSR)
2548 nor->flags |= SNOR_F_USE_CLSR;
2550 if (info->flags & SPI_NOR_NO_ERASE)
2551 mtd->flags |= MTD_NO_ERASE;
2553 nor->page_size = params.page_size;
2554 mtd->writebufsize = nor->page_size;
2556 /* Some devices cannot do fast-read, no matter what DT tells us */
2557 if ((info->flags & SPI_NOR_NO_FR) || (spi->mode & SPI_RX_SLOW))
2558 params.hwcaps.mask &= ~SNOR_HWCAPS_READ_FAST;
2561 * Configure the SPI memory:
2562 * - select op codes for (Fast) Read, Page Program and Sector Erase.
2563 * - set the number of dummy cycles (mode cycles + wait states).
2564 * - set the SPI protocols for register and memory accesses.
2565 * - set the Quad Enable bit if needed (required by SPI x-y-4 protos).
2567 ret = spi_nor_setup(nor, info, ¶ms, &hwcaps);
2571 if (nor->addr_width) {
2572 /* already configured from SFDP */
2573 } else if (info->addr_width) {
2574 nor->addr_width = info->addr_width;
2575 } else if (mtd->size > SZ_16M) {
2576 #ifndef CONFIG_SPI_FLASH_BAR
2577 /* enable 4-byte addressing if the device exceeds 16MiB */
2578 nor->addr_width = 4;
2579 if (JEDEC_MFR(info) == SNOR_MFR_SPANSION ||
2580 info->flags & SPI_NOR_4B_OPCODES)
2581 spi_nor_set_4byte_opcodes(nor, info);
2583 /* Configure the BAR - discover bank cmds and read current bank */
2584 nor->addr_width = 3;
2585 ret = read_bar(nor, info);
2590 nor->addr_width = 3;
2593 if (nor->addr_width > SPI_NOR_MAX_ADDR_WIDTH) {
2594 dev_dbg(dev, "address width is too large: %u\n",
2599 /* Send all the required SPI flash commands to initialize device */
2601 ret = spi_nor_init(nor);
2605 nor->name = mtd->name;
2606 nor->size = mtd->size;
2607 nor->erase_size = mtd->erasesize;
2608 nor->sector_size = mtd->erasesize;
2610 #ifndef CONFIG_SPL_BUILD
2611 printf("SF: Detected %s with page size ", nor->name);
2612 print_size(nor->page_size, ", erase size ");
2613 print_size(nor->erase_size, ", total ");
2614 print_size(nor->size, "");
2621 /* U-Boot specific functions, need to extend MTD to support these */
2622 int spi_flash_cmd_get_sw_write_prot(struct spi_nor *nor)
2624 int sr = read_sr(nor);
2629 return (sr >> 2) & 7;