1 // SPDX-License-Identifier: GPL-2.0
3 * Based on m25p80.c, by Mike Lavender (mike@steroidmicros.com), with
4 * influence from lart.c (Abraham Van Der Merwe) and mtd_dataflash.c
6 * Copyright (C) 2005, Intec Automation Inc.
7 * Copyright (C) 2014, Freescale Semiconductor, Inc.
9 * Synced from Linux v4.19
13 #include <linux/err.h>
14 #include <linux/errno.h>
15 #include <linux/log2.h>
16 #include <linux/math64.h>
17 #include <linux/sizes.h>
19 #include <linux/mtd/mtd.h>
20 #include <linux/mtd/spi-nor.h>
24 /* Define max times to check status register before we give up. */
27 * For everything but full-chip erase; probably could be much smaller, but kept
28 * around for safety for now
31 #define HZ CONFIG_SYS_HZ
33 #define DEFAULT_READY_WAIT_JIFFIES (40UL * HZ)
35 #define SPI_NOR_MAX_ID_LEN 6
36 #define SPI_NOR_MAX_ADDR_WIDTH 4
42 * This array stores the ID bytes.
43 * The first three bytes are the JEDIC ID.
44 * JEDEC ID zero means "no ID" (mostly older chips).
46 u8 id[SPI_NOR_MAX_ID_LEN];
49 /* The size listed here is what works with SPINOR_OP_SE, which isn't
50 * necessarily called a "sector" by the vendor.
52 unsigned int sector_size;
59 #define SECT_4K BIT(0) /* SPINOR_OP_BE_4K works uniformly */
60 #define SPI_NOR_NO_ERASE BIT(1) /* No erase command needed */
61 #define SST_WRITE BIT(2) /* use SST byte programming */
62 #define SPI_NOR_NO_FR BIT(3) /* Can't do fastread */
63 #define SECT_4K_PMC BIT(4) /* SPINOR_OP_BE_4K_PMC works uniformly */
64 #define SPI_NOR_DUAL_READ BIT(5) /* Flash supports Dual Read */
65 #define SPI_NOR_QUAD_READ BIT(6) /* Flash supports Quad Read */
66 #define USE_FSR BIT(7) /* use flag status register */
67 #define SPI_NOR_HAS_LOCK BIT(8) /* Flash supports lock/unlock via SR */
68 #define SPI_NOR_HAS_TB BIT(9) /*
69 * Flash SR has Top/Bottom (TB) protect
70 * bit. Must be used with
73 #define SPI_S3AN BIT(10) /*
74 * Xilinx Spartan 3AN In-System Flash
75 * (MFR cannot be used for probing
76 * because it has the same value as
79 #define SPI_NOR_4B_OPCODES BIT(11) /*
80 * Use dedicated 4byte address op codes
81 * to support memory size above 128Mib.
83 #define NO_CHIP_ERASE BIT(12) /* Chip does not support chip erase */
84 #define SPI_NOR_SKIP_SFDP BIT(13) /* Skip parsing of SFDP tables */
85 #define USE_CLSR BIT(14) /* use CLSR command */
87 int (*quad_enable)(struct spi_nor *nor);
90 #define JEDEC_MFR(info) ((info)->id[0])
92 static int spi_nor_read_write_reg(struct spi_nor *nor, struct spi_mem_op
95 if (op->data.dir == SPI_MEM_DATA_IN)
96 op->data.buf.in = buf;
98 op->data.buf.out = buf;
99 return spi_mem_exec_op(nor->spi, op);
102 static int spi_nor_read_reg(struct spi_nor *nor, u8 code, u8 *val, int len)
104 struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(code, 1),
107 SPI_MEM_OP_DATA_IN(len, NULL, 1));
110 ret = spi_nor_read_write_reg(nor, &op, val);
112 dev_dbg(&flash->spimem->spi->dev, "error %d reading %x\n", ret,
118 static int spi_nor_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
120 struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(opcode, 1),
123 SPI_MEM_OP_DATA_OUT(len, NULL, 1));
125 return spi_nor_read_write_reg(nor, &op, buf);
128 static ssize_t spi_nor_read_data(struct spi_nor *nor, loff_t from, size_t len,
131 struct spi_mem_op op =
132 SPI_MEM_OP(SPI_MEM_OP_CMD(nor->read_opcode, 1),
133 SPI_MEM_OP_ADDR(nor->addr_width, from, 1),
134 SPI_MEM_OP_DUMMY(nor->read_dummy, 1),
135 SPI_MEM_OP_DATA_IN(len, buf, 1));
136 size_t remaining = len;
139 /* get transfer protocols. */
140 op.cmd.buswidth = spi_nor_get_protocol_inst_nbits(nor->read_proto);
141 op.addr.buswidth = spi_nor_get_protocol_addr_nbits(nor->read_proto);
142 op.dummy.buswidth = op.addr.buswidth;
143 op.data.buswidth = spi_nor_get_protocol_data_nbits(nor->read_proto);
145 /* convert the dummy cycles to the number of bytes */
146 op.dummy.nbytes = (nor->read_dummy * op.dummy.buswidth) / 8;
149 op.data.nbytes = remaining < UINT_MAX ? remaining : UINT_MAX;
150 ret = spi_mem_adjust_op_size(nor->spi, &op);
154 ret = spi_mem_exec_op(nor->spi, &op);
158 op.addr.val += op.data.nbytes;
159 remaining -= op.data.nbytes;
160 op.data.buf.in += op.data.nbytes;
166 static ssize_t spi_nor_write_data(struct spi_nor *nor, loff_t to, size_t len,
169 struct spi_mem_op op =
170 SPI_MEM_OP(SPI_MEM_OP_CMD(nor->program_opcode, 1),
171 SPI_MEM_OP_ADDR(nor->addr_width, to, 1),
173 SPI_MEM_OP_DATA_OUT(len, buf, 1));
174 size_t remaining = len;
177 /* get transfer protocols. */
178 op.cmd.buswidth = spi_nor_get_protocol_inst_nbits(nor->write_proto);
179 op.addr.buswidth = spi_nor_get_protocol_addr_nbits(nor->write_proto);
180 op.data.buswidth = spi_nor_get_protocol_data_nbits(nor->write_proto);
182 if (nor->program_opcode == SPINOR_OP_AAI_WP && nor->sst_write_second)
186 op.data.nbytes = remaining < UINT_MAX ? remaining : UINT_MAX;
187 ret = spi_mem_adjust_op_size(nor->spi, &op);
191 ret = spi_mem_exec_op(nor->spi, &op);
195 op.addr.val += op.data.nbytes;
196 remaining -= op.data.nbytes;
197 op.data.buf.out += op.data.nbytes;
204 * Read the status register, returning its value in the location
205 * Return the status register value.
206 * Returns negative if error occurred.
208 static int read_sr(struct spi_nor *nor)
213 ret = nor->read_reg(nor, SPINOR_OP_RDSR, &val, 1);
215 pr_debug("error %d reading SR\n", (int)ret);
223 * Read the flag status register, returning its value in the location
224 * Return the status register value.
225 * Returns negative if error occurred.
227 static int read_fsr(struct spi_nor *nor)
232 ret = nor->read_reg(nor, SPINOR_OP_RDFSR, &val, 1);
234 pr_debug("error %d reading FSR\n", ret);
242 * Read configuration register, returning its value in the
243 * location. Return the configuration register value.
244 * Returns negative if error occurred.
246 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
247 static int read_cr(struct spi_nor *nor)
252 ret = nor->read_reg(nor, SPINOR_OP_RDCR, &val, 1);
254 dev_dbg(nor->dev, "error %d reading CR\n", ret);
263 * Write status register 1 byte
264 * Returns negative if error occurred.
266 static int write_sr(struct spi_nor *nor, u8 val)
268 nor->cmd_buf[0] = val;
269 return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1);
273 * Set write enable latch with Write Enable command.
274 * Returns negative if error occurred.
276 static int write_enable(struct spi_nor *nor)
278 return nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0);
282 * Send write disable instruction to the chip.
284 static int write_disable(struct spi_nor *nor)
286 return nor->write_reg(nor, SPINOR_OP_WRDI, NULL, 0);
289 static struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd)
294 #ifndef CONFIG_SPI_FLASH_BAR
295 static u8 spi_nor_convert_opcode(u8 opcode, const u8 table[][2], size_t size)
299 for (i = 0; i < size; i++)
300 if (table[i][0] == opcode)
303 /* No conversion found, keep input op code. */
307 static u8 spi_nor_convert_3to4_read(u8 opcode)
309 static const u8 spi_nor_3to4_read[][2] = {
310 { SPINOR_OP_READ, SPINOR_OP_READ_4B },
311 { SPINOR_OP_READ_FAST, SPINOR_OP_READ_FAST_4B },
312 { SPINOR_OP_READ_1_1_2, SPINOR_OP_READ_1_1_2_4B },
313 { SPINOR_OP_READ_1_2_2, SPINOR_OP_READ_1_2_2_4B },
314 { SPINOR_OP_READ_1_1_4, SPINOR_OP_READ_1_1_4_4B },
315 { SPINOR_OP_READ_1_4_4, SPINOR_OP_READ_1_4_4_4B },
317 { SPINOR_OP_READ_1_1_1_DTR, SPINOR_OP_READ_1_1_1_DTR_4B },
318 { SPINOR_OP_READ_1_2_2_DTR, SPINOR_OP_READ_1_2_2_DTR_4B },
319 { SPINOR_OP_READ_1_4_4_DTR, SPINOR_OP_READ_1_4_4_DTR_4B },
322 return spi_nor_convert_opcode(opcode, spi_nor_3to4_read,
323 ARRAY_SIZE(spi_nor_3to4_read));
326 static u8 spi_nor_convert_3to4_program(u8 opcode)
328 static const u8 spi_nor_3to4_program[][2] = {
329 { SPINOR_OP_PP, SPINOR_OP_PP_4B },
330 { SPINOR_OP_PP_1_1_4, SPINOR_OP_PP_1_1_4_4B },
331 { SPINOR_OP_PP_1_4_4, SPINOR_OP_PP_1_4_4_4B },
334 return spi_nor_convert_opcode(opcode, spi_nor_3to4_program,
335 ARRAY_SIZE(spi_nor_3to4_program));
338 static u8 spi_nor_convert_3to4_erase(u8 opcode)
340 static const u8 spi_nor_3to4_erase[][2] = {
341 { SPINOR_OP_BE_4K, SPINOR_OP_BE_4K_4B },
342 { SPINOR_OP_BE_32K, SPINOR_OP_BE_32K_4B },
343 { SPINOR_OP_SE, SPINOR_OP_SE_4B },
346 return spi_nor_convert_opcode(opcode, spi_nor_3to4_erase,
347 ARRAY_SIZE(spi_nor_3to4_erase));
350 static void spi_nor_set_4byte_opcodes(struct spi_nor *nor,
351 const struct flash_info *info)
353 /* Do some manufacturer fixups first */
354 switch (JEDEC_MFR(info)) {
355 case SNOR_MFR_SPANSION:
356 /* No small sector erase for 4-byte command set */
357 nor->erase_opcode = SPINOR_OP_SE;
358 nor->mtd.erasesize = info->sector_size;
365 nor->read_opcode = spi_nor_convert_3to4_read(nor->read_opcode);
366 nor->program_opcode = spi_nor_convert_3to4_program(nor->program_opcode);
367 nor->erase_opcode = spi_nor_convert_3to4_erase(nor->erase_opcode);
369 #endif /* !CONFIG_SPI_FLASH_BAR */
371 /* Enable/disable 4-byte addressing mode. */
372 static int set_4byte(struct spi_nor *nor, const struct flash_info *info,
376 bool need_wren = false;
379 switch (JEDEC_MFR(info)) {
381 case SNOR_MFR_MICRON:
382 /* Some Micron need WREN command; all will accept it */
384 case SNOR_MFR_MACRONIX:
385 case SNOR_MFR_WINBOND:
389 cmd = enable ? SPINOR_OP_EN4B : SPINOR_OP_EX4B;
390 status = nor->write_reg(nor, cmd, NULL, 0);
394 if (!status && !enable &&
395 JEDEC_MFR(info) == SNOR_MFR_WINBOND) {
397 * On Winbond W25Q256FV, leaving 4byte mode causes
398 * the Extended Address Register to be set to 1, so all
399 * 3-byte-address reads come from the second 16M.
400 * We must clear the register to enable normal behavior.
404 nor->write_reg(nor, SPINOR_OP_WREAR, nor->cmd_buf, 1);
411 nor->cmd_buf[0] = enable << 7;
412 return nor->write_reg(nor, SPINOR_OP_BRWR, nor->cmd_buf, 1);
416 static int spi_nor_sr_ready(struct spi_nor *nor)
418 int sr = read_sr(nor);
423 if (nor->flags & SNOR_F_USE_CLSR && sr & (SR_E_ERR | SR_P_ERR)) {
425 dev_dbg(nor->dev, "Erase Error occurred\n");
427 dev_dbg(nor->dev, "Programming Error occurred\n");
429 nor->write_reg(nor, SPINOR_OP_CLSR, NULL, 0);
433 return !(sr & SR_WIP);
436 static int spi_nor_fsr_ready(struct spi_nor *nor)
438 int fsr = read_fsr(nor);
443 if (fsr & (FSR_E_ERR | FSR_P_ERR)) {
445 dev_dbg(nor->dev, "Erase operation failed.\n");
447 dev_dbg(nor->dev, "Program operation failed.\n");
449 if (fsr & FSR_PT_ERR)
451 "Attempted to modify a protected sector.\n");
453 nor->write_reg(nor, SPINOR_OP_CLFSR, NULL, 0);
457 return fsr & FSR_READY;
460 static int spi_nor_ready(struct spi_nor *nor)
464 sr = spi_nor_sr_ready(nor);
467 fsr = nor->flags & SNOR_F_USE_FSR ? spi_nor_fsr_ready(nor) : 1;
474 * Service routine to read status register until ready, or timeout occurs.
475 * Returns non-zero if error.
477 static int spi_nor_wait_till_ready_with_timeout(struct spi_nor *nor,
478 unsigned long timeout)
480 unsigned long timebase;
483 timebase = get_timer(0);
485 while (get_timer(timebase) < timeout) {
486 ret = spi_nor_ready(nor);
493 dev_err(nor->dev, "flash operation timed out\n");
498 static int spi_nor_wait_till_ready(struct spi_nor *nor)
500 return spi_nor_wait_till_ready_with_timeout(nor,
501 DEFAULT_READY_WAIT_JIFFIES);
504 #ifdef CONFIG_SPI_FLASH_BAR
506 * This "clean_bar" is necessary in a situation when one was accessing
507 * spi flash memory > 16 MiB by using Bank Address Register's BA24 bit.
509 * After it the BA24 bit shall be cleared to allow access to correct
510 * memory region after SW reset (by calling "reset" command).
512 * Otherwise, the BA24 bit may be left set and then after reset, the
513 * ROM would read/write/erase SPL from 16 MiB * bank_sel address.
515 static int clean_bar(struct spi_nor *nor)
517 u8 cmd, bank_sel = 0;
519 if (nor->bank_curr == 0)
521 cmd = nor->bank_write_cmd;
525 return nor->write_reg(nor, cmd, &bank_sel, 1);
528 static int write_bar(struct spi_nor *nor, u32 offset)
533 bank_sel = offset / SZ_16M;
534 if (bank_sel == nor->bank_curr)
537 cmd = nor->bank_write_cmd;
539 ret = nor->write_reg(nor, cmd, &bank_sel, 1);
541 debug("SF: fail to write bank register\n");
546 nor->bank_curr = bank_sel;
547 return nor->bank_curr;
550 static int read_bar(struct spi_nor *nor, const struct flash_info *info)
555 switch (JEDEC_MFR(info)) {
556 case SNOR_MFR_SPANSION:
557 nor->bank_read_cmd = SPINOR_OP_BRRD;
558 nor->bank_write_cmd = SPINOR_OP_BRWR;
561 nor->bank_read_cmd = SPINOR_OP_RDEAR;
562 nor->bank_write_cmd = SPINOR_OP_WREAR;
565 ret = nor->read_reg(nor, nor->bank_read_cmd,
568 debug("SF: fail to read bank addr register\n");
571 nor->bank_curr = curr_bank;
578 * Initiate the erasure of a single sector
580 static int spi_nor_erase_sector(struct spi_nor *nor, u32 addr)
582 u8 buf[SPI_NOR_MAX_ADDR_WIDTH];
586 return nor->erase(nor, addr);
589 * Default implementation, if driver doesn't have a specialized HW
592 for (i = nor->addr_width - 1; i >= 0; i--) {
593 buf[i] = addr & 0xff;
597 return nor->write_reg(nor, nor->erase_opcode, buf, nor->addr_width);
601 * Erase an address range on the nor chip. The address range may extend
602 * one or more erase sectors. Return an error is there is a problem erasing.
604 static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
606 struct spi_nor *nor = mtd_to_spi_nor(mtd);
610 dev_dbg(nor->dev, "at 0x%llx, len %lld\n", (long long)instr->addr,
611 (long long)instr->len);
613 div_u64_rem(instr->len, mtd->erasesize, &rem);
621 #ifdef CONFIG_SPI_FLASH_BAR
622 ret = write_bar(nor, addr);
628 ret = spi_nor_erase_sector(nor, addr);
632 addr += mtd->erasesize;
633 len -= mtd->erasesize;
635 ret = spi_nor_wait_till_ready(nor);
641 #ifdef CONFIG_SPI_FLASH_BAR
642 ret = clean_bar(nor);
649 #if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST)
650 /* Write status register and ensure bits in mask match written values */
651 static int write_sr_and_check(struct spi_nor *nor, u8 status_new, u8 mask)
656 ret = write_sr(nor, status_new);
660 ret = spi_nor_wait_till_ready(nor);
668 return ((ret & mask) != (status_new & mask)) ? -EIO : 0;
671 static void stm_get_locked_range(struct spi_nor *nor, u8 sr, loff_t *ofs,
674 struct mtd_info *mtd = &nor->mtd;
675 u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
676 int shift = ffs(mask) - 1;
684 pow = ((sr & mask) ^ mask) >> shift;
685 *len = mtd->size >> pow;
686 if (nor->flags & SNOR_F_HAS_SR_TB && sr & SR_TB)
689 *ofs = mtd->size - *len;
694 * Return 1 if the entire region is locked (if @locked is true) or unlocked (if
695 * @locked is false); 0 otherwise
697 static int stm_check_lock_status_sr(struct spi_nor *nor, loff_t ofs, u64 len,
706 stm_get_locked_range(nor, sr, &lock_offs, &lock_len);
709 /* Requested range is a sub-range of locked range */
710 return (ofs + len <= lock_offs + lock_len) && (ofs >= lock_offs);
712 /* Requested range does not overlap with locked range */
713 return (ofs >= lock_offs + lock_len) || (ofs + len <= lock_offs);
716 static int stm_is_locked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len,
719 return stm_check_lock_status_sr(nor, ofs, len, sr, true);
722 static int stm_is_unlocked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len,
725 return stm_check_lock_status_sr(nor, ofs, len, sr, false);
729 * Lock a region of the flash. Compatible with ST Micro and similar flash.
730 * Supports the block protection bits BP{0,1,2} in the status register
731 * (SR). Does not support these features found in newer SR bitfields:
732 * - SEC: sector/block protect - only handle SEC=0 (block protect)
733 * - CMP: complement protect - only support CMP=0 (range is not complemented)
735 * Support for the following is provided conditionally for some flash:
736 * - TB: top/bottom protect
738 * Sample table portion for 8MB flash (Winbond w25q64fw):
740 * SEC | TB | BP2 | BP1 | BP0 | Prot Length | Protected Portion
741 * --------------------------------------------------------------------------
742 * X | X | 0 | 0 | 0 | NONE | NONE
743 * 0 | 0 | 0 | 0 | 1 | 128 KB | Upper 1/64
744 * 0 | 0 | 0 | 1 | 0 | 256 KB | Upper 1/32
745 * 0 | 0 | 0 | 1 | 1 | 512 KB | Upper 1/16
746 * 0 | 0 | 1 | 0 | 0 | 1 MB | Upper 1/8
747 * 0 | 0 | 1 | 0 | 1 | 2 MB | Upper 1/4
748 * 0 | 0 | 1 | 1 | 0 | 4 MB | Upper 1/2
749 * X | X | 1 | 1 | 1 | 8 MB | ALL
750 * ------|-------|-------|-------|-------|---------------|-------------------
751 * 0 | 1 | 0 | 0 | 1 | 128 KB | Lower 1/64
752 * 0 | 1 | 0 | 1 | 0 | 256 KB | Lower 1/32
753 * 0 | 1 | 0 | 1 | 1 | 512 KB | Lower 1/16
754 * 0 | 1 | 1 | 0 | 0 | 1 MB | Lower 1/8
755 * 0 | 1 | 1 | 0 | 1 | 2 MB | Lower 1/4
756 * 0 | 1 | 1 | 1 | 0 | 4 MB | Lower 1/2
758 * Returns negative on errors, 0 on success.
760 static int stm_lock(struct spi_nor *nor, loff_t ofs, uint64_t len)
762 struct mtd_info *mtd = &nor->mtd;
763 int status_old, status_new;
764 u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
765 u8 shift = ffs(mask) - 1, pow, val;
767 bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB;
770 status_old = read_sr(nor);
774 /* If nothing in our range is unlocked, we don't need to do anything */
775 if (stm_is_locked_sr(nor, ofs, len, status_old))
778 /* If anything below us is unlocked, we can't use 'bottom' protection */
779 if (!stm_is_locked_sr(nor, 0, ofs, status_old))
780 can_be_bottom = false;
782 /* If anything above us is unlocked, we can't use 'top' protection */
783 if (!stm_is_locked_sr(nor, ofs + len, mtd->size - (ofs + len),
787 if (!can_be_bottom && !can_be_top)
790 /* Prefer top, if both are valid */
791 use_top = can_be_top;
793 /* lock_len: length of region that should end up locked */
795 lock_len = mtd->size - ofs;
797 lock_len = ofs + len;
800 * Need smallest pow such that:
802 * 1 / (2^pow) <= (len / size)
804 * so (assuming power-of-2 size) we do:
806 * pow = ceil(log2(size / len)) = log2(size) - floor(log2(len))
808 pow = ilog2(mtd->size) - ilog2(lock_len);
809 val = mask - (pow << shift);
812 /* Don't "lock" with no region! */
816 status_new = (status_old & ~mask & ~SR_TB) | val;
818 /* Disallow further writes if WP pin is asserted */
819 status_new |= SR_SRWD;
824 /* Don't bother if they're the same */
825 if (status_new == status_old)
828 /* Only modify protection if it will not unlock other areas */
829 if ((status_new & mask) < (status_old & mask))
832 return write_sr_and_check(nor, status_new, mask);
836 * Unlock a region of the flash. See stm_lock() for more info
838 * Returns negative on errors, 0 on success.
840 static int stm_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len)
842 struct mtd_info *mtd = &nor->mtd;
843 int status_old, status_new;
844 u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
845 u8 shift = ffs(mask) - 1, pow, val;
847 bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB;
850 status_old = read_sr(nor);
854 /* If nothing in our range is locked, we don't need to do anything */
855 if (stm_is_unlocked_sr(nor, ofs, len, status_old))
858 /* If anything below us is locked, we can't use 'top' protection */
859 if (!stm_is_unlocked_sr(nor, 0, ofs, status_old))
862 /* If anything above us is locked, we can't use 'bottom' protection */
863 if (!stm_is_unlocked_sr(nor, ofs + len, mtd->size - (ofs + len),
865 can_be_bottom = false;
867 if (!can_be_bottom && !can_be_top)
870 /* Prefer top, if both are valid */
871 use_top = can_be_top;
873 /* lock_len: length of region that should remain locked */
875 lock_len = mtd->size - (ofs + len);
880 * Need largest pow such that:
882 * 1 / (2^pow) >= (len / size)
884 * so (assuming power-of-2 size) we do:
886 * pow = floor(log2(size / len)) = log2(size) - ceil(log2(len))
888 pow = ilog2(mtd->size) - order_base_2(lock_len);
890 val = 0; /* fully unlocked */
892 val = mask - (pow << shift);
893 /* Some power-of-two sizes are not supported */
898 status_new = (status_old & ~mask & ~SR_TB) | val;
900 /* Don't protect status register if we're fully unlocked */
902 status_new &= ~SR_SRWD;
907 /* Don't bother if they're the same */
908 if (status_new == status_old)
911 /* Only modify protection if it will not lock other areas */
912 if ((status_new & mask) > (status_old & mask))
915 return write_sr_and_check(nor, status_new, mask);
919 * Check if a region of the flash is (completely) locked. See stm_lock() for
922 * Returns 1 if entire region is locked, 0 if any portion is unlocked, and
923 * negative on errors.
925 static int stm_is_locked(struct spi_nor *nor, loff_t ofs, uint64_t len)
929 status = read_sr(nor);
933 return stm_is_locked_sr(nor, ofs, len, status);
935 #endif /* CONFIG_SPI_FLASH_STMICRO */
937 /* Used when the "_ext_id" is two bytes at most */
938 #define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
940 ((_jedec_id) >> 16) & 0xff, \
941 ((_jedec_id) >> 8) & 0xff, \
942 (_jedec_id) & 0xff, \
943 ((_ext_id) >> 8) & 0xff, \
946 .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))), \
947 .sector_size = (_sector_size), \
948 .n_sectors = (_n_sectors), \
952 #define INFO6(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
954 ((_jedec_id) >> 16) & 0xff, \
955 ((_jedec_id) >> 8) & 0xff, \
956 (_jedec_id) & 0xff, \
957 ((_ext_id) >> 16) & 0xff, \
958 ((_ext_id) >> 8) & 0xff, \
962 .sector_size = (_sector_size), \
963 .n_sectors = (_n_sectors), \
967 /* NOTE: double check command sets and memory organization when you add
968 * more nor chips. This current list focusses on newer chips, which
969 * have been converging on command sets which including JEDEC ID.
971 * All newly added entries should describe *hardware* and should use SECT_4K
972 * (or SECT_4K_PMC) if hardware supports erasing 4 KiB sectors. For usage
973 * scenarios excluding small sectors there is config option that can be
974 * disabled: CONFIG_MTD_SPI_NOR_USE_4K_SECTORS.
975 * For historical (and compatibility) reasons (before we got above config) some
976 * old entries may be missing 4K flag.
978 const struct flash_info spi_nor_ids[] = {
979 #ifdef CONFIG_SPI_FLASH_ATMEL /* ATMEL */
980 /* Atmel -- some are (confusingly) marketed as "DataFlash" */
981 { "at26df321", INFO(0x1f4700, 0, 64 * 1024, 64, SECT_4K) },
982 { "at25df321a", INFO(0x1f4701, 0, 64 * 1024, 64, SECT_4K) },
984 { "at45db011d", INFO(0x1f2200, 0, 64 * 1024, 4, SECT_4K) },
985 { "at45db021d", INFO(0x1f2300, 0, 64 * 1024, 8, SECT_4K) },
986 { "at45db041d", INFO(0x1f2400, 0, 64 * 1024, 8, SECT_4K) },
987 { "at45db081d", INFO(0x1f2500, 0, 64 * 1024, 16, SECT_4K) },
988 { "at45db161d", INFO(0x1f2600, 0, 64 * 1024, 32, SECT_4K) },
989 { "at45db321d", INFO(0x1f2700, 0, 64 * 1024, 64, SECT_4K) },
990 { "at45db641d", INFO(0x1f2800, 0, 64 * 1024, 128, SECT_4K) },
991 { "at26df081a", INFO(0x1f4501, 0, 64 * 1024, 16, SECT_4K) },
993 #ifdef CONFIG_SPI_FLASH_EON /* EON */
995 { "en25q32b", INFO(0x1c3016, 0, 64 * 1024, 64, 0) },
996 { "en25q64", INFO(0x1c3017, 0, 64 * 1024, 128, SECT_4K) },
997 { "en25qh128", INFO(0x1c7018, 0, 64 * 1024, 256, 0) },
998 { "en25s64", INFO(0x1c3817, 0, 64 * 1024, 128, SECT_4K) },
1000 #ifdef CONFIG_SPI_FLASH_GIGADEVICE /* GIGADEVICE */
1003 "gd25q16", INFO(0xc84015, 0, 64 * 1024, 32,
1004 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
1005 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
1008 "gd25q32", INFO(0xc84016, 0, 64 * 1024, 64,
1009 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
1010 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
1013 "gd25lq32", INFO(0xc86016, 0, 64 * 1024, 64,
1014 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
1015 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
1018 "gd25q64", INFO(0xc84017, 0, 64 * 1024, 128,
1019 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
1020 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
1023 #ifdef CONFIG_SPI_FLASH_ISSI /* ISSI */
1025 { "is25lq040b", INFO(0x9d4013, 0, 64 * 1024, 8,
1026 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1027 { "is25lp032", INFO(0x9d6016, 0, 64 * 1024, 64, 0) },
1028 { "is25lp064", INFO(0x9d6017, 0, 64 * 1024, 128, 0) },
1029 { "is25lp128", INFO(0x9d6018, 0, 64 * 1024, 256,
1030 SECT_4K | SPI_NOR_DUAL_READ) },
1031 { "is25lp256", INFO(0x9d6019, 0, 64 * 1024, 512,
1032 SECT_4K | SPI_NOR_DUAL_READ) },
1033 { "is25wp032", INFO(0x9d7016, 0, 64 * 1024, 64,
1034 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1035 { "is25wp064", INFO(0x9d7017, 0, 64 * 1024, 128,
1036 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1037 { "is25wp128", INFO(0x9d7018, 0, 64 * 1024, 256,
1038 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1040 #ifdef CONFIG_SPI_FLASH_MACRONIX /* MACRONIX */
1042 { "mx25l2005a", INFO(0xc22012, 0, 64 * 1024, 4, SECT_4K) },
1043 { "mx25l4005a", INFO(0xc22013, 0, 64 * 1024, 8, SECT_4K) },
1044 { "mx25l8005", INFO(0xc22014, 0, 64 * 1024, 16, 0) },
1045 { "mx25l1606e", INFO(0xc22015, 0, 64 * 1024, 32, SECT_4K) },
1046 { "mx25l3205d", INFO(0xc22016, 0, 64 * 1024, 64, SECT_4K) },
1047 { "mx25l6405d", INFO(0xc22017, 0, 64 * 1024, 128, SECT_4K) },
1048 { "mx25u2033e", INFO(0xc22532, 0, 64 * 1024, 4, SECT_4K) },
1049 { "mx25u1635e", INFO(0xc22535, 0, 64 * 1024, 32, SECT_4K) },
1050 { "mx25u6435f", INFO(0xc22537, 0, 64 * 1024, 128, SECT_4K) },
1051 { "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, 0) },
1052 { "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) },
1053 { "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1054 { "mx25u25635f", INFO(0xc22539, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_4B_OPCODES) },
1055 { "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) },
1056 { "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
1057 { "mx66u51235f", INFO(0xc2253a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
1058 { "mx66l1g45g", INFO(0xc2201b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1059 { "mx25l1633e", INFO(0xc22415, 0, 64 * 1024, 32, SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | SECT_4K) },
1062 #ifdef CONFIG_SPI_FLASH_STMICRO /* STMICRO */
1064 { "n25q016a", INFO(0x20bb15, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_QUAD_READ) },
1065 { "n25q032", INFO(0x20ba16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) },
1066 { "n25q032a", INFO(0x20bb16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) },
1067 { "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) },
1068 { "n25q064a", INFO(0x20bb17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) },
1069 { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) },
1070 { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) },
1071 { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1072 { "n25q256ax1", INFO(0x20bb19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) },
1073 { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
1074 { "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
1075 { "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
1076 { "n25q00a", INFO(0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
1077 { "mt25qu02g", INFO(0x20bb22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
1079 #ifdef CONFIG_SPI_FLASH_SPANSION /* SPANSION */
1080 /* Spansion/Cypress -- single (large) sector size only, at least
1081 * for the chips listed here (without boot sectors).
1083 { "s25sl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1084 { "s25sl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1085 { "s25fl256s0", INFO(0x010219, 0x4d00, 256 * 1024, 128, USE_CLSR) },
1086 { "s25fl256s1", INFO(0x010219, 0x4d01, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
1087 { "s25fl512s", INFO6(0x010220, 0x4d0081, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
1088 { "s25fl512s_256k", INFO(0x010220, 0x4d00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
1089 { "s25fl512s_64k", INFO(0x010220, 0x4d01, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
1090 { "s25fl512s_512k", INFO(0x010220, 0x4f00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
1091 { "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) },
1092 { "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) },
1093 { "s25fl128s", INFO6(0x012018, 0x4d0180, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
1094 { "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
1095 { "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
1096 { "s25sl008a", INFO(0x010213, 0, 64 * 1024, 16, 0) },
1097 { "s25sl016a", INFO(0x010214, 0, 64 * 1024, 32, 0) },
1098 { "s25sl032a", INFO(0x010215, 0, 64 * 1024, 64, 0) },
1099 { "s25sl064a", INFO(0x010216, 0, 64 * 1024, 128, 0) },
1100 { "s25fl116k", INFO(0x014015, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1101 { "s25fl164k", INFO(0x014017, 0, 64 * 1024, 128, SECT_4K) },
1102 { "s25fl208k", INFO(0x014014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ) },
1103 { "s25fl128l", INFO(0x016018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
1105 #ifdef CONFIG_SPI_FLASH_SST /* SST */
1106 /* SST -- large erase sizes are "overlays", "sectors" are 4K */
1107 { "sst25vf040b", INFO(0xbf258d, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) },
1108 { "sst25vf080b", INFO(0xbf258e, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) },
1109 { "sst25vf016b", INFO(0xbf2541, 0, 64 * 1024, 32, SECT_4K | SST_WRITE) },
1110 { "sst25vf032b", INFO(0xbf254a, 0, 64 * 1024, 64, SECT_4K | SST_WRITE) },
1111 { "sst25vf064c", INFO(0xbf254b, 0, 64 * 1024, 128, SECT_4K) },
1112 { "sst25wf512", INFO(0xbf2501, 0, 64 * 1024, 1, SECT_4K | SST_WRITE) },
1113 { "sst25wf010", INFO(0xbf2502, 0, 64 * 1024, 2, SECT_4K | SST_WRITE) },
1114 { "sst25wf020", INFO(0xbf2503, 0, 64 * 1024, 4, SECT_4K | SST_WRITE) },
1115 { "sst25wf020a", INFO(0x621612, 0, 64 * 1024, 4, SECT_4K) },
1116 { "sst25wf040b", INFO(0x621613, 0, 64 * 1024, 8, SECT_4K) },
1117 { "sst25wf040", INFO(0xbf2504, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) },
1118 { "sst25wf080", INFO(0xbf2505, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) },
1119 { "sst26vf064b", INFO(0xbf2643, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1120 { "sst26wf016", INFO(0xbf2651, 0, 64 * 1024, 32, SECT_4K) },
1121 { "sst26wf032", INFO(0xbf2622, 0, 64 * 1024, 64, SECT_4K) },
1122 { "sst26wf064", INFO(0xbf2643, 0, 64 * 1024, 128, SECT_4K) },
1124 #ifdef CONFIG_SPI_FLASH_STMICRO /* STMICRO */
1125 /* ST Microelectronics -- newer production may have feature updates */
1126 { "m25p10", INFO(0x202011, 0, 32 * 1024, 4, 0) },
1127 { "m25p20", INFO(0x202012, 0, 64 * 1024, 4, 0) },
1128 { "m25p40", INFO(0x202013, 0, 64 * 1024, 8, 0) },
1129 { "m25p80", INFO(0x202014, 0, 64 * 1024, 16, 0) },
1130 { "m25p16", INFO(0x202015, 0, 64 * 1024, 32, 0) },
1131 { "m25p32", INFO(0x202016, 0, 64 * 1024, 64, 0) },
1132 { "m25p64", INFO(0x202017, 0, 64 * 1024, 128, 0) },
1133 { "m25p128", INFO(0x202018, 0, 256 * 1024, 64, 0) },
1134 { "m25pe16", INFO(0x208015, 0, 64 * 1024, 32, SECT_4K) },
1135 { "m25px16", INFO(0x207115, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1136 { "m25px64", INFO(0x207117, 0, 64 * 1024, 128, 0) },
1138 #ifdef CONFIG_SPI_FLASH_WINBOND /* WINBOND */
1139 /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */
1140 { "w25x05", INFO(0xef3010, 0, 64 * 1024, 1, SECT_4K) },
1141 { "w25x10", INFO(0xef3011, 0, 64 * 1024, 2, SECT_4K) },
1142 { "w25x20", INFO(0xef3012, 0, 64 * 1024, 4, SECT_4K) },
1143 { "w25x40", INFO(0xef3013, 0, 64 * 1024, 8, SECT_4K) },
1144 { "w25x80", INFO(0xef3014, 0, 64 * 1024, 16, SECT_4K) },
1145 { "w25x16", INFO(0xef3015, 0, 64 * 1024, 32, SECT_4K) },
1147 "w25q16dw", INFO(0xef6015, 0, 64 * 1024, 32,
1148 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
1149 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
1151 { "w25x32", INFO(0xef3016, 0, 64 * 1024, 64, SECT_4K) },
1152 { "w25q20cl", INFO(0xef4012, 0, 64 * 1024, 4, SECT_4K) },
1153 { "w25q20bw", INFO(0xef5012, 0, 64 * 1024, 4, SECT_4K) },
1154 { "w25q20ew", INFO(0xef6012, 0, 64 * 1024, 4, SECT_4K) },
1155 { "w25q32", INFO(0xef4016, 0, 64 * 1024, 64, SECT_4K) },
1157 "w25q32dw", INFO(0xef6016, 0, 64 * 1024, 64,
1158 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
1159 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
1162 "w25q32jv", INFO(0xef7016, 0, 64 * 1024, 64,
1163 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
1164 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
1166 { "w25x64", INFO(0xef3017, 0, 64 * 1024, 128, SECT_4K) },
1167 { "w25q64", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },
1169 "w25q64dw", INFO(0xef6017, 0, 64 * 1024, 128,
1170 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
1171 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
1174 "w25q128fw", INFO(0xef6018, 0, 64 * 1024, 256,
1175 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
1176 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
1178 { "w25q80", INFO(0xef5014, 0, 64 * 1024, 16, SECT_4K) },
1179 { "w25q80bl", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K) },
1180 { "w25q128", INFO(0xef4018, 0, 64 * 1024, 256, SECT_4K) },
1181 { "w25q256", INFO(0xef4019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1182 { "w25m512jv", INFO(0xef7119, 0, 64 * 1024, 1024,
1183 SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_DUAL_READ) },
1185 #ifdef CONFIG_SPI_FLASH_XMC
1186 /* XMC (Wuhan Xinxin Semiconductor Manufacturing Corp.) */
1187 { "XM25QH64A", INFO(0x207017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1188 { "XM25QH128A", INFO(0x207018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1193 static const struct flash_info *spi_nor_read_id(struct spi_nor *nor)
1196 u8 id[SPI_NOR_MAX_ID_LEN];
1197 const struct flash_info *info;
1199 if (!ARRAY_SIZE(spi_nor_ids))
1200 return ERR_PTR(-ENODEV);
1202 tmp = nor->read_reg(nor, SPINOR_OP_RDID, id, SPI_NOR_MAX_ID_LEN);
1204 dev_dbg(nor->dev, "error %d reading JEDEC ID\n", tmp);
1205 return ERR_PTR(tmp);
1208 for (tmp = 0; tmp < ARRAY_SIZE(spi_nor_ids) - 1; tmp++) {
1209 info = &spi_nor_ids[tmp];
1211 if (!memcmp(info->id, id, info->id_len))
1212 return &spi_nor_ids[tmp];
1215 dev_err(nor->dev, "unrecognized JEDEC id bytes: %02x, %02x, %02x\n",
1216 id[0], id[1], id[2]);
1217 return ERR_PTR(-ENODEV);
1220 static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len,
1221 size_t *retlen, u_char *buf)
1223 struct spi_nor *nor = mtd_to_spi_nor(mtd);
1226 dev_dbg(nor->dev, "from 0x%08x, len %zd\n", (u32)from, len);
1230 size_t read_len = len;
1232 #ifdef CONFIG_SPI_FLASH_BAR
1235 ret = write_bar(nor, addr);
1237 return log_ret(ret);
1238 remain_len = (SZ_16M * (nor->bank_curr + 1)) - addr;
1240 if (len < remain_len)
1243 read_len = remain_len;
1246 ret = nor->read(nor, addr, read_len, buf);
1248 /* We shouldn't see 0-length reads */
1263 #ifdef CONFIG_SPI_FLASH_BAR
1264 ret = clean_bar(nor);
1269 #ifdef CONFIG_SPI_FLASH_SST
1270 static int sst_write_byteprogram(struct spi_nor *nor, loff_t to, size_t len,
1271 size_t *retlen, const u_char *buf)
1276 for (actual = 0; actual < len; actual++) {
1277 nor->program_opcode = SPINOR_OP_BP;
1280 /* write one byte. */
1281 ret = nor->write(nor, to, 1, buf + actual);
1284 ret = spi_nor_wait_till_ready(nor);
1295 static int sst_write(struct mtd_info *mtd, loff_t to, size_t len,
1296 size_t *retlen, const u_char *buf)
1298 struct spi_nor *nor = mtd_to_spi_nor(mtd);
1299 struct spi_slave *spi = nor->spi;
1303 dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len);
1304 if (spi->mode & SPI_TX_BYTE)
1305 return sst_write_byteprogram(nor, to, len, retlen, buf);
1309 nor->sst_write_second = false;
1312 /* Start write from odd address. */
1314 nor->program_opcode = SPINOR_OP_BP;
1316 /* write one byte. */
1317 ret = nor->write(nor, to, 1, buf);
1320 ret = spi_nor_wait_till_ready(nor);
1326 /* Write out most of the data here. */
1327 for (; actual < len - 1; actual += 2) {
1328 nor->program_opcode = SPINOR_OP_AAI_WP;
1330 /* write two bytes. */
1331 ret = nor->write(nor, to, 2, buf + actual);
1334 ret = spi_nor_wait_till_ready(nor);
1338 nor->sst_write_second = true;
1340 nor->sst_write_second = false;
1343 ret = spi_nor_wait_till_ready(nor);
1347 /* Write out trailing byte if it exists. */
1348 if (actual != len) {
1351 nor->program_opcode = SPINOR_OP_BP;
1352 ret = nor->write(nor, to, 1, buf + actual);
1355 ret = spi_nor_wait_till_ready(nor);
1367 * Write an address range to the nor chip. Data must be written in
1368 * FLASH_PAGESIZE chunks. The address range may be any size provided
1369 * it is within the physical boundaries.
1371 static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len,
1372 size_t *retlen, const u_char *buf)
1374 struct spi_nor *nor = mtd_to_spi_nor(mtd);
1375 size_t page_offset, page_remain, i;
1378 dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len);
1380 for (i = 0; i < len; ) {
1382 loff_t addr = to + i;
1385 * If page_size is a power of two, the offset can be quickly
1386 * calculated with an AND operation. On the other cases we
1387 * need to do a modulus operation (more expensive).
1388 * Power of two numbers have only one bit set and we can use
1389 * the instruction hweight32 to detect if we need to do a
1390 * modulus (do_div()) or not.
1392 if (hweight32(nor->page_size) == 1) {
1393 page_offset = addr & (nor->page_size - 1);
1397 page_offset = do_div(aux, nor->page_size);
1399 /* the size of data remaining on the first page */
1400 page_remain = min_t(size_t,
1401 nor->page_size - page_offset, len - i);
1403 #ifdef CONFIG_SPI_FLASH_BAR
1404 ret = write_bar(nor, addr);
1409 ret = nor->write(nor, addr, page_remain, buf + i);
1414 ret = spi_nor_wait_till_ready(nor);
1419 if (written != page_remain) {
1426 #ifdef CONFIG_SPI_FLASH_BAR
1427 ret = clean_bar(nor);
1432 #ifdef CONFIG_SPI_FLASH_MACRONIX
1434 * macronix_quad_enable() - set QE bit in Status Register.
1435 * @nor: pointer to a 'struct spi_nor'
1437 * Set the Quad Enable (QE) bit in the Status Register.
1439 * bit 6 of the Status Register is the QE bit for Macronix like QSPI memories.
1441 * Return: 0 on success, -errno otherwise.
1443 static int macronix_quad_enable(struct spi_nor *nor)
1450 if (val & SR_QUAD_EN_MX)
1455 write_sr(nor, val | SR_QUAD_EN_MX);
1457 ret = spi_nor_wait_till_ready(nor);
1462 if (!(ret > 0 && (ret & SR_QUAD_EN_MX))) {
1463 dev_err(nor->dev, "Macronix Quad bit not set\n");
1471 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
1473 * Write status Register and configuration register with 2 bytes
1474 * The first byte will be written to the status register, while the
1475 * second byte will be written to the configuration register.
1476 * Return negative if error occurred.
1478 static int write_sr_cr(struct spi_nor *nor, u8 *sr_cr)
1484 ret = nor->write_reg(nor, SPINOR_OP_WRSR, sr_cr, 2);
1487 "error while writing configuration register\n");
1491 ret = spi_nor_wait_till_ready(nor);
1494 "timeout while writing configuration register\n");
1502 * spansion_read_cr_quad_enable() - set QE bit in Configuration Register.
1503 * @nor: pointer to a 'struct spi_nor'
1505 * Set the Quad Enable (QE) bit in the Configuration Register.
1506 * This function should be used with QSPI memories supporting the Read
1507 * Configuration Register (35h) instruction.
1509 * bit 1 of the Configuration Register is the QE bit for Spansion like QSPI
1512 * Return: 0 on success, -errno otherwise.
1514 static int spansion_read_cr_quad_enable(struct spi_nor *nor)
1519 /* Check current Quad Enable bit value. */
1522 dev_dbg(dev, "error while reading configuration register\n");
1526 if (ret & CR_QUAD_EN_SPAN)
1529 sr_cr[1] = ret | CR_QUAD_EN_SPAN;
1531 /* Keep the current value of the Status Register. */
1534 dev_dbg(dev, "error while reading status register\n");
1539 ret = write_sr_cr(nor, sr_cr);
1543 /* Read back and check it. */
1545 if (!(ret > 0 && (ret & CR_QUAD_EN_SPAN))) {
1546 dev_dbg(nor->dev, "Spansion Quad bit not set\n");
1553 #if CONFIG_IS_ENABLED(SPI_FLASH_SFDP_SUPPORT)
1555 * spansion_no_read_cr_quad_enable() - set QE bit in Configuration Register.
1556 * @nor: pointer to a 'struct spi_nor'
1558 * Set the Quad Enable (QE) bit in the Configuration Register.
1559 * This function should be used with QSPI memories not supporting the Read
1560 * Configuration Register (35h) instruction.
1562 * bit 1 of the Configuration Register is the QE bit for Spansion like QSPI
1565 * Return: 0 on success, -errno otherwise.
1567 static int spansion_no_read_cr_quad_enable(struct spi_nor *nor)
1572 /* Keep the current value of the Status Register. */
1575 dev_dbg(nor->dev, "error while reading status register\n");
1579 sr_cr[1] = CR_QUAD_EN_SPAN;
1581 return write_sr_cr(nor, sr_cr);
1584 #endif /* CONFIG_SPI_FLASH_SFDP_SUPPORT */
1585 #endif /* CONFIG_SPI_FLASH_SPANSION */
1587 struct spi_nor_read_command {
1591 enum spi_nor_protocol proto;
1594 struct spi_nor_pp_command {
1596 enum spi_nor_protocol proto;
1599 enum spi_nor_read_command_index {
1602 SNOR_CMD_READ_1_1_1_DTR,
1605 SNOR_CMD_READ_1_1_2,
1606 SNOR_CMD_READ_1_2_2,
1607 SNOR_CMD_READ_2_2_2,
1608 SNOR_CMD_READ_1_2_2_DTR,
1611 SNOR_CMD_READ_1_1_4,
1612 SNOR_CMD_READ_1_4_4,
1613 SNOR_CMD_READ_4_4_4,
1614 SNOR_CMD_READ_1_4_4_DTR,
1617 SNOR_CMD_READ_1_1_8,
1618 SNOR_CMD_READ_1_8_8,
1619 SNOR_CMD_READ_8_8_8,
1620 SNOR_CMD_READ_1_8_8_DTR,
1625 enum spi_nor_pp_command_index {
1641 struct spi_nor_flash_parameter {
1645 struct spi_nor_hwcaps hwcaps;
1646 struct spi_nor_read_command reads[SNOR_CMD_READ_MAX];
1647 struct spi_nor_pp_command page_programs[SNOR_CMD_PP_MAX];
1649 int (*quad_enable)(struct spi_nor *nor);
1653 spi_nor_set_read_settings(struct spi_nor_read_command *read,
1657 enum spi_nor_protocol proto)
1659 read->num_mode_clocks = num_mode_clocks;
1660 read->num_wait_states = num_wait_states;
1661 read->opcode = opcode;
1662 read->proto = proto;
1666 spi_nor_set_pp_settings(struct spi_nor_pp_command *pp,
1668 enum spi_nor_protocol proto)
1670 pp->opcode = opcode;
1674 #if CONFIG_IS_ENABLED(SPI_FLASH_SFDP_SUPPORT)
1676 * Serial Flash Discoverable Parameters (SFDP) parsing.
1680 * spi_nor_read_sfdp() - read Serial Flash Discoverable Parameters.
1681 * @nor: pointer to a 'struct spi_nor'
1682 * @addr: offset in the SFDP area to start reading data from
1683 * @len: number of bytes to read
1684 * @buf: buffer where the SFDP data are copied into (dma-safe memory)
1686 * Whatever the actual numbers of bytes for address and dummy cycles are
1687 * for (Fast) Read commands, the Read SFDP (5Ah) instruction is always
1688 * followed by a 3-byte address and 8 dummy clock cycles.
1690 * Return: 0 on success, -errno otherwise.
1692 static int spi_nor_read_sfdp(struct spi_nor *nor, u32 addr,
1693 size_t len, void *buf)
1695 u8 addr_width, read_opcode, read_dummy;
1698 read_opcode = nor->read_opcode;
1699 addr_width = nor->addr_width;
1700 read_dummy = nor->read_dummy;
1702 nor->read_opcode = SPINOR_OP_RDSFDP;
1703 nor->addr_width = 3;
1704 nor->read_dummy = 8;
1707 ret = nor->read(nor, addr, len, (u8 *)buf);
1708 if (!ret || ret > len) {
1722 nor->read_opcode = read_opcode;
1723 nor->addr_width = addr_width;
1724 nor->read_dummy = read_dummy;
1729 struct sfdp_parameter_header {
1733 u8 length; /* in double words */
1734 u8 parameter_table_pointer[3]; /* byte address */
1738 #define SFDP_PARAM_HEADER_ID(p) (((p)->id_msb << 8) | (p)->id_lsb)
1739 #define SFDP_PARAM_HEADER_PTP(p) \
1740 (((p)->parameter_table_pointer[2] << 16) | \
1741 ((p)->parameter_table_pointer[1] << 8) | \
1742 ((p)->parameter_table_pointer[0] << 0))
1744 #define SFDP_BFPT_ID 0xff00 /* Basic Flash Parameter Table */
1745 #define SFDP_SECTOR_MAP_ID 0xff81 /* Sector Map Table */
1747 #define SFDP_SIGNATURE 0x50444653U
1748 #define SFDP_JESD216_MAJOR 1
1749 #define SFDP_JESD216_MINOR 0
1750 #define SFDP_JESD216A_MINOR 5
1751 #define SFDP_JESD216B_MINOR 6
1753 struct sfdp_header {
1754 u32 signature; /* Ox50444653U <=> "SFDP" */
1757 u8 nph; /* 0-base number of parameter headers */
1760 /* Basic Flash Parameter Table. */
1761 struct sfdp_parameter_header bfpt_header;
1764 /* Basic Flash Parameter Table */
1767 * JESD216 rev B defines a Basic Flash Parameter Table of 16 DWORDs.
1768 * They are indexed from 1 but C arrays are indexed from 0.
1770 #define BFPT_DWORD(i) ((i) - 1)
1771 #define BFPT_DWORD_MAX 16
1773 /* The first version of JESB216 defined only 9 DWORDs. */
1774 #define BFPT_DWORD_MAX_JESD216 9
1777 #define BFPT_DWORD1_FAST_READ_1_1_2 BIT(16)
1778 #define BFPT_DWORD1_ADDRESS_BYTES_MASK GENMASK(18, 17)
1779 #define BFPT_DWORD1_ADDRESS_BYTES_3_ONLY (0x0UL << 17)
1780 #define BFPT_DWORD1_ADDRESS_BYTES_3_OR_4 (0x1UL << 17)
1781 #define BFPT_DWORD1_ADDRESS_BYTES_4_ONLY (0x2UL << 17)
1782 #define BFPT_DWORD1_DTR BIT(19)
1783 #define BFPT_DWORD1_FAST_READ_1_2_2 BIT(20)
1784 #define BFPT_DWORD1_FAST_READ_1_4_4 BIT(21)
1785 #define BFPT_DWORD1_FAST_READ_1_1_4 BIT(22)
1788 #define BFPT_DWORD5_FAST_READ_2_2_2 BIT(0)
1789 #define BFPT_DWORD5_FAST_READ_4_4_4 BIT(4)
1792 #define BFPT_DWORD11_PAGE_SIZE_SHIFT 4
1793 #define BFPT_DWORD11_PAGE_SIZE_MASK GENMASK(7, 4)
1798 * (from JESD216 rev B)
1799 * Quad Enable Requirements (QER):
1800 * - 000b: Device does not have a QE bit. Device detects 1-1-4 and 1-4-4
1801 * reads based on instruction. DQ3/HOLD# functions are hold during
1802 * instruction phase.
1803 * - 001b: QE is bit 1 of status register 2. It is set via Write Status with
1804 * two data bytes where bit 1 of the second byte is one.
1806 * Writing only one byte to the status register has the side-effect of
1807 * clearing status register 2, including the QE bit. The 100b code is
1808 * used if writing one byte to the status register does not modify
1809 * status register 2.
1810 * - 010b: QE is bit 6 of status register 1. It is set via Write Status with
1811 * one data byte where bit 6 is one.
1813 * - 011b: QE is bit 7 of status register 2. It is set via Write status
1814 * register 2 instruction 3Eh with one data byte where bit 7 is one.
1816 * The status register 2 is read using instruction 3Fh.
1817 * - 100b: QE is bit 1 of status register 2. It is set via Write Status with
1818 * two data bytes where bit 1 of the second byte is one.
1820 * In contrast to the 001b code, writing one byte to the status
1821 * register does not modify status register 2.
1822 * - 101b: QE is bit 1 of status register 2. Status register 1 is read using
1823 * Read Status instruction 05h. Status register2 is read using
1824 * instruction 35h. QE is set via Writ Status instruction 01h with
1825 * two data bytes where bit 1 of the second byte is one.
1828 #define BFPT_DWORD15_QER_MASK GENMASK(22, 20)
1829 #define BFPT_DWORD15_QER_NONE (0x0UL << 20) /* Micron */
1830 #define BFPT_DWORD15_QER_SR2_BIT1_BUGGY (0x1UL << 20)
1831 #define BFPT_DWORD15_QER_SR1_BIT6 (0x2UL << 20) /* Macronix */
1832 #define BFPT_DWORD15_QER_SR2_BIT7 (0x3UL << 20)
1833 #define BFPT_DWORD15_QER_SR2_BIT1_NO_RD (0x4UL << 20)
1834 #define BFPT_DWORD15_QER_SR2_BIT1 (0x5UL << 20) /* Spansion */
1837 u32 dwords[BFPT_DWORD_MAX];
1840 /* Fast Read settings. */
1843 spi_nor_set_read_settings_from_bfpt(struct spi_nor_read_command *read,
1845 enum spi_nor_protocol proto)
1847 read->num_mode_clocks = (half >> 5) & 0x07;
1848 read->num_wait_states = (half >> 0) & 0x1f;
1849 read->opcode = (half >> 8) & 0xff;
1850 read->proto = proto;
1853 struct sfdp_bfpt_read {
1854 /* The Fast Read x-y-z hardware capability in params->hwcaps.mask. */
1858 * The <supported_bit> bit in <supported_dword> BFPT DWORD tells us
1859 * whether the Fast Read x-y-z command is supported.
1861 u32 supported_dword;
1865 * The half-word at offset <setting_shift> in <setting_dword> BFPT DWORD
1866 * encodes the op code, the number of mode clocks and the number of wait
1867 * states to be used by Fast Read x-y-z command.
1872 /* The SPI protocol for this Fast Read x-y-z command. */
1873 enum spi_nor_protocol proto;
1876 static const struct sfdp_bfpt_read sfdp_bfpt_reads[] = {
1877 /* Fast Read 1-1-2 */
1879 SNOR_HWCAPS_READ_1_1_2,
1880 BFPT_DWORD(1), BIT(16), /* Supported bit */
1881 BFPT_DWORD(4), 0, /* Settings */
1885 /* Fast Read 1-2-2 */
1887 SNOR_HWCAPS_READ_1_2_2,
1888 BFPT_DWORD(1), BIT(20), /* Supported bit */
1889 BFPT_DWORD(4), 16, /* Settings */
1893 /* Fast Read 2-2-2 */
1895 SNOR_HWCAPS_READ_2_2_2,
1896 BFPT_DWORD(5), BIT(0), /* Supported bit */
1897 BFPT_DWORD(6), 16, /* Settings */
1901 /* Fast Read 1-1-4 */
1903 SNOR_HWCAPS_READ_1_1_4,
1904 BFPT_DWORD(1), BIT(22), /* Supported bit */
1905 BFPT_DWORD(3), 16, /* Settings */
1909 /* Fast Read 1-4-4 */
1911 SNOR_HWCAPS_READ_1_4_4,
1912 BFPT_DWORD(1), BIT(21), /* Supported bit */
1913 BFPT_DWORD(3), 0, /* Settings */
1917 /* Fast Read 4-4-4 */
1919 SNOR_HWCAPS_READ_4_4_4,
1920 BFPT_DWORD(5), BIT(4), /* Supported bit */
1921 BFPT_DWORD(7), 16, /* Settings */
1926 struct sfdp_bfpt_erase {
1928 * The half-word at offset <shift> in DWORD <dwoard> encodes the
1929 * op code and erase sector size to be used by Sector Erase commands.
1935 static const struct sfdp_bfpt_erase sfdp_bfpt_erases[] = {
1936 /* Erase Type 1 in DWORD8 bits[15:0] */
1939 /* Erase Type 2 in DWORD8 bits[31:16] */
1940 {BFPT_DWORD(8), 16},
1942 /* Erase Type 3 in DWORD9 bits[15:0] */
1945 /* Erase Type 4 in DWORD9 bits[31:16] */
1946 {BFPT_DWORD(9), 16},
1949 static int spi_nor_hwcaps_read2cmd(u32 hwcaps);
1952 * spi_nor_parse_bfpt() - read and parse the Basic Flash Parameter Table.
1953 * @nor: pointer to a 'struct spi_nor'
1954 * @bfpt_header: pointer to the 'struct sfdp_parameter_header' describing
1955 * the Basic Flash Parameter Table length and version
1956 * @params: pointer to the 'struct spi_nor_flash_parameter' to be
1959 * The Basic Flash Parameter Table is the main and only mandatory table as
1960 * defined by the SFDP (JESD216) specification.
1961 * It provides us with the total size (memory density) of the data array and
1962 * the number of address bytes for Fast Read, Page Program and Sector Erase
1964 * For Fast READ commands, it also gives the number of mode clock cycles and
1965 * wait states (regrouped in the number of dummy clock cycles) for each
1966 * supported instruction op code.
1967 * For Page Program, the page size is now available since JESD216 rev A, however
1968 * the supported instruction op codes are still not provided.
1969 * For Sector Erase commands, this table stores the supported instruction op
1970 * codes and the associated sector sizes.
1971 * Finally, the Quad Enable Requirements (QER) are also available since JESD216
1972 * rev A. The QER bits encode the manufacturer dependent procedure to be
1973 * executed to set the Quad Enable (QE) bit in some internal register of the
1974 * Quad SPI memory. Indeed the QE bit, when it exists, must be set before
1975 * sending any Quad SPI command to the memory. Actually, setting the QE bit
1976 * tells the memory to reassign its WP# and HOLD#/RESET# pins to functions IO2
1977 * and IO3 hence enabling 4 (Quad) I/O lines.
1979 * Return: 0 on success, -errno otherwise.
1981 static int spi_nor_parse_bfpt(struct spi_nor *nor,
1982 const struct sfdp_parameter_header *bfpt_header,
1983 struct spi_nor_flash_parameter *params)
1985 struct mtd_info *mtd = &nor->mtd;
1986 struct sfdp_bfpt bfpt;
1992 /* JESD216 Basic Flash Parameter Table length is at least 9 DWORDs. */
1993 if (bfpt_header->length < BFPT_DWORD_MAX_JESD216)
1996 /* Read the Basic Flash Parameter Table. */
1997 len = min_t(size_t, sizeof(bfpt),
1998 bfpt_header->length * sizeof(u32));
1999 addr = SFDP_PARAM_HEADER_PTP(bfpt_header);
2000 memset(&bfpt, 0, sizeof(bfpt));
2001 err = spi_nor_read_sfdp(nor, addr, len, &bfpt);
2005 /* Fix endianness of the BFPT DWORDs. */
2006 for (i = 0; i < BFPT_DWORD_MAX; i++)
2007 bfpt.dwords[i] = le32_to_cpu(bfpt.dwords[i]);
2009 /* Number of address bytes. */
2010 switch (bfpt.dwords[BFPT_DWORD(1)] & BFPT_DWORD1_ADDRESS_BYTES_MASK) {
2011 case BFPT_DWORD1_ADDRESS_BYTES_3_ONLY:
2012 nor->addr_width = 3;
2015 case BFPT_DWORD1_ADDRESS_BYTES_4_ONLY:
2016 nor->addr_width = 4;
2023 /* Flash Memory Density (in bits). */
2024 params->size = bfpt.dwords[BFPT_DWORD(2)];
2025 if (params->size & BIT(31)) {
2026 params->size &= ~BIT(31);
2029 * Prevent overflows on params->size. Anyway, a NOR of 2^64
2030 * bits is unlikely to exist so this error probably means
2031 * the BFPT we are reading is corrupted/wrong.
2033 if (params->size > 63)
2036 params->size = 1ULL << params->size;
2040 params->size >>= 3; /* Convert to bytes. */
2042 /* Fast Read settings. */
2043 for (i = 0; i < ARRAY_SIZE(sfdp_bfpt_reads); i++) {
2044 const struct sfdp_bfpt_read *rd = &sfdp_bfpt_reads[i];
2045 struct spi_nor_read_command *read;
2047 if (!(bfpt.dwords[rd->supported_dword] & rd->supported_bit)) {
2048 params->hwcaps.mask &= ~rd->hwcaps;
2052 params->hwcaps.mask |= rd->hwcaps;
2053 cmd = spi_nor_hwcaps_read2cmd(rd->hwcaps);
2054 read = ¶ms->reads[cmd];
2055 half = bfpt.dwords[rd->settings_dword] >> rd->settings_shift;
2056 spi_nor_set_read_settings_from_bfpt(read, half, rd->proto);
2059 /* Sector Erase settings. */
2060 for (i = 0; i < ARRAY_SIZE(sfdp_bfpt_erases); i++) {
2061 const struct sfdp_bfpt_erase *er = &sfdp_bfpt_erases[i];
2065 half = bfpt.dwords[er->dword] >> er->shift;
2066 erasesize = half & 0xff;
2068 /* erasesize == 0 means this Erase Type is not supported. */
2072 erasesize = 1U << erasesize;
2073 opcode = (half >> 8) & 0xff;
2074 #ifdef CONFIG_MTD_SPI_NOR_USE_4K_SECTORS
2075 if (erasesize == SZ_4K) {
2076 nor->erase_opcode = opcode;
2077 mtd->erasesize = erasesize;
2081 if (!mtd->erasesize || mtd->erasesize < erasesize) {
2082 nor->erase_opcode = opcode;
2083 mtd->erasesize = erasesize;
2087 /* Stop here if not JESD216 rev A or later. */
2088 if (bfpt_header->length < BFPT_DWORD_MAX)
2091 /* Page size: this field specifies 'N' so the page size = 2^N bytes. */
2092 params->page_size = bfpt.dwords[BFPT_DWORD(11)];
2093 params->page_size &= BFPT_DWORD11_PAGE_SIZE_MASK;
2094 params->page_size >>= BFPT_DWORD11_PAGE_SIZE_SHIFT;
2095 params->page_size = 1U << params->page_size;
2097 /* Quad Enable Requirements. */
2098 switch (bfpt.dwords[BFPT_DWORD(15)] & BFPT_DWORD15_QER_MASK) {
2099 case BFPT_DWORD15_QER_NONE:
2100 params->quad_enable = NULL;
2102 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
2103 case BFPT_DWORD15_QER_SR2_BIT1_BUGGY:
2104 case BFPT_DWORD15_QER_SR2_BIT1_NO_RD:
2105 params->quad_enable = spansion_no_read_cr_quad_enable;
2108 #ifdef CONFIG_SPI_FLASH_MACRONIX
2109 case BFPT_DWORD15_QER_SR1_BIT6:
2110 params->quad_enable = macronix_quad_enable;
2113 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
2114 case BFPT_DWORD15_QER_SR2_BIT1:
2115 params->quad_enable = spansion_read_cr_quad_enable;
2126 * spi_nor_parse_sfdp() - parse the Serial Flash Discoverable Parameters.
2127 * @nor: pointer to a 'struct spi_nor'
2128 * @params: pointer to the 'struct spi_nor_flash_parameter' to be
2131 * The Serial Flash Discoverable Parameters are described by the JEDEC JESD216
2132 * specification. This is a standard which tends to supported by almost all
2133 * (Q)SPI memory manufacturers. Those hard-coded tables allow us to learn at
2134 * runtime the main parameters needed to perform basic SPI flash operations such
2135 * as Fast Read, Page Program or Sector Erase commands.
2137 * Return: 0 on success, -errno otherwise.
2139 static int spi_nor_parse_sfdp(struct spi_nor *nor,
2140 struct spi_nor_flash_parameter *params)
2142 const struct sfdp_parameter_header *param_header, *bfpt_header;
2143 struct sfdp_parameter_header *param_headers = NULL;
2144 struct sfdp_header header;
2148 /* Get the SFDP header. */
2149 err = spi_nor_read_sfdp(nor, 0, sizeof(header), &header);
2153 /* Check the SFDP header version. */
2154 if (le32_to_cpu(header.signature) != SFDP_SIGNATURE ||
2155 header.major != SFDP_JESD216_MAJOR)
2159 * Verify that the first and only mandatory parameter header is a
2160 * Basic Flash Parameter Table header as specified in JESD216.
2162 bfpt_header = &header.bfpt_header;
2163 if (SFDP_PARAM_HEADER_ID(bfpt_header) != SFDP_BFPT_ID ||
2164 bfpt_header->major != SFDP_JESD216_MAJOR)
2168 * Allocate memory then read all parameter headers with a single
2169 * Read SFDP command. These parameter headers will actually be parsed
2170 * twice: a first time to get the latest revision of the basic flash
2171 * parameter table, then a second time to handle the supported optional
2173 * Hence we read the parameter headers once for all to reduce the
2174 * processing time. Also we use kmalloc() instead of devm_kmalloc()
2175 * because we don't need to keep these parameter headers: the allocated
2176 * memory is always released with kfree() before exiting this function.
2179 psize = header.nph * sizeof(*param_headers);
2181 param_headers = kmalloc(psize, GFP_KERNEL);
2185 err = spi_nor_read_sfdp(nor, sizeof(header),
2186 psize, param_headers);
2188 dev_err(dev, "failed to read SFDP parameter headers\n");
2194 * Check other parameter headers to get the latest revision of
2195 * the basic flash parameter table.
2197 for (i = 0; i < header.nph; i++) {
2198 param_header = ¶m_headers[i];
2200 if (SFDP_PARAM_HEADER_ID(param_header) == SFDP_BFPT_ID &&
2201 param_header->major == SFDP_JESD216_MAJOR &&
2202 (param_header->minor > bfpt_header->minor ||
2203 (param_header->minor == bfpt_header->minor &&
2204 param_header->length > bfpt_header->length)))
2205 bfpt_header = param_header;
2208 err = spi_nor_parse_bfpt(nor, bfpt_header, params);
2212 /* Parse other parameter headers. */
2213 for (i = 0; i < header.nph; i++) {
2214 param_header = ¶m_headers[i];
2216 switch (SFDP_PARAM_HEADER_ID(param_header)) {
2217 case SFDP_SECTOR_MAP_ID:
2218 dev_info(dev, "non-uniform erase sector maps are not supported yet.\n");
2230 kfree(param_headers);
2234 static int spi_nor_parse_sfdp(struct spi_nor *nor,
2235 struct spi_nor_flash_parameter *params)
2239 #endif /* SPI_FLASH_SFDP_SUPPORT */
2241 static int spi_nor_init_params(struct spi_nor *nor,
2242 const struct flash_info *info,
2243 struct spi_nor_flash_parameter *params)
2245 /* Set legacy flash parameters as default. */
2246 memset(params, 0, sizeof(*params));
2248 /* Set SPI NOR sizes. */
2249 params->size = info->sector_size * info->n_sectors;
2250 params->page_size = info->page_size;
2252 /* (Fast) Read settings. */
2253 params->hwcaps.mask |= SNOR_HWCAPS_READ;
2254 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ],
2255 0, 0, SPINOR_OP_READ,
2258 if (!(info->flags & SPI_NOR_NO_FR)) {
2259 params->hwcaps.mask |= SNOR_HWCAPS_READ_FAST;
2260 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_FAST],
2261 0, 8, SPINOR_OP_READ_FAST,
2265 if (info->flags & SPI_NOR_DUAL_READ) {
2266 params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_2;
2267 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_2],
2268 0, 8, SPINOR_OP_READ_1_1_2,
2272 if (info->flags & SPI_NOR_QUAD_READ) {
2273 params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4;
2274 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_4],
2275 0, 8, SPINOR_OP_READ_1_1_4,
2279 /* Page Program settings. */
2280 params->hwcaps.mask |= SNOR_HWCAPS_PP;
2281 spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP],
2282 SPINOR_OP_PP, SNOR_PROTO_1_1_1);
2284 if (info->flags & SPI_NOR_QUAD_READ) {
2285 params->hwcaps.mask |= SNOR_HWCAPS_PP_1_1_4;
2286 spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP_1_1_4],
2287 SPINOR_OP_PP_1_1_4, SNOR_PROTO_1_1_4);
2290 /* Select the procedure to set the Quad Enable bit. */
2291 if (params->hwcaps.mask & (SNOR_HWCAPS_READ_QUAD |
2292 SNOR_HWCAPS_PP_QUAD)) {
2293 switch (JEDEC_MFR(info)) {
2294 #ifdef CONFIG_SPI_FLASH_MACRONIX
2295 case SNOR_MFR_MACRONIX:
2296 params->quad_enable = macronix_quad_enable;
2300 case SNOR_MFR_MICRON:
2304 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
2305 /* Kept only for backward compatibility purpose. */
2306 params->quad_enable = spansion_read_cr_quad_enable;
2312 /* Override the parameters with data read from SFDP tables. */
2313 nor->addr_width = 0;
2314 nor->mtd.erasesize = 0;
2315 if ((info->flags & (SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)) &&
2316 !(info->flags & SPI_NOR_SKIP_SFDP)) {
2317 struct spi_nor_flash_parameter sfdp_params;
2319 memcpy(&sfdp_params, params, sizeof(sfdp_params));
2320 if (spi_nor_parse_sfdp(nor, &sfdp_params)) {
2321 nor->addr_width = 0;
2322 nor->mtd.erasesize = 0;
2324 memcpy(params, &sfdp_params, sizeof(*params));
2331 static int spi_nor_hwcaps2cmd(u32 hwcaps, const int table[][2], size_t size)
2335 for (i = 0; i < size; i++)
2336 if (table[i][0] == (int)hwcaps)
2342 static int spi_nor_hwcaps_read2cmd(u32 hwcaps)
2344 static const int hwcaps_read2cmd[][2] = {
2345 { SNOR_HWCAPS_READ, SNOR_CMD_READ },
2346 { SNOR_HWCAPS_READ_FAST, SNOR_CMD_READ_FAST },
2347 { SNOR_HWCAPS_READ_1_1_1_DTR, SNOR_CMD_READ_1_1_1_DTR },
2348 { SNOR_HWCAPS_READ_1_1_2, SNOR_CMD_READ_1_1_2 },
2349 { SNOR_HWCAPS_READ_1_2_2, SNOR_CMD_READ_1_2_2 },
2350 { SNOR_HWCAPS_READ_2_2_2, SNOR_CMD_READ_2_2_2 },
2351 { SNOR_HWCAPS_READ_1_2_2_DTR, SNOR_CMD_READ_1_2_2_DTR },
2352 { SNOR_HWCAPS_READ_1_1_4, SNOR_CMD_READ_1_1_4 },
2353 { SNOR_HWCAPS_READ_1_4_4, SNOR_CMD_READ_1_4_4 },
2354 { SNOR_HWCAPS_READ_4_4_4, SNOR_CMD_READ_4_4_4 },
2355 { SNOR_HWCAPS_READ_1_4_4_DTR, SNOR_CMD_READ_1_4_4_DTR },
2356 { SNOR_HWCAPS_READ_1_1_8, SNOR_CMD_READ_1_1_8 },
2357 { SNOR_HWCAPS_READ_1_8_8, SNOR_CMD_READ_1_8_8 },
2358 { SNOR_HWCAPS_READ_8_8_8, SNOR_CMD_READ_8_8_8 },
2359 { SNOR_HWCAPS_READ_1_8_8_DTR, SNOR_CMD_READ_1_8_8_DTR },
2362 return spi_nor_hwcaps2cmd(hwcaps, hwcaps_read2cmd,
2363 ARRAY_SIZE(hwcaps_read2cmd));
2366 static int spi_nor_hwcaps_pp2cmd(u32 hwcaps)
2368 static const int hwcaps_pp2cmd[][2] = {
2369 { SNOR_HWCAPS_PP, SNOR_CMD_PP },
2370 { SNOR_HWCAPS_PP_1_1_4, SNOR_CMD_PP_1_1_4 },
2371 { SNOR_HWCAPS_PP_1_4_4, SNOR_CMD_PP_1_4_4 },
2372 { SNOR_HWCAPS_PP_4_4_4, SNOR_CMD_PP_4_4_4 },
2373 { SNOR_HWCAPS_PP_1_1_8, SNOR_CMD_PP_1_1_8 },
2374 { SNOR_HWCAPS_PP_1_8_8, SNOR_CMD_PP_1_8_8 },
2375 { SNOR_HWCAPS_PP_8_8_8, SNOR_CMD_PP_8_8_8 },
2378 return spi_nor_hwcaps2cmd(hwcaps, hwcaps_pp2cmd,
2379 ARRAY_SIZE(hwcaps_pp2cmd));
2382 static int spi_nor_select_read(struct spi_nor *nor,
2383 const struct spi_nor_flash_parameter *params,
2386 int cmd, best_match = fls(shared_hwcaps & SNOR_HWCAPS_READ_MASK) - 1;
2387 const struct spi_nor_read_command *read;
2392 cmd = spi_nor_hwcaps_read2cmd(BIT(best_match));
2396 read = ¶ms->reads[cmd];
2397 nor->read_opcode = read->opcode;
2398 nor->read_proto = read->proto;
2401 * In the spi-nor framework, we don't need to make the difference
2402 * between mode clock cycles and wait state clock cycles.
2403 * Indeed, the value of the mode clock cycles is used by a QSPI
2404 * flash memory to know whether it should enter or leave its 0-4-4
2405 * (Continuous Read / XIP) mode.
2406 * eXecution In Place is out of the scope of the mtd sub-system.
2407 * Hence we choose to merge both mode and wait state clock cycles
2408 * into the so called dummy clock cycles.
2410 nor->read_dummy = read->num_mode_clocks + read->num_wait_states;
2414 static int spi_nor_select_pp(struct spi_nor *nor,
2415 const struct spi_nor_flash_parameter *params,
2418 int cmd, best_match = fls(shared_hwcaps & SNOR_HWCAPS_PP_MASK) - 1;
2419 const struct spi_nor_pp_command *pp;
2424 cmd = spi_nor_hwcaps_pp2cmd(BIT(best_match));
2428 pp = ¶ms->page_programs[cmd];
2429 nor->program_opcode = pp->opcode;
2430 nor->write_proto = pp->proto;
2434 static int spi_nor_select_erase(struct spi_nor *nor,
2435 const struct flash_info *info)
2437 struct mtd_info *mtd = &nor->mtd;
2439 /* Do nothing if already configured from SFDP. */
2443 #ifdef CONFIG_SPI_FLASH_USE_4K_SECTORS
2444 /* prefer "small sector" erase if possible */
2445 if (info->flags & SECT_4K) {
2446 nor->erase_opcode = SPINOR_OP_BE_4K;
2447 mtd->erasesize = 4096;
2448 } else if (info->flags & SECT_4K_PMC) {
2449 nor->erase_opcode = SPINOR_OP_BE_4K_PMC;
2450 mtd->erasesize = 4096;
2454 nor->erase_opcode = SPINOR_OP_SE;
2455 mtd->erasesize = info->sector_size;
2460 static int spi_nor_setup(struct spi_nor *nor, const struct flash_info *info,
2461 const struct spi_nor_flash_parameter *params,
2462 const struct spi_nor_hwcaps *hwcaps)
2464 u32 ignored_mask, shared_mask;
2465 bool enable_quad_io;
2469 * Keep only the hardware capabilities supported by both the SPI
2470 * controller and the SPI flash memory.
2472 shared_mask = hwcaps->mask & params->hwcaps.mask;
2474 /* SPI n-n-n protocols are not supported yet. */
2475 ignored_mask = (SNOR_HWCAPS_READ_2_2_2 |
2476 SNOR_HWCAPS_READ_4_4_4 |
2477 SNOR_HWCAPS_READ_8_8_8 |
2478 SNOR_HWCAPS_PP_4_4_4 |
2479 SNOR_HWCAPS_PP_8_8_8);
2480 if (shared_mask & ignored_mask) {
2482 "SPI n-n-n protocols are not supported yet.\n");
2483 shared_mask &= ~ignored_mask;
2486 /* Select the (Fast) Read command. */
2487 err = spi_nor_select_read(nor, params, shared_mask);
2490 "can't select read settings supported by both the SPI controller and memory.\n");
2494 /* Select the Page Program command. */
2495 err = spi_nor_select_pp(nor, params, shared_mask);
2498 "can't select write settings supported by both the SPI controller and memory.\n");
2502 /* Select the Sector Erase command. */
2503 err = spi_nor_select_erase(nor, info);
2506 "can't select erase settings supported by both the SPI controller and memory.\n");
2510 /* Enable Quad I/O if needed. */
2511 enable_quad_io = (spi_nor_get_protocol_width(nor->read_proto) == 4 ||
2512 spi_nor_get_protocol_width(nor->write_proto) == 4);
2513 if (enable_quad_io && params->quad_enable)
2514 nor->quad_enable = params->quad_enable;
2516 nor->quad_enable = NULL;
2521 static int spi_nor_init(struct spi_nor *nor)
2526 * Atmel, SST, Intel/Numonyx, and others serial NOR tend to power up
2527 * with the software protection bits set
2529 if (JEDEC_MFR(nor->info) == SNOR_MFR_ATMEL ||
2530 JEDEC_MFR(nor->info) == SNOR_MFR_INTEL ||
2531 JEDEC_MFR(nor->info) == SNOR_MFR_SST ||
2532 nor->info->flags & SPI_NOR_HAS_LOCK) {
2535 spi_nor_wait_till_ready(nor);
2538 if (nor->quad_enable) {
2539 err = nor->quad_enable(nor);
2541 dev_dbg(nor->dev, "quad mode not supported\n");
2546 if (nor->addr_width == 4 &&
2547 (JEDEC_MFR(nor->info) != SNOR_MFR_SPANSION) &&
2548 !(nor->info->flags & SPI_NOR_4B_OPCODES)) {
2550 * If the RESET# pin isn't hooked up properly, or the system
2551 * otherwise doesn't perform a reset command in the boot
2552 * sequence, it's impossible to 100% protect against unexpected
2553 * reboots (e.g., crashes). Warn the user (or hopefully, system
2554 * designer) that this is bad.
2556 if (nor->flags & SNOR_F_BROKEN_RESET)
2557 printf("enabling reset hack; may not recover from unexpected reboots\n");
2558 set_4byte(nor, nor->info, 1);
2564 int spi_nor_scan(struct spi_nor *nor)
2566 struct spi_nor_flash_parameter params;
2567 const struct flash_info *info = NULL;
2568 struct mtd_info *mtd = &nor->mtd;
2569 struct spi_nor_hwcaps hwcaps = {
2570 .mask = SNOR_HWCAPS_READ |
2571 SNOR_HWCAPS_READ_FAST |
2574 struct spi_slave *spi = nor->spi;
2577 /* Reset SPI protocol for all commands. */
2578 nor->reg_proto = SNOR_PROTO_1_1_1;
2579 nor->read_proto = SNOR_PROTO_1_1_1;
2580 nor->write_proto = SNOR_PROTO_1_1_1;
2581 nor->read = spi_nor_read_data;
2582 nor->write = spi_nor_write_data;
2583 nor->read_reg = spi_nor_read_reg;
2584 nor->write_reg = spi_nor_write_reg;
2586 if (spi->mode & SPI_RX_QUAD) {
2587 hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4;
2589 if (spi->mode & SPI_TX_QUAD)
2590 hwcaps.mask |= (SNOR_HWCAPS_READ_1_4_4 |
2591 SNOR_HWCAPS_PP_1_1_4 |
2592 SNOR_HWCAPS_PP_1_4_4);
2593 } else if (spi->mode & SPI_RX_DUAL) {
2594 hwcaps.mask |= SNOR_HWCAPS_READ_1_1_2;
2596 if (spi->mode & SPI_TX_DUAL)
2597 hwcaps.mask |= SNOR_HWCAPS_READ_1_2_2;
2600 info = spi_nor_read_id(nor);
2601 if (IS_ERR_OR_NULL(info))
2603 /* Parse the Serial Flash Discoverable Parameters table. */
2604 ret = spi_nor_init_params(nor, info, ¶ms);
2609 mtd->name = info->name;
2611 mtd->type = MTD_NORFLASH;
2613 mtd->flags = MTD_CAP_NORFLASH;
2614 mtd->size = params.size;
2615 mtd->_erase = spi_nor_erase;
2616 mtd->_read = spi_nor_read;
2618 #if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST)
2619 /* NOR protection support for STmicro/Micron chips and similar */
2620 if (JEDEC_MFR(info) == SNOR_MFR_ST ||
2621 JEDEC_MFR(info) == SNOR_MFR_MICRON ||
2622 JEDEC_MFR(info) == SNOR_MFR_SST ||
2623 info->flags & SPI_NOR_HAS_LOCK) {
2624 nor->flash_lock = stm_lock;
2625 nor->flash_unlock = stm_unlock;
2626 nor->flash_is_locked = stm_is_locked;
2630 #ifdef CONFIG_SPI_FLASH_SST
2631 /* sst nor chips use AAI word program */
2632 if (info->flags & SST_WRITE)
2633 mtd->_write = sst_write;
2636 mtd->_write = spi_nor_write;
2638 if (info->flags & USE_FSR)
2639 nor->flags |= SNOR_F_USE_FSR;
2640 if (info->flags & SPI_NOR_HAS_TB)
2641 nor->flags |= SNOR_F_HAS_SR_TB;
2642 if (info->flags & NO_CHIP_ERASE)
2643 nor->flags |= SNOR_F_NO_OP_CHIP_ERASE;
2644 if (info->flags & USE_CLSR)
2645 nor->flags |= SNOR_F_USE_CLSR;
2647 if (info->flags & SPI_NOR_NO_ERASE)
2648 mtd->flags |= MTD_NO_ERASE;
2650 nor->page_size = params.page_size;
2651 mtd->writebufsize = nor->page_size;
2653 /* Some devices cannot do fast-read, no matter what DT tells us */
2654 if ((info->flags & SPI_NOR_NO_FR) || (spi->mode & SPI_RX_SLOW))
2655 params.hwcaps.mask &= ~SNOR_HWCAPS_READ_FAST;
2658 * Configure the SPI memory:
2659 * - select op codes for (Fast) Read, Page Program and Sector Erase.
2660 * - set the number of dummy cycles (mode cycles + wait states).
2661 * - set the SPI protocols for register and memory accesses.
2662 * - set the Quad Enable bit if needed (required by SPI x-y-4 protos).
2664 ret = spi_nor_setup(nor, info, ¶ms, &hwcaps);
2668 if (nor->addr_width) {
2669 /* already configured from SFDP */
2670 } else if (info->addr_width) {
2671 nor->addr_width = info->addr_width;
2672 } else if (mtd->size > SZ_16M) {
2673 #ifndef CONFIG_SPI_FLASH_BAR
2674 /* enable 4-byte addressing if the device exceeds 16MiB */
2675 nor->addr_width = 4;
2676 if (JEDEC_MFR(info) == SNOR_MFR_SPANSION ||
2677 info->flags & SPI_NOR_4B_OPCODES)
2678 spi_nor_set_4byte_opcodes(nor, info);
2680 /* Configure the BAR - discover bank cmds and read current bank */
2681 nor->addr_width = 3;
2682 ret = read_bar(nor, info);
2687 nor->addr_width = 3;
2690 if (nor->addr_width > SPI_NOR_MAX_ADDR_WIDTH) {
2691 dev_dbg(dev, "address width is too large: %u\n",
2696 /* Send all the required SPI flash commands to initialize device */
2698 ret = spi_nor_init(nor);
2702 nor->name = mtd->name;
2703 nor->size = mtd->size;
2704 nor->erase_size = mtd->erasesize;
2705 nor->sector_size = mtd->erasesize;
2707 #ifndef CONFIG_SPL_BUILD
2708 printf("SF: Detected %s with page size ", nor->name);
2709 print_size(nor->page_size, ", erase size ");
2710 print_size(nor->erase_size, ", total ");
2711 print_size(nor->size, "");
2718 /* U-Boot specific functions, need to extend MTD to support these */
2719 int spi_flash_cmd_get_sw_write_prot(struct spi_nor *nor)
2721 int sr = read_sr(nor);
2726 return (sr >> 2) & 7;