1 // SPDX-License-Identifier: GPL-2.0
3 * Based on m25p80.c, by Mike Lavender (mike@steroidmicros.com), with
4 * influence from lart.c (Abraham Van Der Merwe) and mtd_dataflash.c
6 * Copyright (C) 2005, Intec Automation Inc.
7 * Copyright (C) 2014, Freescale Semiconductor, Inc.
9 * Synced from Linux v4.19
14 #include <dm/device_compat.h>
15 #include <dm/devres.h>
16 #include <linux/bitops.h>
17 #include <linux/err.h>
18 #include <linux/errno.h>
19 #include <linux/log2.h>
20 #include <linux/math64.h>
21 #include <linux/sizes.h>
23 #include <linux/mtd/mtd.h>
24 #include <linux/mtd/spi-nor.h>
28 #include "sf_internal.h"
30 /* Define max times to check status register before we give up. */
33 * For everything but full-chip erase; probably could be much smaller, but kept
34 * around for safety for now
37 #define HZ CONFIG_SYS_HZ
39 #define DEFAULT_READY_WAIT_JIFFIES (40UL * HZ)
41 static int spi_nor_read_write_reg(struct spi_nor *nor, struct spi_mem_op
44 if (op->data.dir == SPI_MEM_DATA_IN)
45 op->data.buf.in = buf;
47 op->data.buf.out = buf;
48 return spi_mem_exec_op(nor->spi, op);
51 static int spi_nor_read_reg(struct spi_nor *nor, u8 code, u8 *val, int len)
53 struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(code, 1),
56 SPI_MEM_OP_DATA_IN(len, NULL, 1));
59 ret = spi_nor_read_write_reg(nor, &op, val);
61 dev_dbg(nor->dev, "error %d reading %x\n", ret, code);
66 static int spi_nor_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
68 struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(opcode, 1),
71 SPI_MEM_OP_DATA_OUT(len, NULL, 1));
73 return spi_nor_read_write_reg(nor, &op, buf);
76 static ssize_t spi_nor_read_data(struct spi_nor *nor, loff_t from, size_t len,
79 struct spi_mem_op op =
80 SPI_MEM_OP(SPI_MEM_OP_CMD(nor->read_opcode, 1),
81 SPI_MEM_OP_ADDR(nor->addr_width, from, 1),
82 SPI_MEM_OP_DUMMY(nor->read_dummy, 1),
83 SPI_MEM_OP_DATA_IN(len, buf, 1));
84 size_t remaining = len;
87 /* get transfer protocols. */
88 op.cmd.buswidth = spi_nor_get_protocol_inst_nbits(nor->read_proto);
89 op.addr.buswidth = spi_nor_get_protocol_addr_nbits(nor->read_proto);
90 op.dummy.buswidth = op.addr.buswidth;
91 op.data.buswidth = spi_nor_get_protocol_data_nbits(nor->read_proto);
93 /* convert the dummy cycles to the number of bytes */
94 op.dummy.nbytes = (nor->read_dummy * op.dummy.buswidth) / 8;
97 op.data.nbytes = remaining < UINT_MAX ? remaining : UINT_MAX;
98 ret = spi_mem_adjust_op_size(nor->spi, &op);
102 ret = spi_mem_exec_op(nor->spi, &op);
106 op.addr.val += op.data.nbytes;
107 remaining -= op.data.nbytes;
108 op.data.buf.in += op.data.nbytes;
114 static ssize_t spi_nor_write_data(struct spi_nor *nor, loff_t to, size_t len,
117 struct spi_mem_op op =
118 SPI_MEM_OP(SPI_MEM_OP_CMD(nor->program_opcode, 1),
119 SPI_MEM_OP_ADDR(nor->addr_width, to, 1),
121 SPI_MEM_OP_DATA_OUT(len, buf, 1));
124 /* get transfer protocols. */
125 op.cmd.buswidth = spi_nor_get_protocol_inst_nbits(nor->write_proto);
126 op.addr.buswidth = spi_nor_get_protocol_addr_nbits(nor->write_proto);
127 op.data.buswidth = spi_nor_get_protocol_data_nbits(nor->write_proto);
129 if (nor->program_opcode == SPINOR_OP_AAI_WP && nor->sst_write_second)
132 ret = spi_mem_adjust_op_size(nor->spi, &op);
135 op.data.nbytes = len < op.data.nbytes ? len : op.data.nbytes;
137 ret = spi_mem_exec_op(nor->spi, &op);
141 return op.data.nbytes;
145 * Read the status register, returning its value in the location
146 * Return the status register value.
147 * Returns negative if error occurred.
149 static int read_sr(struct spi_nor *nor)
154 ret = nor->read_reg(nor, SPINOR_OP_RDSR, &val, 1);
156 pr_debug("error %d reading SR\n", (int)ret);
164 * Read the flag status register, returning its value in the location
165 * Return the status register value.
166 * Returns negative if error occurred.
168 static int read_fsr(struct spi_nor *nor)
173 ret = nor->read_reg(nor, SPINOR_OP_RDFSR, &val, 1);
175 pr_debug("error %d reading FSR\n", ret);
183 * Read configuration register, returning its value in the
184 * location. Return the configuration register value.
185 * Returns negative if error occurred.
187 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
188 static int read_cr(struct spi_nor *nor)
193 ret = nor->read_reg(nor, SPINOR_OP_RDCR, &val, 1);
195 dev_dbg(nor->dev, "error %d reading CR\n", ret);
204 * Write status register 1 byte
205 * Returns negative if error occurred.
207 static int write_sr(struct spi_nor *nor, u8 val)
209 nor->cmd_buf[0] = val;
210 return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1);
214 * Set write enable latch with Write Enable command.
215 * Returns negative if error occurred.
217 static int write_enable(struct spi_nor *nor)
219 return nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0);
223 * Send write disable instruction to the chip.
225 static int write_disable(struct spi_nor *nor)
227 return nor->write_reg(nor, SPINOR_OP_WRDI, NULL, 0);
230 static struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd)
235 #ifndef CONFIG_SPI_FLASH_BAR
236 static u8 spi_nor_convert_opcode(u8 opcode, const u8 table[][2], size_t size)
240 for (i = 0; i < size; i++)
241 if (table[i][0] == opcode)
244 /* No conversion found, keep input op code. */
248 static u8 spi_nor_convert_3to4_read(u8 opcode)
250 static const u8 spi_nor_3to4_read[][2] = {
251 { SPINOR_OP_READ, SPINOR_OP_READ_4B },
252 { SPINOR_OP_READ_FAST, SPINOR_OP_READ_FAST_4B },
253 { SPINOR_OP_READ_1_1_2, SPINOR_OP_READ_1_1_2_4B },
254 { SPINOR_OP_READ_1_2_2, SPINOR_OP_READ_1_2_2_4B },
255 { SPINOR_OP_READ_1_1_4, SPINOR_OP_READ_1_1_4_4B },
256 { SPINOR_OP_READ_1_4_4, SPINOR_OP_READ_1_4_4_4B },
257 { SPINOR_OP_READ_1_1_8, SPINOR_OP_READ_1_1_8_4B },
258 { SPINOR_OP_READ_1_8_8, SPINOR_OP_READ_1_8_8_4B },
260 { SPINOR_OP_READ_1_1_1_DTR, SPINOR_OP_READ_1_1_1_DTR_4B },
261 { SPINOR_OP_READ_1_2_2_DTR, SPINOR_OP_READ_1_2_2_DTR_4B },
262 { SPINOR_OP_READ_1_4_4_DTR, SPINOR_OP_READ_1_4_4_DTR_4B },
265 return spi_nor_convert_opcode(opcode, spi_nor_3to4_read,
266 ARRAY_SIZE(spi_nor_3to4_read));
269 static u8 spi_nor_convert_3to4_program(u8 opcode)
271 static const u8 spi_nor_3to4_program[][2] = {
272 { SPINOR_OP_PP, SPINOR_OP_PP_4B },
273 { SPINOR_OP_PP_1_1_4, SPINOR_OP_PP_1_1_4_4B },
274 { SPINOR_OP_PP_1_4_4, SPINOR_OP_PP_1_4_4_4B },
275 { SPINOR_OP_PP_1_1_8, SPINOR_OP_PP_1_1_8_4B },
276 { SPINOR_OP_PP_1_8_8, SPINOR_OP_PP_1_8_8_4B },
279 return spi_nor_convert_opcode(opcode, spi_nor_3to4_program,
280 ARRAY_SIZE(spi_nor_3to4_program));
283 static u8 spi_nor_convert_3to4_erase(u8 opcode)
285 static const u8 spi_nor_3to4_erase[][2] = {
286 { SPINOR_OP_BE_4K, SPINOR_OP_BE_4K_4B },
287 { SPINOR_OP_BE_32K, SPINOR_OP_BE_32K_4B },
288 { SPINOR_OP_SE, SPINOR_OP_SE_4B },
291 return spi_nor_convert_opcode(opcode, spi_nor_3to4_erase,
292 ARRAY_SIZE(spi_nor_3to4_erase));
295 static void spi_nor_set_4byte_opcodes(struct spi_nor *nor,
296 const struct flash_info *info)
298 /* Do some manufacturer fixups first */
299 switch (JEDEC_MFR(info)) {
300 case SNOR_MFR_SPANSION:
301 /* No small sector erase for 4-byte command set */
302 nor->erase_opcode = SPINOR_OP_SE;
303 nor->mtd.erasesize = info->sector_size;
310 nor->read_opcode = spi_nor_convert_3to4_read(nor->read_opcode);
311 nor->program_opcode = spi_nor_convert_3to4_program(nor->program_opcode);
312 nor->erase_opcode = spi_nor_convert_3to4_erase(nor->erase_opcode);
314 #endif /* !CONFIG_SPI_FLASH_BAR */
316 /* Enable/disable 4-byte addressing mode. */
317 static int set_4byte(struct spi_nor *nor, const struct flash_info *info,
321 bool need_wren = false;
324 switch (JEDEC_MFR(info)) {
326 case SNOR_MFR_MICRON:
327 /* Some Micron need WREN command; all will accept it */
330 case SNOR_MFR_MACRONIX:
331 case SNOR_MFR_WINBOND:
335 cmd = enable ? SPINOR_OP_EN4B : SPINOR_OP_EX4B;
336 status = nor->write_reg(nor, cmd, NULL, 0);
340 if (!status && !enable &&
341 JEDEC_MFR(info) == SNOR_MFR_WINBOND) {
343 * On Winbond W25Q256FV, leaving 4byte mode causes
344 * the Extended Address Register to be set to 1, so all
345 * 3-byte-address reads come from the second 16M.
346 * We must clear the register to enable normal behavior.
350 nor->write_reg(nor, SPINOR_OP_WREAR, nor->cmd_buf, 1);
357 nor->cmd_buf[0] = enable << 7;
358 return nor->write_reg(nor, SPINOR_OP_BRWR, nor->cmd_buf, 1);
362 static int spi_nor_sr_ready(struct spi_nor *nor)
364 int sr = read_sr(nor);
369 if (nor->flags & SNOR_F_USE_CLSR && sr & (SR_E_ERR | SR_P_ERR)) {
371 dev_dbg(nor->dev, "Erase Error occurred\n");
373 dev_dbg(nor->dev, "Programming Error occurred\n");
375 nor->write_reg(nor, SPINOR_OP_CLSR, NULL, 0);
379 return !(sr & SR_WIP);
382 static int spi_nor_fsr_ready(struct spi_nor *nor)
384 int fsr = read_fsr(nor);
389 if (fsr & (FSR_E_ERR | FSR_P_ERR)) {
391 dev_err(nor->dev, "Erase operation failed.\n");
393 dev_err(nor->dev, "Program operation failed.\n");
395 if (fsr & FSR_PT_ERR)
397 "Attempted to modify a protected sector.\n");
399 nor->write_reg(nor, SPINOR_OP_CLFSR, NULL, 0);
403 return fsr & FSR_READY;
406 static int spi_nor_ready(struct spi_nor *nor)
410 sr = spi_nor_sr_ready(nor);
413 fsr = nor->flags & SNOR_F_USE_FSR ? spi_nor_fsr_ready(nor) : 1;
420 * Service routine to read status register until ready, or timeout occurs.
421 * Returns non-zero if error.
423 static int spi_nor_wait_till_ready_with_timeout(struct spi_nor *nor,
424 unsigned long timeout)
426 unsigned long timebase;
429 timebase = get_timer(0);
431 while (get_timer(timebase) < timeout) {
432 ret = spi_nor_ready(nor);
439 dev_err(nor->dev, "flash operation timed out\n");
444 static int spi_nor_wait_till_ready(struct spi_nor *nor)
446 return spi_nor_wait_till_ready_with_timeout(nor,
447 DEFAULT_READY_WAIT_JIFFIES);
450 #ifdef CONFIG_SPI_FLASH_BAR
452 * This "clean_bar" is necessary in a situation when one was accessing
453 * spi flash memory > 16 MiB by using Bank Address Register's BA24 bit.
455 * After it the BA24 bit shall be cleared to allow access to correct
456 * memory region after SW reset (by calling "reset" command).
458 * Otherwise, the BA24 bit may be left set and then after reset, the
459 * ROM would read/write/erase SPL from 16 MiB * bank_sel address.
461 static int clean_bar(struct spi_nor *nor)
463 u8 cmd, bank_sel = 0;
465 if (nor->bank_curr == 0)
467 cmd = nor->bank_write_cmd;
471 return nor->write_reg(nor, cmd, &bank_sel, 1);
474 static int write_bar(struct spi_nor *nor, u32 offset)
479 bank_sel = offset / SZ_16M;
480 if (bank_sel == nor->bank_curr)
483 cmd = nor->bank_write_cmd;
485 ret = nor->write_reg(nor, cmd, &bank_sel, 1);
487 debug("SF: fail to write bank register\n");
492 nor->bank_curr = bank_sel;
493 return nor->bank_curr;
496 static int read_bar(struct spi_nor *nor, const struct flash_info *info)
501 switch (JEDEC_MFR(info)) {
502 case SNOR_MFR_SPANSION:
503 nor->bank_read_cmd = SPINOR_OP_BRRD;
504 nor->bank_write_cmd = SPINOR_OP_BRWR;
507 nor->bank_read_cmd = SPINOR_OP_RDEAR;
508 nor->bank_write_cmd = SPINOR_OP_WREAR;
511 ret = nor->read_reg(nor, nor->bank_read_cmd,
514 debug("SF: fail to read bank addr register\n");
517 nor->bank_curr = curr_bank;
524 * Initiate the erasure of a single sector
526 static int spi_nor_erase_sector(struct spi_nor *nor, u32 addr)
528 struct spi_mem_op op =
529 SPI_MEM_OP(SPI_MEM_OP_CMD(nor->erase_opcode, 1),
530 SPI_MEM_OP_ADDR(nor->addr_width, addr, 1),
535 return nor->erase(nor, addr);
538 * Default implementation, if driver doesn't have a specialized HW
541 return spi_mem_exec_op(nor->spi, &op);
545 * Erase an address range on the nor chip. The address range may extend
546 * one or more erase sectors. Return an error is there is a problem erasing.
548 static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
550 struct spi_nor *nor = mtd_to_spi_nor(mtd);
554 dev_dbg(nor->dev, "at 0x%llx, len %lld\n", (long long)instr->addr,
555 (long long)instr->len);
560 div_u64_rem(instr->len, mtd->erasesize, &rem);
568 #ifdef CONFIG_SPI_FLASH_BAR
569 ret = write_bar(nor, addr);
575 ret = spi_nor_erase_sector(nor, addr);
579 addr += mtd->erasesize;
580 len -= mtd->erasesize;
582 ret = spi_nor_wait_till_ready(nor);
588 #ifdef CONFIG_SPI_FLASH_BAR
589 ret = clean_bar(nor);
596 #if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST)
597 /* Write status register and ensure bits in mask match written values */
598 static int write_sr_and_check(struct spi_nor *nor, u8 status_new, u8 mask)
603 ret = write_sr(nor, status_new);
607 ret = spi_nor_wait_till_ready(nor);
615 return ((ret & mask) != (status_new & mask)) ? -EIO : 0;
618 static void stm_get_locked_range(struct spi_nor *nor, u8 sr, loff_t *ofs,
621 struct mtd_info *mtd = &nor->mtd;
622 u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
623 int shift = ffs(mask) - 1;
631 pow = ((sr & mask) ^ mask) >> shift;
632 *len = mtd->size >> pow;
633 if (nor->flags & SNOR_F_HAS_SR_TB && sr & SR_TB)
636 *ofs = mtd->size - *len;
641 * Return 1 if the entire region is locked (if @locked is true) or unlocked (if
642 * @locked is false); 0 otherwise
644 static int stm_check_lock_status_sr(struct spi_nor *nor, loff_t ofs, u64 len,
653 stm_get_locked_range(nor, sr, &lock_offs, &lock_len);
656 /* Requested range is a sub-range of locked range */
657 return (ofs + len <= lock_offs + lock_len) && (ofs >= lock_offs);
659 /* Requested range does not overlap with locked range */
660 return (ofs >= lock_offs + lock_len) || (ofs + len <= lock_offs);
663 static int stm_is_locked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len,
666 return stm_check_lock_status_sr(nor, ofs, len, sr, true);
669 static int stm_is_unlocked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len,
672 return stm_check_lock_status_sr(nor, ofs, len, sr, false);
676 * Lock a region of the flash. Compatible with ST Micro and similar flash.
677 * Supports the block protection bits BP{0,1,2} in the status register
678 * (SR). Does not support these features found in newer SR bitfields:
679 * - SEC: sector/block protect - only handle SEC=0 (block protect)
680 * - CMP: complement protect - only support CMP=0 (range is not complemented)
682 * Support for the following is provided conditionally for some flash:
683 * - TB: top/bottom protect
685 * Sample table portion for 8MB flash (Winbond w25q64fw):
687 * SEC | TB | BP2 | BP1 | BP0 | Prot Length | Protected Portion
688 * --------------------------------------------------------------------------
689 * X | X | 0 | 0 | 0 | NONE | NONE
690 * 0 | 0 | 0 | 0 | 1 | 128 KB | Upper 1/64
691 * 0 | 0 | 0 | 1 | 0 | 256 KB | Upper 1/32
692 * 0 | 0 | 0 | 1 | 1 | 512 KB | Upper 1/16
693 * 0 | 0 | 1 | 0 | 0 | 1 MB | Upper 1/8
694 * 0 | 0 | 1 | 0 | 1 | 2 MB | Upper 1/4
695 * 0 | 0 | 1 | 1 | 0 | 4 MB | Upper 1/2
696 * X | X | 1 | 1 | 1 | 8 MB | ALL
697 * ------|-------|-------|-------|-------|---------------|-------------------
698 * 0 | 1 | 0 | 0 | 1 | 128 KB | Lower 1/64
699 * 0 | 1 | 0 | 1 | 0 | 256 KB | Lower 1/32
700 * 0 | 1 | 0 | 1 | 1 | 512 KB | Lower 1/16
701 * 0 | 1 | 1 | 0 | 0 | 1 MB | Lower 1/8
702 * 0 | 1 | 1 | 0 | 1 | 2 MB | Lower 1/4
703 * 0 | 1 | 1 | 1 | 0 | 4 MB | Lower 1/2
705 * Returns negative on errors, 0 on success.
707 static int stm_lock(struct spi_nor *nor, loff_t ofs, uint64_t len)
709 struct mtd_info *mtd = &nor->mtd;
710 int status_old, status_new;
711 u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
712 u8 shift = ffs(mask) - 1, pow, val;
714 bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB;
717 status_old = read_sr(nor);
721 /* If nothing in our range is unlocked, we don't need to do anything */
722 if (stm_is_locked_sr(nor, ofs, len, status_old))
725 /* If anything below us is unlocked, we can't use 'bottom' protection */
726 if (!stm_is_locked_sr(nor, 0, ofs, status_old))
727 can_be_bottom = false;
729 /* If anything above us is unlocked, we can't use 'top' protection */
730 if (!stm_is_locked_sr(nor, ofs + len, mtd->size - (ofs + len),
734 if (!can_be_bottom && !can_be_top)
737 /* Prefer top, if both are valid */
738 use_top = can_be_top;
740 /* lock_len: length of region that should end up locked */
742 lock_len = mtd->size - ofs;
744 lock_len = ofs + len;
747 * Need smallest pow such that:
749 * 1 / (2^pow) <= (len / size)
751 * so (assuming power-of-2 size) we do:
753 * pow = ceil(log2(size / len)) = log2(size) - floor(log2(len))
755 pow = ilog2(mtd->size) - ilog2(lock_len);
756 val = mask - (pow << shift);
759 /* Don't "lock" with no region! */
763 status_new = (status_old & ~mask & ~SR_TB) | val;
765 /* Disallow further writes if WP pin is asserted */
766 status_new |= SR_SRWD;
771 /* Don't bother if they're the same */
772 if (status_new == status_old)
775 /* Only modify protection if it will not unlock other areas */
776 if ((status_new & mask) < (status_old & mask))
779 return write_sr_and_check(nor, status_new, mask);
783 * Unlock a region of the flash. See stm_lock() for more info
785 * Returns negative on errors, 0 on success.
787 static int stm_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len)
789 struct mtd_info *mtd = &nor->mtd;
790 int status_old, status_new;
791 u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
792 u8 shift = ffs(mask) - 1, pow, val;
794 bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB;
797 status_old = read_sr(nor);
801 /* If nothing in our range is locked, we don't need to do anything */
802 if (stm_is_unlocked_sr(nor, ofs, len, status_old))
805 /* If anything below us is locked, we can't use 'top' protection */
806 if (!stm_is_unlocked_sr(nor, 0, ofs, status_old))
809 /* If anything above us is locked, we can't use 'bottom' protection */
810 if (!stm_is_unlocked_sr(nor, ofs + len, mtd->size - (ofs + len),
812 can_be_bottom = false;
814 if (!can_be_bottom && !can_be_top)
817 /* Prefer top, if both are valid */
818 use_top = can_be_top;
820 /* lock_len: length of region that should remain locked */
822 lock_len = mtd->size - (ofs + len);
827 * Need largest pow such that:
829 * 1 / (2^pow) >= (len / size)
831 * so (assuming power-of-2 size) we do:
833 * pow = floor(log2(size / len)) = log2(size) - ceil(log2(len))
835 pow = ilog2(mtd->size) - order_base_2(lock_len);
837 val = 0; /* fully unlocked */
839 val = mask - (pow << shift);
840 /* Some power-of-two sizes are not supported */
845 status_new = (status_old & ~mask & ~SR_TB) | val;
847 /* Don't protect status register if we're fully unlocked */
849 status_new &= ~SR_SRWD;
854 /* Don't bother if they're the same */
855 if (status_new == status_old)
858 /* Only modify protection if it will not lock other areas */
859 if ((status_new & mask) > (status_old & mask))
862 return write_sr_and_check(nor, status_new, mask);
866 * Check if a region of the flash is (completely) locked. See stm_lock() for
869 * Returns 1 if entire region is locked, 0 if any portion is unlocked, and
870 * negative on errors.
872 static int stm_is_locked(struct spi_nor *nor, loff_t ofs, uint64_t len)
876 status = read_sr(nor);
880 return stm_is_locked_sr(nor, ofs, len, status);
882 #endif /* CONFIG_SPI_FLASH_STMICRO */
884 static const struct flash_info *spi_nor_read_id(struct spi_nor *nor)
887 u8 id[SPI_NOR_MAX_ID_LEN];
888 const struct flash_info *info;
890 tmp = nor->read_reg(nor, SPINOR_OP_RDID, id, SPI_NOR_MAX_ID_LEN);
892 dev_dbg(nor->dev, "error %d reading JEDEC ID\n", tmp);
897 for (; info->name; info++) {
899 if (!memcmp(info->id, id, info->id_len))
904 dev_err(nor->dev, "unrecognized JEDEC id bytes: %02x, %02x, %02x\n",
905 id[0], id[1], id[2]);
906 return ERR_PTR(-ENODEV);
909 static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len,
910 size_t *retlen, u_char *buf)
912 struct spi_nor *nor = mtd_to_spi_nor(mtd);
915 dev_dbg(nor->dev, "from 0x%08x, len %zd\n", (u32)from, len);
919 size_t read_len = len;
921 #ifdef CONFIG_SPI_FLASH_BAR
924 ret = write_bar(nor, addr);
927 remain_len = (SZ_16M * (nor->bank_curr + 1)) - addr;
929 if (len < remain_len)
932 read_len = remain_len;
935 ret = nor->read(nor, addr, read_len, buf);
937 /* We shouldn't see 0-length reads */
952 #ifdef CONFIG_SPI_FLASH_BAR
953 ret = clean_bar(nor);
958 #ifdef CONFIG_SPI_FLASH_SST
960 * sst26 flash series has its own block protection implementation:
961 * 4x - 8 KByte blocks - read & write protection bits - upper addresses
962 * 1x - 32 KByte blocks - write protection bits
963 * rest - 64 KByte blocks - write protection bits
964 * 1x - 32 KByte blocks - write protection bits
965 * 4x - 8 KByte blocks - read & write protection bits - lower addresses
967 * We'll support only per 64k lock/unlock so lower and upper 64 KByte region
968 * will be treated as single block.
970 #define SST26_BPR_8K_NUM 4
971 #define SST26_MAX_BPR_REG_LEN (18 + 1)
972 #define SST26_BOUND_REG_SIZE ((32 + SST26_BPR_8K_NUM * 8) * SZ_1K)
980 static bool sst26_process_bpr(u32 bpr_size, u8 *cmd, u32 bit, enum lock_ctl ctl)
984 cmd[bpr_size - (bit / 8) - 1] |= BIT(bit % 8);
986 case SST26_CTL_UNLOCK:
987 cmd[bpr_size - (bit / 8) - 1] &= ~BIT(bit % 8);
989 case SST26_CTL_CHECK:
990 return !!(cmd[bpr_size - (bit / 8) - 1] & BIT(bit % 8));
997 * Lock, unlock or check lock status of the flash region of the flash (depending
998 * on the lock_ctl value)
1000 static int sst26_lock_ctl(struct spi_nor *nor, loff_t ofs, uint64_t len, enum lock_ctl ctl)
1002 struct mtd_info *mtd = &nor->mtd;
1003 u32 i, bpr_ptr, rptr_64k, lptr_64k, bpr_size;
1004 bool lower_64k = false, upper_64k = false;
1005 u8 bpr_buff[SST26_MAX_BPR_REG_LEN] = {};
1008 /* Check length and offset for 64k alignment */
1009 if ((ofs & (SZ_64K - 1)) || (len & (SZ_64K - 1))) {
1010 dev_err(nor->dev, "length or offset is not 64KiB allighned\n");
1014 if (ofs + len > mtd->size) {
1015 dev_err(nor->dev, "range is more than device size: %#llx + %#llx > %#llx\n",
1016 ofs, len, mtd->size);
1020 /* SST26 family has only 16 Mbit, 32 Mbit and 64 Mbit IC */
1021 if (mtd->size != SZ_2M &&
1022 mtd->size != SZ_4M &&
1026 bpr_size = 2 + (mtd->size / SZ_64K / 8);
1028 ret = nor->read_reg(nor, SPINOR_OP_READ_BPR, bpr_buff, bpr_size);
1030 dev_err(nor->dev, "fail to read block-protection register\n");
1034 rptr_64k = min_t(u32, ofs + len, mtd->size - SST26_BOUND_REG_SIZE);
1035 lptr_64k = max_t(u32, ofs, SST26_BOUND_REG_SIZE);
1037 upper_64k = ((ofs + len) > (mtd->size - SST26_BOUND_REG_SIZE));
1038 lower_64k = (ofs < SST26_BOUND_REG_SIZE);
1040 /* Lower bits in block-protection register are about 64k region */
1041 bpr_ptr = lptr_64k / SZ_64K - 1;
1043 /* Process 64K blocks region */
1044 while (lptr_64k < rptr_64k) {
1045 if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl))
1052 /* 32K and 8K region bits in BPR are after 64k region bits */
1053 bpr_ptr = (mtd->size - 2 * SST26_BOUND_REG_SIZE) / SZ_64K;
1055 /* Process lower 32K block region */
1057 if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl))
1062 /* Process upper 32K block region */
1064 if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl))
1069 /* Process lower 8K block regions */
1070 for (i = 0; i < SST26_BPR_8K_NUM; i++) {
1072 if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl))
1075 /* In 8K area BPR has both read and write protection bits */
1079 /* Process upper 8K block regions */
1080 for (i = 0; i < SST26_BPR_8K_NUM; i++) {
1082 if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl))
1085 /* In 8K area BPR has both read and write protection bits */
1089 /* If we check region status we don't need to write BPR back */
1090 if (ctl == SST26_CTL_CHECK)
1093 ret = nor->write_reg(nor, SPINOR_OP_WRITE_BPR, bpr_buff, bpr_size);
1095 dev_err(nor->dev, "fail to write block-protection register\n");
1102 static int sst26_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len)
1104 return sst26_lock_ctl(nor, ofs, len, SST26_CTL_UNLOCK);
1107 static int sst26_lock(struct spi_nor *nor, loff_t ofs, uint64_t len)
1109 return sst26_lock_ctl(nor, ofs, len, SST26_CTL_LOCK);
1113 * Returns EACCES (positive value) if region is locked, 0 if region is unlocked,
1114 * and negative on errors.
1116 static int sst26_is_locked(struct spi_nor *nor, loff_t ofs, uint64_t len)
1119 * is_locked function is used for check before reading or erasing flash
1120 * region, so offset and length might be not 64k allighned, so adjust
1121 * them to be 64k allighned as sst26_lock_ctl works only with 64k
1122 * allighned regions.
1124 ofs -= ofs & (SZ_64K - 1);
1125 len = len & (SZ_64K - 1) ? (len & ~(SZ_64K - 1)) + SZ_64K : len;
1127 return sst26_lock_ctl(nor, ofs, len, SST26_CTL_CHECK);
1130 static int sst_write_byteprogram(struct spi_nor *nor, loff_t to, size_t len,
1131 size_t *retlen, const u_char *buf)
1136 for (actual = 0; actual < len; actual++) {
1137 nor->program_opcode = SPINOR_OP_BP;
1140 /* write one byte. */
1141 ret = nor->write(nor, to, 1, buf + actual);
1144 ret = spi_nor_wait_till_ready(nor);
1155 static int sst_write(struct mtd_info *mtd, loff_t to, size_t len,
1156 size_t *retlen, const u_char *buf)
1158 struct spi_nor *nor = mtd_to_spi_nor(mtd);
1159 struct spi_slave *spi = nor->spi;
1163 dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len);
1164 if (spi->mode & SPI_TX_BYTE)
1165 return sst_write_byteprogram(nor, to, len, retlen, buf);
1169 nor->sst_write_second = false;
1172 /* Start write from odd address. */
1174 nor->program_opcode = SPINOR_OP_BP;
1176 /* write one byte. */
1177 ret = nor->write(nor, to, 1, buf);
1180 ret = spi_nor_wait_till_ready(nor);
1186 /* Write out most of the data here. */
1187 for (; actual < len - 1; actual += 2) {
1188 nor->program_opcode = SPINOR_OP_AAI_WP;
1190 /* write two bytes. */
1191 ret = nor->write(nor, to, 2, buf + actual);
1194 ret = spi_nor_wait_till_ready(nor);
1198 nor->sst_write_second = true;
1200 nor->sst_write_second = false;
1203 ret = spi_nor_wait_till_ready(nor);
1207 /* Write out trailing byte if it exists. */
1208 if (actual != len) {
1211 nor->program_opcode = SPINOR_OP_BP;
1212 ret = nor->write(nor, to, 1, buf + actual);
1215 ret = spi_nor_wait_till_ready(nor);
1227 * Write an address range to the nor chip. Data must be written in
1228 * FLASH_PAGESIZE chunks. The address range may be any size provided
1229 * it is within the physical boundaries.
1231 static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len,
1232 size_t *retlen, const u_char *buf)
1234 struct spi_nor *nor = mtd_to_spi_nor(mtd);
1235 size_t page_offset, page_remain, i;
1238 #ifdef CONFIG_SPI_FLASH_SST
1239 /* sst nor chips use AAI word program */
1240 if (nor->info->flags & SST_WRITE)
1241 return sst_write(mtd, to, len, retlen, buf);
1244 dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len);
1249 for (i = 0; i < len; ) {
1251 loff_t addr = to + i;
1254 * If page_size is a power of two, the offset can be quickly
1255 * calculated with an AND operation. On the other cases we
1256 * need to do a modulus operation (more expensive).
1258 if (is_power_of_2(nor->page_size)) {
1259 page_offset = addr & (nor->page_size - 1);
1263 page_offset = do_div(aux, nor->page_size);
1265 /* the size of data remaining on the first page */
1266 page_remain = min_t(size_t,
1267 nor->page_size - page_offset, len - i);
1269 #ifdef CONFIG_SPI_FLASH_BAR
1270 ret = write_bar(nor, addr);
1275 ret = nor->write(nor, addr, page_remain, buf + i);
1280 ret = spi_nor_wait_till_ready(nor);
1288 #ifdef CONFIG_SPI_FLASH_BAR
1289 ret = clean_bar(nor);
1294 #ifdef CONFIG_SPI_FLASH_MACRONIX
1296 * macronix_quad_enable() - set QE bit in Status Register.
1297 * @nor: pointer to a 'struct spi_nor'
1299 * Set the Quad Enable (QE) bit in the Status Register.
1301 * bit 6 of the Status Register is the QE bit for Macronix like QSPI memories.
1303 * Return: 0 on success, -errno otherwise.
1305 static int macronix_quad_enable(struct spi_nor *nor)
1312 if (val & SR_QUAD_EN_MX)
1317 write_sr(nor, val | SR_QUAD_EN_MX);
1319 ret = spi_nor_wait_till_ready(nor);
1324 if (!(ret > 0 && (ret & SR_QUAD_EN_MX))) {
1325 dev_err(nor->dev, "Macronix Quad bit not set\n");
1333 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
1335 * Write status Register and configuration register with 2 bytes
1336 * The first byte will be written to the status register, while the
1337 * second byte will be written to the configuration register.
1338 * Return negative if error occurred.
1340 static int write_sr_cr(struct spi_nor *nor, u8 *sr_cr)
1346 ret = nor->write_reg(nor, SPINOR_OP_WRSR, sr_cr, 2);
1349 "error while writing configuration register\n");
1353 ret = spi_nor_wait_till_ready(nor);
1356 "timeout while writing configuration register\n");
1364 * spansion_read_cr_quad_enable() - set QE bit in Configuration Register.
1365 * @nor: pointer to a 'struct spi_nor'
1367 * Set the Quad Enable (QE) bit in the Configuration Register.
1368 * This function should be used with QSPI memories supporting the Read
1369 * Configuration Register (35h) instruction.
1371 * bit 1 of the Configuration Register is the QE bit for Spansion like QSPI
1374 * Return: 0 on success, -errno otherwise.
1376 static int spansion_read_cr_quad_enable(struct spi_nor *nor)
1381 /* Check current Quad Enable bit value. */
1385 "error while reading configuration register\n");
1389 if (ret & CR_QUAD_EN_SPAN)
1392 sr_cr[1] = ret | CR_QUAD_EN_SPAN;
1394 /* Keep the current value of the Status Register. */
1397 dev_dbg(nor->dev, "error while reading status register\n");
1402 ret = write_sr_cr(nor, sr_cr);
1406 /* Read back and check it. */
1408 if (!(ret > 0 && (ret & CR_QUAD_EN_SPAN))) {
1409 dev_dbg(nor->dev, "Spansion Quad bit not set\n");
1416 #if CONFIG_IS_ENABLED(SPI_FLASH_SFDP_SUPPORT)
1418 * spansion_no_read_cr_quad_enable() - set QE bit in Configuration Register.
1419 * @nor: pointer to a 'struct spi_nor'
1421 * Set the Quad Enable (QE) bit in the Configuration Register.
1422 * This function should be used with QSPI memories not supporting the Read
1423 * Configuration Register (35h) instruction.
1425 * bit 1 of the Configuration Register is the QE bit for Spansion like QSPI
1428 * Return: 0 on success, -errno otherwise.
1430 static int spansion_no_read_cr_quad_enable(struct spi_nor *nor)
1435 /* Keep the current value of the Status Register. */
1438 dev_dbg(nor->dev, "error while reading status register\n");
1442 sr_cr[1] = CR_QUAD_EN_SPAN;
1444 return write_sr_cr(nor, sr_cr);
1447 #endif /* CONFIG_SPI_FLASH_SFDP_SUPPORT */
1448 #endif /* CONFIG_SPI_FLASH_SPANSION */
1450 struct spi_nor_read_command {
1454 enum spi_nor_protocol proto;
1457 struct spi_nor_pp_command {
1459 enum spi_nor_protocol proto;
1462 enum spi_nor_read_command_index {
1465 SNOR_CMD_READ_1_1_1_DTR,
1468 SNOR_CMD_READ_1_1_2,
1469 SNOR_CMD_READ_1_2_2,
1470 SNOR_CMD_READ_2_2_2,
1471 SNOR_CMD_READ_1_2_2_DTR,
1474 SNOR_CMD_READ_1_1_4,
1475 SNOR_CMD_READ_1_4_4,
1476 SNOR_CMD_READ_4_4_4,
1477 SNOR_CMD_READ_1_4_4_DTR,
1480 SNOR_CMD_READ_1_1_8,
1481 SNOR_CMD_READ_1_8_8,
1482 SNOR_CMD_READ_8_8_8,
1483 SNOR_CMD_READ_1_8_8_DTR,
1488 enum spi_nor_pp_command_index {
1504 struct spi_nor_flash_parameter {
1508 struct spi_nor_hwcaps hwcaps;
1509 struct spi_nor_read_command reads[SNOR_CMD_READ_MAX];
1510 struct spi_nor_pp_command page_programs[SNOR_CMD_PP_MAX];
1512 int (*quad_enable)(struct spi_nor *nor);
1516 spi_nor_set_read_settings(struct spi_nor_read_command *read,
1520 enum spi_nor_protocol proto)
1522 read->num_mode_clocks = num_mode_clocks;
1523 read->num_wait_states = num_wait_states;
1524 read->opcode = opcode;
1525 read->proto = proto;
1529 spi_nor_set_pp_settings(struct spi_nor_pp_command *pp,
1531 enum spi_nor_protocol proto)
1533 pp->opcode = opcode;
1537 #if CONFIG_IS_ENABLED(SPI_FLASH_SFDP_SUPPORT)
1539 * Serial Flash Discoverable Parameters (SFDP) parsing.
1543 * spi_nor_read_sfdp() - read Serial Flash Discoverable Parameters.
1544 * @nor: pointer to a 'struct spi_nor'
1545 * @addr: offset in the SFDP area to start reading data from
1546 * @len: number of bytes to read
1547 * @buf: buffer where the SFDP data are copied into (dma-safe memory)
1549 * Whatever the actual numbers of bytes for address and dummy cycles are
1550 * for (Fast) Read commands, the Read SFDP (5Ah) instruction is always
1551 * followed by a 3-byte address and 8 dummy clock cycles.
1553 * Return: 0 on success, -errno otherwise.
1555 static int spi_nor_read_sfdp(struct spi_nor *nor, u32 addr,
1556 size_t len, void *buf)
1558 u8 addr_width, read_opcode, read_dummy;
1561 read_opcode = nor->read_opcode;
1562 addr_width = nor->addr_width;
1563 read_dummy = nor->read_dummy;
1565 nor->read_opcode = SPINOR_OP_RDSFDP;
1566 nor->addr_width = 3;
1567 nor->read_dummy = 8;
1570 ret = nor->read(nor, addr, len, (u8 *)buf);
1571 if (!ret || ret > len) {
1585 nor->read_opcode = read_opcode;
1586 nor->addr_width = addr_width;
1587 nor->read_dummy = read_dummy;
1592 struct sfdp_parameter_header {
1596 u8 length; /* in double words */
1597 u8 parameter_table_pointer[3]; /* byte address */
1601 #define SFDP_PARAM_HEADER_ID(p) (((p)->id_msb << 8) | (p)->id_lsb)
1602 #define SFDP_PARAM_HEADER_PTP(p) \
1603 (((p)->parameter_table_pointer[2] << 16) | \
1604 ((p)->parameter_table_pointer[1] << 8) | \
1605 ((p)->parameter_table_pointer[0] << 0))
1607 #define SFDP_BFPT_ID 0xff00 /* Basic Flash Parameter Table */
1608 #define SFDP_SECTOR_MAP_ID 0xff81 /* Sector Map Table */
1609 #define SFDP_SST_ID 0x01bf /* Manufacturer specific Table */
1611 #define SFDP_SIGNATURE 0x50444653U
1612 #define SFDP_JESD216_MAJOR 1
1613 #define SFDP_JESD216_MINOR 0
1614 #define SFDP_JESD216A_MINOR 5
1615 #define SFDP_JESD216B_MINOR 6
1617 struct sfdp_header {
1618 u32 signature; /* Ox50444653U <=> "SFDP" */
1621 u8 nph; /* 0-base number of parameter headers */
1624 /* Basic Flash Parameter Table. */
1625 struct sfdp_parameter_header bfpt_header;
1628 /* Basic Flash Parameter Table */
1631 * JESD216 rev B defines a Basic Flash Parameter Table of 16 DWORDs.
1632 * They are indexed from 1 but C arrays are indexed from 0.
1634 #define BFPT_DWORD(i) ((i) - 1)
1635 #define BFPT_DWORD_MAX 16
1637 /* The first version of JESB216 defined only 9 DWORDs. */
1638 #define BFPT_DWORD_MAX_JESD216 9
1641 #define BFPT_DWORD1_FAST_READ_1_1_2 BIT(16)
1642 #define BFPT_DWORD1_ADDRESS_BYTES_MASK GENMASK(18, 17)
1643 #define BFPT_DWORD1_ADDRESS_BYTES_3_ONLY (0x0UL << 17)
1644 #define BFPT_DWORD1_ADDRESS_BYTES_3_OR_4 (0x1UL << 17)
1645 #define BFPT_DWORD1_ADDRESS_BYTES_4_ONLY (0x2UL << 17)
1646 #define BFPT_DWORD1_DTR BIT(19)
1647 #define BFPT_DWORD1_FAST_READ_1_2_2 BIT(20)
1648 #define BFPT_DWORD1_FAST_READ_1_4_4 BIT(21)
1649 #define BFPT_DWORD1_FAST_READ_1_1_4 BIT(22)
1652 #define BFPT_DWORD5_FAST_READ_2_2_2 BIT(0)
1653 #define BFPT_DWORD5_FAST_READ_4_4_4 BIT(4)
1656 #define BFPT_DWORD11_PAGE_SIZE_SHIFT 4
1657 #define BFPT_DWORD11_PAGE_SIZE_MASK GENMASK(7, 4)
1662 * (from JESD216 rev B)
1663 * Quad Enable Requirements (QER):
1664 * - 000b: Device does not have a QE bit. Device detects 1-1-4 and 1-4-4
1665 * reads based on instruction. DQ3/HOLD# functions are hold during
1666 * instruction phase.
1667 * - 001b: QE is bit 1 of status register 2. It is set via Write Status with
1668 * two data bytes where bit 1 of the second byte is one.
1670 * Writing only one byte to the status register has the side-effect of
1671 * clearing status register 2, including the QE bit. The 100b code is
1672 * used if writing one byte to the status register does not modify
1673 * status register 2.
1674 * - 010b: QE is bit 6 of status register 1. It is set via Write Status with
1675 * one data byte where bit 6 is one.
1677 * - 011b: QE is bit 7 of status register 2. It is set via Write status
1678 * register 2 instruction 3Eh with one data byte where bit 7 is one.
1680 * The status register 2 is read using instruction 3Fh.
1681 * - 100b: QE is bit 1 of status register 2. It is set via Write Status with
1682 * two data bytes where bit 1 of the second byte is one.
1684 * In contrast to the 001b code, writing one byte to the status
1685 * register does not modify status register 2.
1686 * - 101b: QE is bit 1 of status register 2. Status register 1 is read using
1687 * Read Status instruction 05h. Status register2 is read using
1688 * instruction 35h. QE is set via Writ Status instruction 01h with
1689 * two data bytes where bit 1 of the second byte is one.
1692 #define BFPT_DWORD15_QER_MASK GENMASK(22, 20)
1693 #define BFPT_DWORD15_QER_NONE (0x0UL << 20) /* Micron */
1694 #define BFPT_DWORD15_QER_SR2_BIT1_BUGGY (0x1UL << 20)
1695 #define BFPT_DWORD15_QER_SR1_BIT6 (0x2UL << 20) /* Macronix */
1696 #define BFPT_DWORD15_QER_SR2_BIT7 (0x3UL << 20)
1697 #define BFPT_DWORD15_QER_SR2_BIT1_NO_RD (0x4UL << 20)
1698 #define BFPT_DWORD15_QER_SR2_BIT1 (0x5UL << 20) /* Spansion */
1701 u32 dwords[BFPT_DWORD_MAX];
1704 /* Fast Read settings. */
1707 spi_nor_set_read_settings_from_bfpt(struct spi_nor_read_command *read,
1709 enum spi_nor_protocol proto)
1711 read->num_mode_clocks = (half >> 5) & 0x07;
1712 read->num_wait_states = (half >> 0) & 0x1f;
1713 read->opcode = (half >> 8) & 0xff;
1714 read->proto = proto;
1717 struct sfdp_bfpt_read {
1718 /* The Fast Read x-y-z hardware capability in params->hwcaps.mask. */
1722 * The <supported_bit> bit in <supported_dword> BFPT DWORD tells us
1723 * whether the Fast Read x-y-z command is supported.
1725 u32 supported_dword;
1729 * The half-word at offset <setting_shift> in <setting_dword> BFPT DWORD
1730 * encodes the op code, the number of mode clocks and the number of wait
1731 * states to be used by Fast Read x-y-z command.
1736 /* The SPI protocol for this Fast Read x-y-z command. */
1737 enum spi_nor_protocol proto;
1740 static const struct sfdp_bfpt_read sfdp_bfpt_reads[] = {
1741 /* Fast Read 1-1-2 */
1743 SNOR_HWCAPS_READ_1_1_2,
1744 BFPT_DWORD(1), BIT(16), /* Supported bit */
1745 BFPT_DWORD(4), 0, /* Settings */
1749 /* Fast Read 1-2-2 */
1751 SNOR_HWCAPS_READ_1_2_2,
1752 BFPT_DWORD(1), BIT(20), /* Supported bit */
1753 BFPT_DWORD(4), 16, /* Settings */
1757 /* Fast Read 2-2-2 */
1759 SNOR_HWCAPS_READ_2_2_2,
1760 BFPT_DWORD(5), BIT(0), /* Supported bit */
1761 BFPT_DWORD(6), 16, /* Settings */
1765 /* Fast Read 1-1-4 */
1767 SNOR_HWCAPS_READ_1_1_4,
1768 BFPT_DWORD(1), BIT(22), /* Supported bit */
1769 BFPT_DWORD(3), 16, /* Settings */
1773 /* Fast Read 1-4-4 */
1775 SNOR_HWCAPS_READ_1_4_4,
1776 BFPT_DWORD(1), BIT(21), /* Supported bit */
1777 BFPT_DWORD(3), 0, /* Settings */
1781 /* Fast Read 4-4-4 */
1783 SNOR_HWCAPS_READ_4_4_4,
1784 BFPT_DWORD(5), BIT(4), /* Supported bit */
1785 BFPT_DWORD(7), 16, /* Settings */
1790 struct sfdp_bfpt_erase {
1792 * The half-word at offset <shift> in DWORD <dwoard> encodes the
1793 * op code and erase sector size to be used by Sector Erase commands.
1799 static const struct sfdp_bfpt_erase sfdp_bfpt_erases[] = {
1800 /* Erase Type 1 in DWORD8 bits[15:0] */
1803 /* Erase Type 2 in DWORD8 bits[31:16] */
1804 {BFPT_DWORD(8), 16},
1806 /* Erase Type 3 in DWORD9 bits[15:0] */
1809 /* Erase Type 4 in DWORD9 bits[31:16] */
1810 {BFPT_DWORD(9), 16},
1813 static int spi_nor_hwcaps_read2cmd(u32 hwcaps);
1816 * spi_nor_parse_bfpt() - read and parse the Basic Flash Parameter Table.
1817 * @nor: pointer to a 'struct spi_nor'
1818 * @bfpt_header: pointer to the 'struct sfdp_parameter_header' describing
1819 * the Basic Flash Parameter Table length and version
1820 * @params: pointer to the 'struct spi_nor_flash_parameter' to be
1823 * The Basic Flash Parameter Table is the main and only mandatory table as
1824 * defined by the SFDP (JESD216) specification.
1825 * It provides us with the total size (memory density) of the data array and
1826 * the number of address bytes for Fast Read, Page Program and Sector Erase
1828 * For Fast READ commands, it also gives the number of mode clock cycles and
1829 * wait states (regrouped in the number of dummy clock cycles) for each
1830 * supported instruction op code.
1831 * For Page Program, the page size is now available since JESD216 rev A, however
1832 * the supported instruction op codes are still not provided.
1833 * For Sector Erase commands, this table stores the supported instruction op
1834 * codes and the associated sector sizes.
1835 * Finally, the Quad Enable Requirements (QER) are also available since JESD216
1836 * rev A. The QER bits encode the manufacturer dependent procedure to be
1837 * executed to set the Quad Enable (QE) bit in some internal register of the
1838 * Quad SPI memory. Indeed the QE bit, when it exists, must be set before
1839 * sending any Quad SPI command to the memory. Actually, setting the QE bit
1840 * tells the memory to reassign its WP# and HOLD#/RESET# pins to functions IO2
1841 * and IO3 hence enabling 4 (Quad) I/O lines.
1843 * Return: 0 on success, -errno otherwise.
1845 static int spi_nor_parse_bfpt(struct spi_nor *nor,
1846 const struct sfdp_parameter_header *bfpt_header,
1847 struct spi_nor_flash_parameter *params)
1849 struct mtd_info *mtd = &nor->mtd;
1850 struct sfdp_bfpt bfpt;
1856 /* JESD216 Basic Flash Parameter Table length is at least 9 DWORDs. */
1857 if (bfpt_header->length < BFPT_DWORD_MAX_JESD216)
1860 /* Read the Basic Flash Parameter Table. */
1861 len = min_t(size_t, sizeof(bfpt),
1862 bfpt_header->length * sizeof(u32));
1863 addr = SFDP_PARAM_HEADER_PTP(bfpt_header);
1864 memset(&bfpt, 0, sizeof(bfpt));
1865 err = spi_nor_read_sfdp(nor, addr, len, &bfpt);
1869 /* Fix endianness of the BFPT DWORDs. */
1870 for (i = 0; i < BFPT_DWORD_MAX; i++)
1871 bfpt.dwords[i] = le32_to_cpu(bfpt.dwords[i]);
1873 /* Number of address bytes. */
1874 switch (bfpt.dwords[BFPT_DWORD(1)] & BFPT_DWORD1_ADDRESS_BYTES_MASK) {
1875 case BFPT_DWORD1_ADDRESS_BYTES_3_ONLY:
1876 nor->addr_width = 3;
1879 case BFPT_DWORD1_ADDRESS_BYTES_4_ONLY:
1880 nor->addr_width = 4;
1887 /* Flash Memory Density (in bits). */
1888 params->size = bfpt.dwords[BFPT_DWORD(2)];
1889 if (params->size & BIT(31)) {
1890 params->size &= ~BIT(31);
1893 * Prevent overflows on params->size. Anyway, a NOR of 2^64
1894 * bits is unlikely to exist so this error probably means
1895 * the BFPT we are reading is corrupted/wrong.
1897 if (params->size > 63)
1900 params->size = 1ULL << params->size;
1904 params->size >>= 3; /* Convert to bytes. */
1906 /* Fast Read settings. */
1907 for (i = 0; i < ARRAY_SIZE(sfdp_bfpt_reads); i++) {
1908 const struct sfdp_bfpt_read *rd = &sfdp_bfpt_reads[i];
1909 struct spi_nor_read_command *read;
1911 if (!(bfpt.dwords[rd->supported_dword] & rd->supported_bit)) {
1912 params->hwcaps.mask &= ~rd->hwcaps;
1916 params->hwcaps.mask |= rd->hwcaps;
1917 cmd = spi_nor_hwcaps_read2cmd(rd->hwcaps);
1918 read = ¶ms->reads[cmd];
1919 half = bfpt.dwords[rd->settings_dword] >> rd->settings_shift;
1920 spi_nor_set_read_settings_from_bfpt(read, half, rd->proto);
1923 /* Sector Erase settings. */
1924 for (i = 0; i < ARRAY_SIZE(sfdp_bfpt_erases); i++) {
1925 const struct sfdp_bfpt_erase *er = &sfdp_bfpt_erases[i];
1929 half = bfpt.dwords[er->dword] >> er->shift;
1930 erasesize = half & 0xff;
1932 /* erasesize == 0 means this Erase Type is not supported. */
1936 erasesize = 1U << erasesize;
1937 opcode = (half >> 8) & 0xff;
1938 #ifdef CONFIG_SPI_FLASH_USE_4K_SECTORS
1939 if (erasesize == SZ_4K) {
1940 nor->erase_opcode = opcode;
1941 mtd->erasesize = erasesize;
1945 if (!mtd->erasesize || mtd->erasesize < erasesize) {
1946 nor->erase_opcode = opcode;
1947 mtd->erasesize = erasesize;
1951 /* Stop here if not JESD216 rev A or later. */
1952 if (bfpt_header->length < BFPT_DWORD_MAX)
1955 /* Page size: this field specifies 'N' so the page size = 2^N bytes. */
1956 params->page_size = bfpt.dwords[BFPT_DWORD(11)];
1957 params->page_size &= BFPT_DWORD11_PAGE_SIZE_MASK;
1958 params->page_size >>= BFPT_DWORD11_PAGE_SIZE_SHIFT;
1959 params->page_size = 1U << params->page_size;
1961 /* Quad Enable Requirements. */
1962 switch (bfpt.dwords[BFPT_DWORD(15)] & BFPT_DWORD15_QER_MASK) {
1963 case BFPT_DWORD15_QER_NONE:
1964 params->quad_enable = NULL;
1966 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
1967 case BFPT_DWORD15_QER_SR2_BIT1_BUGGY:
1968 case BFPT_DWORD15_QER_SR2_BIT1_NO_RD:
1969 params->quad_enable = spansion_no_read_cr_quad_enable;
1972 #ifdef CONFIG_SPI_FLASH_MACRONIX
1973 case BFPT_DWORD15_QER_SR1_BIT6:
1974 params->quad_enable = macronix_quad_enable;
1977 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
1978 case BFPT_DWORD15_QER_SR2_BIT1:
1979 params->quad_enable = spansion_read_cr_quad_enable;
1990 * spi_nor_parse_microchip_sfdp() - parse the Microchip manufacturer specific
1992 * @nor: pointer to a 'struct spi_nor'.
1993 * @param_header: pointer to the SFDP parameter header.
1995 * Return: 0 on success, -errno otherwise.
1998 spi_nor_parse_microchip_sfdp(struct spi_nor *nor,
1999 const struct sfdp_parameter_header *param_header)
2005 size = param_header->length * sizeof(u32);
2006 addr = SFDP_PARAM_HEADER_PTP(param_header);
2008 nor->manufacturer_sfdp = devm_kmalloc(nor->dev, size, GFP_KERNEL);
2009 if (!nor->manufacturer_sfdp)
2012 ret = spi_nor_read_sfdp(nor, addr, size, nor->manufacturer_sfdp);
2018 * spi_nor_parse_sfdp() - parse the Serial Flash Discoverable Parameters.
2019 * @nor: pointer to a 'struct spi_nor'
2020 * @params: pointer to the 'struct spi_nor_flash_parameter' to be
2023 * The Serial Flash Discoverable Parameters are described by the JEDEC JESD216
2024 * specification. This is a standard which tends to supported by almost all
2025 * (Q)SPI memory manufacturers. Those hard-coded tables allow us to learn at
2026 * runtime the main parameters needed to perform basic SPI flash operations such
2027 * as Fast Read, Page Program or Sector Erase commands.
2029 * Return: 0 on success, -errno otherwise.
2031 static int spi_nor_parse_sfdp(struct spi_nor *nor,
2032 struct spi_nor_flash_parameter *params)
2034 const struct sfdp_parameter_header *param_header, *bfpt_header;
2035 struct sfdp_parameter_header *param_headers = NULL;
2036 struct sfdp_header header;
2040 /* Get the SFDP header. */
2041 err = spi_nor_read_sfdp(nor, 0, sizeof(header), &header);
2045 /* Check the SFDP header version. */
2046 if (le32_to_cpu(header.signature) != SFDP_SIGNATURE ||
2047 header.major != SFDP_JESD216_MAJOR)
2051 * Verify that the first and only mandatory parameter header is a
2052 * Basic Flash Parameter Table header as specified in JESD216.
2054 bfpt_header = &header.bfpt_header;
2055 if (SFDP_PARAM_HEADER_ID(bfpt_header) != SFDP_BFPT_ID ||
2056 bfpt_header->major != SFDP_JESD216_MAJOR)
2060 * Allocate memory then read all parameter headers with a single
2061 * Read SFDP command. These parameter headers will actually be parsed
2062 * twice: a first time to get the latest revision of the basic flash
2063 * parameter table, then a second time to handle the supported optional
2065 * Hence we read the parameter headers once for all to reduce the
2066 * processing time. Also we use kmalloc() instead of devm_kmalloc()
2067 * because we don't need to keep these parameter headers: the allocated
2068 * memory is always released with kfree() before exiting this function.
2071 psize = header.nph * sizeof(*param_headers);
2073 param_headers = kmalloc(psize, GFP_KERNEL);
2077 err = spi_nor_read_sfdp(nor, sizeof(header),
2078 psize, param_headers);
2081 "failed to read SFDP parameter headers\n");
2087 * Check other parameter headers to get the latest revision of
2088 * the basic flash parameter table.
2090 for (i = 0; i < header.nph; i++) {
2091 param_header = ¶m_headers[i];
2093 if (SFDP_PARAM_HEADER_ID(param_header) == SFDP_BFPT_ID &&
2094 param_header->major == SFDP_JESD216_MAJOR &&
2095 (param_header->minor > bfpt_header->minor ||
2096 (param_header->minor == bfpt_header->minor &&
2097 param_header->length > bfpt_header->length)))
2098 bfpt_header = param_header;
2101 err = spi_nor_parse_bfpt(nor, bfpt_header, params);
2105 /* Parse other parameter headers. */
2106 for (i = 0; i < header.nph; i++) {
2107 param_header = ¶m_headers[i];
2109 switch (SFDP_PARAM_HEADER_ID(param_header)) {
2110 case SFDP_SECTOR_MAP_ID:
2112 "non-uniform erase sector maps are not supported yet.\n");
2116 err = spi_nor_parse_microchip_sfdp(nor, param_header);
2125 "Failed to parse optional parameter table: %04x\n",
2126 SFDP_PARAM_HEADER_ID(param_header));
2128 * Let's not drop all information we extracted so far
2129 * if optional table parsers fail. In case of failing,
2130 * each optional parser is responsible to roll back to
2131 * the previously known spi_nor data.
2138 kfree(param_headers);
2142 static int spi_nor_parse_sfdp(struct spi_nor *nor,
2143 struct spi_nor_flash_parameter *params)
2147 #endif /* SPI_FLASH_SFDP_SUPPORT */
2149 static int spi_nor_init_params(struct spi_nor *nor,
2150 const struct flash_info *info,
2151 struct spi_nor_flash_parameter *params)
2153 /* Set legacy flash parameters as default. */
2154 memset(params, 0, sizeof(*params));
2156 /* Set SPI NOR sizes. */
2157 params->size = info->sector_size * info->n_sectors;
2158 params->page_size = info->page_size;
2160 /* (Fast) Read settings. */
2161 params->hwcaps.mask |= SNOR_HWCAPS_READ;
2162 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ],
2163 0, 0, SPINOR_OP_READ,
2166 if (!(info->flags & SPI_NOR_NO_FR)) {
2167 params->hwcaps.mask |= SNOR_HWCAPS_READ_FAST;
2168 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_FAST],
2169 0, 8, SPINOR_OP_READ_FAST,
2173 if (info->flags & SPI_NOR_DUAL_READ) {
2174 params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_2;
2175 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_2],
2176 0, 8, SPINOR_OP_READ_1_1_2,
2180 if (info->flags & SPI_NOR_QUAD_READ) {
2181 params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4;
2182 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_4],
2183 0, 8, SPINOR_OP_READ_1_1_4,
2187 if (info->flags & SPI_NOR_OCTAL_READ) {
2188 params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_8;
2189 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_8],
2190 0, 8, SPINOR_OP_READ_1_1_8,
2194 /* Page Program settings. */
2195 params->hwcaps.mask |= SNOR_HWCAPS_PP;
2196 spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP],
2197 SPINOR_OP_PP, SNOR_PROTO_1_1_1);
2199 if (info->flags & SPI_NOR_QUAD_READ) {
2200 params->hwcaps.mask |= SNOR_HWCAPS_PP_1_1_4;
2201 spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP_1_1_4],
2202 SPINOR_OP_PP_1_1_4, SNOR_PROTO_1_1_4);
2205 /* Select the procedure to set the Quad Enable bit. */
2206 if (params->hwcaps.mask & (SNOR_HWCAPS_READ_QUAD |
2207 SNOR_HWCAPS_PP_QUAD)) {
2208 switch (JEDEC_MFR(info)) {
2209 #ifdef CONFIG_SPI_FLASH_MACRONIX
2210 case SNOR_MFR_MACRONIX:
2211 params->quad_enable = macronix_quad_enable;
2215 case SNOR_MFR_MICRON:
2219 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
2220 /* Kept only for backward compatibility purpose. */
2221 params->quad_enable = spansion_read_cr_quad_enable;
2227 /* Override the parameters with data read from SFDP tables. */
2228 nor->addr_width = 0;
2229 nor->mtd.erasesize = 0;
2230 if ((info->flags & (SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)) &&
2231 !(info->flags & SPI_NOR_SKIP_SFDP)) {
2232 struct spi_nor_flash_parameter sfdp_params;
2234 memcpy(&sfdp_params, params, sizeof(sfdp_params));
2235 if (spi_nor_parse_sfdp(nor, &sfdp_params)) {
2236 nor->addr_width = 0;
2237 nor->mtd.erasesize = 0;
2239 memcpy(params, &sfdp_params, sizeof(*params));
2246 static int spi_nor_hwcaps2cmd(u32 hwcaps, const int table[][2], size_t size)
2250 for (i = 0; i < size; i++)
2251 if (table[i][0] == (int)hwcaps)
2257 static int spi_nor_hwcaps_read2cmd(u32 hwcaps)
2259 static const int hwcaps_read2cmd[][2] = {
2260 { SNOR_HWCAPS_READ, SNOR_CMD_READ },
2261 { SNOR_HWCAPS_READ_FAST, SNOR_CMD_READ_FAST },
2262 { SNOR_HWCAPS_READ_1_1_1_DTR, SNOR_CMD_READ_1_1_1_DTR },
2263 { SNOR_HWCAPS_READ_1_1_2, SNOR_CMD_READ_1_1_2 },
2264 { SNOR_HWCAPS_READ_1_2_2, SNOR_CMD_READ_1_2_2 },
2265 { SNOR_HWCAPS_READ_2_2_2, SNOR_CMD_READ_2_2_2 },
2266 { SNOR_HWCAPS_READ_1_2_2_DTR, SNOR_CMD_READ_1_2_2_DTR },
2267 { SNOR_HWCAPS_READ_1_1_4, SNOR_CMD_READ_1_1_4 },
2268 { SNOR_HWCAPS_READ_1_4_4, SNOR_CMD_READ_1_4_4 },
2269 { SNOR_HWCAPS_READ_4_4_4, SNOR_CMD_READ_4_4_4 },
2270 { SNOR_HWCAPS_READ_1_4_4_DTR, SNOR_CMD_READ_1_4_4_DTR },
2271 { SNOR_HWCAPS_READ_1_1_8, SNOR_CMD_READ_1_1_8 },
2272 { SNOR_HWCAPS_READ_1_8_8, SNOR_CMD_READ_1_8_8 },
2273 { SNOR_HWCAPS_READ_8_8_8, SNOR_CMD_READ_8_8_8 },
2274 { SNOR_HWCAPS_READ_1_8_8_DTR, SNOR_CMD_READ_1_8_8_DTR },
2277 return spi_nor_hwcaps2cmd(hwcaps, hwcaps_read2cmd,
2278 ARRAY_SIZE(hwcaps_read2cmd));
2281 static int spi_nor_hwcaps_pp2cmd(u32 hwcaps)
2283 static const int hwcaps_pp2cmd[][2] = {
2284 { SNOR_HWCAPS_PP, SNOR_CMD_PP },
2285 { SNOR_HWCAPS_PP_1_1_4, SNOR_CMD_PP_1_1_4 },
2286 { SNOR_HWCAPS_PP_1_4_4, SNOR_CMD_PP_1_4_4 },
2287 { SNOR_HWCAPS_PP_4_4_4, SNOR_CMD_PP_4_4_4 },
2288 { SNOR_HWCAPS_PP_1_1_8, SNOR_CMD_PP_1_1_8 },
2289 { SNOR_HWCAPS_PP_1_8_8, SNOR_CMD_PP_1_8_8 },
2290 { SNOR_HWCAPS_PP_8_8_8, SNOR_CMD_PP_8_8_8 },
2293 return spi_nor_hwcaps2cmd(hwcaps, hwcaps_pp2cmd,
2294 ARRAY_SIZE(hwcaps_pp2cmd));
2297 static int spi_nor_select_read(struct spi_nor *nor,
2298 const struct spi_nor_flash_parameter *params,
2301 int cmd, best_match = fls(shared_hwcaps & SNOR_HWCAPS_READ_MASK) - 1;
2302 const struct spi_nor_read_command *read;
2307 cmd = spi_nor_hwcaps_read2cmd(BIT(best_match));
2311 read = ¶ms->reads[cmd];
2312 nor->read_opcode = read->opcode;
2313 nor->read_proto = read->proto;
2316 * In the spi-nor framework, we don't need to make the difference
2317 * between mode clock cycles and wait state clock cycles.
2318 * Indeed, the value of the mode clock cycles is used by a QSPI
2319 * flash memory to know whether it should enter or leave its 0-4-4
2320 * (Continuous Read / XIP) mode.
2321 * eXecution In Place is out of the scope of the mtd sub-system.
2322 * Hence we choose to merge both mode and wait state clock cycles
2323 * into the so called dummy clock cycles.
2325 nor->read_dummy = read->num_mode_clocks + read->num_wait_states;
2329 static int spi_nor_select_pp(struct spi_nor *nor,
2330 const struct spi_nor_flash_parameter *params,
2333 int cmd, best_match = fls(shared_hwcaps & SNOR_HWCAPS_PP_MASK) - 1;
2334 const struct spi_nor_pp_command *pp;
2339 cmd = spi_nor_hwcaps_pp2cmd(BIT(best_match));
2343 pp = ¶ms->page_programs[cmd];
2344 nor->program_opcode = pp->opcode;
2345 nor->write_proto = pp->proto;
2349 static int spi_nor_select_erase(struct spi_nor *nor,
2350 const struct flash_info *info)
2352 struct mtd_info *mtd = &nor->mtd;
2354 /* Do nothing if already configured from SFDP. */
2358 #ifdef CONFIG_SPI_FLASH_USE_4K_SECTORS
2359 /* prefer "small sector" erase if possible */
2360 if (info->flags & SECT_4K) {
2361 nor->erase_opcode = SPINOR_OP_BE_4K;
2362 mtd->erasesize = 4096;
2363 } else if (info->flags & SECT_4K_PMC) {
2364 nor->erase_opcode = SPINOR_OP_BE_4K_PMC;
2365 mtd->erasesize = 4096;
2369 nor->erase_opcode = SPINOR_OP_SE;
2370 mtd->erasesize = info->sector_size;
2375 static int spi_nor_setup(struct spi_nor *nor, const struct flash_info *info,
2376 const struct spi_nor_flash_parameter *params,
2377 const struct spi_nor_hwcaps *hwcaps)
2379 u32 ignored_mask, shared_mask;
2380 bool enable_quad_io;
2384 * Keep only the hardware capabilities supported by both the SPI
2385 * controller and the SPI flash memory.
2387 shared_mask = hwcaps->mask & params->hwcaps.mask;
2389 /* SPI n-n-n protocols are not supported yet. */
2390 ignored_mask = (SNOR_HWCAPS_READ_2_2_2 |
2391 SNOR_HWCAPS_READ_4_4_4 |
2392 SNOR_HWCAPS_READ_8_8_8 |
2393 SNOR_HWCAPS_PP_4_4_4 |
2394 SNOR_HWCAPS_PP_8_8_8);
2395 if (shared_mask & ignored_mask) {
2397 "SPI n-n-n protocols are not supported yet.\n");
2398 shared_mask &= ~ignored_mask;
2401 /* Select the (Fast) Read command. */
2402 err = spi_nor_select_read(nor, params, shared_mask);
2405 "can't select read settings supported by both the SPI controller and memory.\n");
2409 /* Select the Page Program command. */
2410 err = spi_nor_select_pp(nor, params, shared_mask);
2413 "can't select write settings supported by both the SPI controller and memory.\n");
2417 /* Select the Sector Erase command. */
2418 err = spi_nor_select_erase(nor, info);
2421 "can't select erase settings supported by both the SPI controller and memory.\n");
2425 /* Enable Quad I/O if needed. */
2426 enable_quad_io = (spi_nor_get_protocol_width(nor->read_proto) == 4 ||
2427 spi_nor_get_protocol_width(nor->write_proto) == 4);
2428 if (enable_quad_io && params->quad_enable)
2429 nor->quad_enable = params->quad_enable;
2431 nor->quad_enable = NULL;
2436 static int spi_nor_init(struct spi_nor *nor)
2441 * Atmel, SST, Intel/Numonyx, and others serial NOR tend to power up
2442 * with the software protection bits set
2444 if (JEDEC_MFR(nor->info) == SNOR_MFR_ATMEL ||
2445 JEDEC_MFR(nor->info) == SNOR_MFR_INTEL ||
2446 JEDEC_MFR(nor->info) == SNOR_MFR_SST ||
2447 nor->info->flags & SPI_NOR_HAS_LOCK) {
2450 spi_nor_wait_till_ready(nor);
2453 if (nor->quad_enable) {
2454 err = nor->quad_enable(nor);
2456 dev_dbg(nor->dev, "quad mode not supported\n");
2461 if (nor->addr_width == 4 &&
2462 (JEDEC_MFR(nor->info) != SNOR_MFR_SPANSION) &&
2463 !(nor->info->flags & SPI_NOR_4B_OPCODES)) {
2465 * If the RESET# pin isn't hooked up properly, or the system
2466 * otherwise doesn't perform a reset command in the boot
2467 * sequence, it's impossible to 100% protect against unexpected
2468 * reboots (e.g., crashes). Warn the user (or hopefully, system
2469 * designer) that this is bad.
2471 if (nor->flags & SNOR_F_BROKEN_RESET)
2472 printf("enabling reset hack; may not recover from unexpected reboots\n");
2473 set_4byte(nor, nor->info, 1);
2479 int spi_nor_scan(struct spi_nor *nor)
2481 struct spi_nor_flash_parameter params;
2482 const struct flash_info *info = NULL;
2483 struct mtd_info *mtd = &nor->mtd;
2484 struct spi_nor_hwcaps hwcaps = {
2485 .mask = SNOR_HWCAPS_READ |
2486 SNOR_HWCAPS_READ_FAST |
2489 struct spi_slave *spi = nor->spi;
2492 /* Reset SPI protocol for all commands. */
2493 nor->reg_proto = SNOR_PROTO_1_1_1;
2494 nor->read_proto = SNOR_PROTO_1_1_1;
2495 nor->write_proto = SNOR_PROTO_1_1_1;
2496 nor->read = spi_nor_read_data;
2497 nor->write = spi_nor_write_data;
2498 nor->read_reg = spi_nor_read_reg;
2499 nor->write_reg = spi_nor_write_reg;
2501 if (spi->mode & SPI_RX_OCTAL) {
2502 hwcaps.mask |= SNOR_HWCAPS_READ_1_1_8;
2504 if (spi->mode & SPI_TX_OCTAL)
2505 hwcaps.mask |= (SNOR_HWCAPS_READ_1_8_8 |
2506 SNOR_HWCAPS_PP_1_1_8 |
2507 SNOR_HWCAPS_PP_1_8_8);
2508 } else if (spi->mode & SPI_RX_QUAD) {
2509 hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4;
2511 if (spi->mode & SPI_TX_QUAD)
2512 hwcaps.mask |= (SNOR_HWCAPS_READ_1_4_4 |
2513 SNOR_HWCAPS_PP_1_1_4 |
2514 SNOR_HWCAPS_PP_1_4_4);
2515 } else if (spi->mode & SPI_RX_DUAL) {
2516 hwcaps.mask |= SNOR_HWCAPS_READ_1_1_2;
2518 if (spi->mode & SPI_TX_DUAL)
2519 hwcaps.mask |= SNOR_HWCAPS_READ_1_2_2;
2522 info = spi_nor_read_id(nor);
2523 if (IS_ERR_OR_NULL(info))
2525 /* Parse the Serial Flash Discoverable Parameters table. */
2526 ret = spi_nor_init_params(nor, info, ¶ms);
2531 mtd->name = info->name;
2533 mtd->type = MTD_NORFLASH;
2535 mtd->flags = MTD_CAP_NORFLASH;
2536 mtd->size = params.size;
2537 mtd->_erase = spi_nor_erase;
2538 mtd->_read = spi_nor_read;
2539 mtd->_write = spi_nor_write;
2541 #if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST)
2542 /* NOR protection support for STmicro/Micron chips and similar */
2543 if (JEDEC_MFR(info) == SNOR_MFR_ST ||
2544 JEDEC_MFR(info) == SNOR_MFR_MICRON ||
2545 JEDEC_MFR(info) == SNOR_MFR_SST ||
2546 info->flags & SPI_NOR_HAS_LOCK) {
2547 nor->flash_lock = stm_lock;
2548 nor->flash_unlock = stm_unlock;
2549 nor->flash_is_locked = stm_is_locked;
2553 #ifdef CONFIG_SPI_FLASH_SST
2555 * sst26 series block protection implementation differs from other
2558 if (info->flags & SPI_NOR_HAS_SST26LOCK) {
2559 nor->flash_lock = sst26_lock;
2560 nor->flash_unlock = sst26_unlock;
2561 nor->flash_is_locked = sst26_is_locked;
2565 if (info->flags & USE_FSR)
2566 nor->flags |= SNOR_F_USE_FSR;
2567 if (info->flags & SPI_NOR_HAS_TB)
2568 nor->flags |= SNOR_F_HAS_SR_TB;
2569 if (info->flags & NO_CHIP_ERASE)
2570 nor->flags |= SNOR_F_NO_OP_CHIP_ERASE;
2571 if (info->flags & USE_CLSR)
2572 nor->flags |= SNOR_F_USE_CLSR;
2574 if (info->flags & SPI_NOR_NO_ERASE)
2575 mtd->flags |= MTD_NO_ERASE;
2577 nor->page_size = params.page_size;
2578 mtd->writebufsize = nor->page_size;
2580 /* Some devices cannot do fast-read, no matter what DT tells us */
2581 if ((info->flags & SPI_NOR_NO_FR) || (spi->mode & SPI_RX_SLOW))
2582 params.hwcaps.mask &= ~SNOR_HWCAPS_READ_FAST;
2585 * Configure the SPI memory:
2586 * - select op codes for (Fast) Read, Page Program and Sector Erase.
2587 * - set the number of dummy cycles (mode cycles + wait states).
2588 * - set the SPI protocols for register and memory accesses.
2589 * - set the Quad Enable bit if needed (required by SPI x-y-4 protos).
2591 ret = spi_nor_setup(nor, info, ¶ms, &hwcaps);
2595 if (nor->addr_width) {
2596 /* already configured from SFDP */
2597 } else if (info->addr_width) {
2598 nor->addr_width = info->addr_width;
2599 } else if (mtd->size > SZ_16M) {
2600 #ifndef CONFIG_SPI_FLASH_BAR
2601 /* enable 4-byte addressing if the device exceeds 16MiB */
2602 nor->addr_width = 4;
2603 if (JEDEC_MFR(info) == SNOR_MFR_SPANSION ||
2604 info->flags & SPI_NOR_4B_OPCODES)
2605 spi_nor_set_4byte_opcodes(nor, info);
2607 /* Configure the BAR - discover bank cmds and read current bank */
2608 nor->addr_width = 3;
2609 ret = read_bar(nor, info);
2614 nor->addr_width = 3;
2617 if (nor->addr_width > SPI_NOR_MAX_ADDR_WIDTH) {
2618 dev_dbg(nor->dev, "address width is too large: %u\n",
2623 /* Send all the required SPI flash commands to initialize device */
2625 ret = spi_nor_init(nor);
2629 nor->name = mtd->name;
2630 nor->size = mtd->size;
2631 nor->erase_size = mtd->erasesize;
2632 nor->sector_size = mtd->erasesize;
2634 #ifndef CONFIG_SPL_BUILD
2635 printf("SF: Detected %s with page size ", nor->name);
2636 print_size(nor->page_size, ", erase size ");
2637 print_size(nor->erase_size, ", total ");
2638 print_size(nor->size, "");