1 // SPDX-License-Identifier: GPL-2.0
3 * Based on m25p80.c, by Mike Lavender (mike@steroidmicros.com), with
4 * influence from lart.c (Abraham Van Der Merwe) and mtd_dataflash.c
6 * Copyright (C) 2005, Intec Automation Inc.
7 * Copyright (C) 2014, Freescale Semiconductor, Inc.
9 * Synced from Linux v4.19
13 #include <linux/err.h>
14 #include <linux/errno.h>
15 #include <linux/log2.h>
16 #include <linux/math64.h>
17 #include <linux/sizes.h>
19 #include <linux/mtd/mtd.h>
20 #include <linux/mtd/spi-nor.h>
24 #include "sf_internal.h"
26 /* Define max times to check status register before we give up. */
29 * For everything but full-chip erase; probably could be much smaller, but kept
30 * around for safety for now
33 #define HZ CONFIG_SYS_HZ
35 #define DEFAULT_READY_WAIT_JIFFIES (40UL * HZ)
37 static int spi_nor_read_write_reg(struct spi_nor *nor, struct spi_mem_op
40 if (op->data.dir == SPI_MEM_DATA_IN)
41 op->data.buf.in = buf;
43 op->data.buf.out = buf;
44 return spi_mem_exec_op(nor->spi, op);
47 static int spi_nor_read_reg(struct spi_nor *nor, u8 code, u8 *val, int len)
49 struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(code, 1),
52 SPI_MEM_OP_DATA_IN(len, NULL, 1));
55 ret = spi_nor_read_write_reg(nor, &op, val);
57 dev_dbg(&flash->spimem->spi->dev, "error %d reading %x\n", ret,
63 static int spi_nor_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
65 struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(opcode, 1),
68 SPI_MEM_OP_DATA_OUT(len, NULL, 1));
70 return spi_nor_read_write_reg(nor, &op, buf);
73 static ssize_t spi_nor_read_data(struct spi_nor *nor, loff_t from, size_t len,
76 struct spi_mem_op op =
77 SPI_MEM_OP(SPI_MEM_OP_CMD(nor->read_opcode, 1),
78 SPI_MEM_OP_ADDR(nor->addr_width, from, 1),
79 SPI_MEM_OP_DUMMY(nor->read_dummy, 1),
80 SPI_MEM_OP_DATA_IN(len, buf, 1));
81 size_t remaining = len;
84 /* get transfer protocols. */
85 op.cmd.buswidth = spi_nor_get_protocol_inst_nbits(nor->read_proto);
86 op.addr.buswidth = spi_nor_get_protocol_addr_nbits(nor->read_proto);
87 op.dummy.buswidth = op.addr.buswidth;
88 op.data.buswidth = spi_nor_get_protocol_data_nbits(nor->read_proto);
90 /* convert the dummy cycles to the number of bytes */
91 op.dummy.nbytes = (nor->read_dummy * op.dummy.buswidth) / 8;
94 op.data.nbytes = remaining < UINT_MAX ? remaining : UINT_MAX;
95 ret = spi_mem_adjust_op_size(nor->spi, &op);
99 ret = spi_mem_exec_op(nor->spi, &op);
103 op.addr.val += op.data.nbytes;
104 remaining -= op.data.nbytes;
105 op.data.buf.in += op.data.nbytes;
111 static ssize_t spi_nor_write_data(struct spi_nor *nor, loff_t to, size_t len,
114 struct spi_mem_op op =
115 SPI_MEM_OP(SPI_MEM_OP_CMD(nor->program_opcode, 1),
116 SPI_MEM_OP_ADDR(nor->addr_width, to, 1),
118 SPI_MEM_OP_DATA_OUT(len, buf, 1));
121 /* get transfer protocols. */
122 op.cmd.buswidth = spi_nor_get_protocol_inst_nbits(nor->write_proto);
123 op.addr.buswidth = spi_nor_get_protocol_addr_nbits(nor->write_proto);
124 op.data.buswidth = spi_nor_get_protocol_data_nbits(nor->write_proto);
126 if (nor->program_opcode == SPINOR_OP_AAI_WP && nor->sst_write_second)
129 ret = spi_mem_adjust_op_size(nor->spi, &op);
132 op.data.nbytes = len < op.data.nbytes ? len : op.data.nbytes;
134 ret = spi_mem_exec_op(nor->spi, &op);
138 return op.data.nbytes;
142 * Read the status register, returning its value in the location
143 * Return the status register value.
144 * Returns negative if error occurred.
146 static int read_sr(struct spi_nor *nor)
151 ret = nor->read_reg(nor, SPINOR_OP_RDSR, &val, 1);
153 pr_debug("error %d reading SR\n", (int)ret);
161 * Read the flag status register, returning its value in the location
162 * Return the status register value.
163 * Returns negative if error occurred.
165 static int read_fsr(struct spi_nor *nor)
170 ret = nor->read_reg(nor, SPINOR_OP_RDFSR, &val, 1);
172 pr_debug("error %d reading FSR\n", ret);
180 * Read configuration register, returning its value in the
181 * location. Return the configuration register value.
182 * Returns negative if error occurred.
184 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
185 static int read_cr(struct spi_nor *nor)
190 ret = nor->read_reg(nor, SPINOR_OP_RDCR, &val, 1);
192 dev_dbg(nor->dev, "error %d reading CR\n", ret);
201 * Write status register 1 byte
202 * Returns negative if error occurred.
204 static int write_sr(struct spi_nor *nor, u8 val)
206 nor->cmd_buf[0] = val;
207 return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1);
211 * Set write enable latch with Write Enable command.
212 * Returns negative if error occurred.
214 static int write_enable(struct spi_nor *nor)
216 return nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0);
220 * Send write disable instruction to the chip.
222 static int write_disable(struct spi_nor *nor)
224 return nor->write_reg(nor, SPINOR_OP_WRDI, NULL, 0);
227 static struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd)
232 #ifndef CONFIG_SPI_FLASH_BAR
233 static u8 spi_nor_convert_opcode(u8 opcode, const u8 table[][2], size_t size)
237 for (i = 0; i < size; i++)
238 if (table[i][0] == opcode)
241 /* No conversion found, keep input op code. */
245 static u8 spi_nor_convert_3to4_read(u8 opcode)
247 static const u8 spi_nor_3to4_read[][2] = {
248 { SPINOR_OP_READ, SPINOR_OP_READ_4B },
249 { SPINOR_OP_READ_FAST, SPINOR_OP_READ_FAST_4B },
250 { SPINOR_OP_READ_1_1_2, SPINOR_OP_READ_1_1_2_4B },
251 { SPINOR_OP_READ_1_2_2, SPINOR_OP_READ_1_2_2_4B },
252 { SPINOR_OP_READ_1_1_4, SPINOR_OP_READ_1_1_4_4B },
253 { SPINOR_OP_READ_1_4_4, SPINOR_OP_READ_1_4_4_4B },
255 { SPINOR_OP_READ_1_1_1_DTR, SPINOR_OP_READ_1_1_1_DTR_4B },
256 { SPINOR_OP_READ_1_2_2_DTR, SPINOR_OP_READ_1_2_2_DTR_4B },
257 { SPINOR_OP_READ_1_4_4_DTR, SPINOR_OP_READ_1_4_4_DTR_4B },
260 return spi_nor_convert_opcode(opcode, spi_nor_3to4_read,
261 ARRAY_SIZE(spi_nor_3to4_read));
264 static u8 spi_nor_convert_3to4_program(u8 opcode)
266 static const u8 spi_nor_3to4_program[][2] = {
267 { SPINOR_OP_PP, SPINOR_OP_PP_4B },
268 { SPINOR_OP_PP_1_1_4, SPINOR_OP_PP_1_1_4_4B },
269 { SPINOR_OP_PP_1_4_4, SPINOR_OP_PP_1_4_4_4B },
272 return spi_nor_convert_opcode(opcode, spi_nor_3to4_program,
273 ARRAY_SIZE(spi_nor_3to4_program));
276 static u8 spi_nor_convert_3to4_erase(u8 opcode)
278 static const u8 spi_nor_3to4_erase[][2] = {
279 { SPINOR_OP_BE_4K, SPINOR_OP_BE_4K_4B },
280 { SPINOR_OP_BE_32K, SPINOR_OP_BE_32K_4B },
281 { SPINOR_OP_SE, SPINOR_OP_SE_4B },
284 return spi_nor_convert_opcode(opcode, spi_nor_3to4_erase,
285 ARRAY_SIZE(spi_nor_3to4_erase));
288 static void spi_nor_set_4byte_opcodes(struct spi_nor *nor,
289 const struct flash_info *info)
291 /* Do some manufacturer fixups first */
292 switch (JEDEC_MFR(info)) {
293 case SNOR_MFR_SPANSION:
294 /* No small sector erase for 4-byte command set */
295 nor->erase_opcode = SPINOR_OP_SE;
296 nor->mtd.erasesize = info->sector_size;
303 nor->read_opcode = spi_nor_convert_3to4_read(nor->read_opcode);
304 nor->program_opcode = spi_nor_convert_3to4_program(nor->program_opcode);
305 nor->erase_opcode = spi_nor_convert_3to4_erase(nor->erase_opcode);
307 #endif /* !CONFIG_SPI_FLASH_BAR */
309 /* Enable/disable 4-byte addressing mode. */
310 static int set_4byte(struct spi_nor *nor, const struct flash_info *info,
314 bool need_wren = false;
317 switch (JEDEC_MFR(info)) {
319 case SNOR_MFR_MICRON:
320 /* Some Micron need WREN command; all will accept it */
322 case SNOR_MFR_MACRONIX:
323 case SNOR_MFR_WINBOND:
327 cmd = enable ? SPINOR_OP_EN4B : SPINOR_OP_EX4B;
328 status = nor->write_reg(nor, cmd, NULL, 0);
332 if (!status && !enable &&
333 JEDEC_MFR(info) == SNOR_MFR_WINBOND) {
335 * On Winbond W25Q256FV, leaving 4byte mode causes
336 * the Extended Address Register to be set to 1, so all
337 * 3-byte-address reads come from the second 16M.
338 * We must clear the register to enable normal behavior.
342 nor->write_reg(nor, SPINOR_OP_WREAR, nor->cmd_buf, 1);
349 nor->cmd_buf[0] = enable << 7;
350 return nor->write_reg(nor, SPINOR_OP_BRWR, nor->cmd_buf, 1);
354 static int spi_nor_sr_ready(struct spi_nor *nor)
356 int sr = read_sr(nor);
361 if (nor->flags & SNOR_F_USE_CLSR && sr & (SR_E_ERR | SR_P_ERR)) {
363 dev_dbg(nor->dev, "Erase Error occurred\n");
365 dev_dbg(nor->dev, "Programming Error occurred\n");
367 nor->write_reg(nor, SPINOR_OP_CLSR, NULL, 0);
371 return !(sr & SR_WIP);
374 static int spi_nor_fsr_ready(struct spi_nor *nor)
376 int fsr = read_fsr(nor);
381 if (fsr & (FSR_E_ERR | FSR_P_ERR)) {
383 dev_err(nor->dev, "Erase operation failed.\n");
385 dev_err(nor->dev, "Program operation failed.\n");
387 if (fsr & FSR_PT_ERR)
389 "Attempted to modify a protected sector.\n");
391 nor->write_reg(nor, SPINOR_OP_CLFSR, NULL, 0);
395 return fsr & FSR_READY;
398 static int spi_nor_ready(struct spi_nor *nor)
402 sr = spi_nor_sr_ready(nor);
405 fsr = nor->flags & SNOR_F_USE_FSR ? spi_nor_fsr_ready(nor) : 1;
412 * Service routine to read status register until ready, or timeout occurs.
413 * Returns non-zero if error.
415 static int spi_nor_wait_till_ready_with_timeout(struct spi_nor *nor,
416 unsigned long timeout)
418 unsigned long timebase;
421 timebase = get_timer(0);
423 while (get_timer(timebase) < timeout) {
424 ret = spi_nor_ready(nor);
431 dev_err(nor->dev, "flash operation timed out\n");
436 static int spi_nor_wait_till_ready(struct spi_nor *nor)
438 return spi_nor_wait_till_ready_with_timeout(nor,
439 DEFAULT_READY_WAIT_JIFFIES);
442 #ifdef CONFIG_SPI_FLASH_BAR
444 * This "clean_bar" is necessary in a situation when one was accessing
445 * spi flash memory > 16 MiB by using Bank Address Register's BA24 bit.
447 * After it the BA24 bit shall be cleared to allow access to correct
448 * memory region after SW reset (by calling "reset" command).
450 * Otherwise, the BA24 bit may be left set and then after reset, the
451 * ROM would read/write/erase SPL from 16 MiB * bank_sel address.
453 static int clean_bar(struct spi_nor *nor)
455 u8 cmd, bank_sel = 0;
457 if (nor->bank_curr == 0)
459 cmd = nor->bank_write_cmd;
463 return nor->write_reg(nor, cmd, &bank_sel, 1);
466 static int write_bar(struct spi_nor *nor, u32 offset)
471 bank_sel = offset / SZ_16M;
472 if (bank_sel == nor->bank_curr)
475 cmd = nor->bank_write_cmd;
477 ret = nor->write_reg(nor, cmd, &bank_sel, 1);
479 debug("SF: fail to write bank register\n");
484 nor->bank_curr = bank_sel;
485 return nor->bank_curr;
488 static int read_bar(struct spi_nor *nor, const struct flash_info *info)
493 switch (JEDEC_MFR(info)) {
494 case SNOR_MFR_SPANSION:
495 nor->bank_read_cmd = SPINOR_OP_BRRD;
496 nor->bank_write_cmd = SPINOR_OP_BRWR;
499 nor->bank_read_cmd = SPINOR_OP_RDEAR;
500 nor->bank_write_cmd = SPINOR_OP_WREAR;
503 ret = nor->read_reg(nor, nor->bank_read_cmd,
506 debug("SF: fail to read bank addr register\n");
509 nor->bank_curr = curr_bank;
516 * Initiate the erasure of a single sector
518 static int spi_nor_erase_sector(struct spi_nor *nor, u32 addr)
520 struct spi_mem_op op =
521 SPI_MEM_OP(SPI_MEM_OP_CMD(nor->erase_opcode, 1),
522 SPI_MEM_OP_ADDR(nor->addr_width, addr, 1),
527 return nor->erase(nor, addr);
530 * Default implementation, if driver doesn't have a specialized HW
533 return spi_mem_exec_op(nor->spi, &op);
537 * Erase an address range on the nor chip. The address range may extend
538 * one or more erase sectors. Return an error is there is a problem erasing.
540 static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
542 struct spi_nor *nor = mtd_to_spi_nor(mtd);
546 dev_dbg(nor->dev, "at 0x%llx, len %lld\n", (long long)instr->addr,
547 (long long)instr->len);
549 div_u64_rem(instr->len, mtd->erasesize, &rem);
557 #ifdef CONFIG_SPI_FLASH_BAR
558 ret = write_bar(nor, addr);
564 ret = spi_nor_erase_sector(nor, addr);
568 addr += mtd->erasesize;
569 len -= mtd->erasesize;
571 ret = spi_nor_wait_till_ready(nor);
577 #ifdef CONFIG_SPI_FLASH_BAR
578 ret = clean_bar(nor);
585 #if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST)
586 /* Write status register and ensure bits in mask match written values */
587 static int write_sr_and_check(struct spi_nor *nor, u8 status_new, u8 mask)
592 ret = write_sr(nor, status_new);
596 ret = spi_nor_wait_till_ready(nor);
604 return ((ret & mask) != (status_new & mask)) ? -EIO : 0;
607 static void stm_get_locked_range(struct spi_nor *nor, u8 sr, loff_t *ofs,
610 struct mtd_info *mtd = &nor->mtd;
611 u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
612 int shift = ffs(mask) - 1;
620 pow = ((sr & mask) ^ mask) >> shift;
621 *len = mtd->size >> pow;
622 if (nor->flags & SNOR_F_HAS_SR_TB && sr & SR_TB)
625 *ofs = mtd->size - *len;
630 * Return 1 if the entire region is locked (if @locked is true) or unlocked (if
631 * @locked is false); 0 otherwise
633 static int stm_check_lock_status_sr(struct spi_nor *nor, loff_t ofs, u64 len,
642 stm_get_locked_range(nor, sr, &lock_offs, &lock_len);
645 /* Requested range is a sub-range of locked range */
646 return (ofs + len <= lock_offs + lock_len) && (ofs >= lock_offs);
648 /* Requested range does not overlap with locked range */
649 return (ofs >= lock_offs + lock_len) || (ofs + len <= lock_offs);
652 static int stm_is_locked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len,
655 return stm_check_lock_status_sr(nor, ofs, len, sr, true);
658 static int stm_is_unlocked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len,
661 return stm_check_lock_status_sr(nor, ofs, len, sr, false);
665 * Lock a region of the flash. Compatible with ST Micro and similar flash.
666 * Supports the block protection bits BP{0,1,2} in the status register
667 * (SR). Does not support these features found in newer SR bitfields:
668 * - SEC: sector/block protect - only handle SEC=0 (block protect)
669 * - CMP: complement protect - only support CMP=0 (range is not complemented)
671 * Support for the following is provided conditionally for some flash:
672 * - TB: top/bottom protect
674 * Sample table portion for 8MB flash (Winbond w25q64fw):
676 * SEC | TB | BP2 | BP1 | BP0 | Prot Length | Protected Portion
677 * --------------------------------------------------------------------------
678 * X | X | 0 | 0 | 0 | NONE | NONE
679 * 0 | 0 | 0 | 0 | 1 | 128 KB | Upper 1/64
680 * 0 | 0 | 0 | 1 | 0 | 256 KB | Upper 1/32
681 * 0 | 0 | 0 | 1 | 1 | 512 KB | Upper 1/16
682 * 0 | 0 | 1 | 0 | 0 | 1 MB | Upper 1/8
683 * 0 | 0 | 1 | 0 | 1 | 2 MB | Upper 1/4
684 * 0 | 0 | 1 | 1 | 0 | 4 MB | Upper 1/2
685 * X | X | 1 | 1 | 1 | 8 MB | ALL
686 * ------|-------|-------|-------|-------|---------------|-------------------
687 * 0 | 1 | 0 | 0 | 1 | 128 KB | Lower 1/64
688 * 0 | 1 | 0 | 1 | 0 | 256 KB | Lower 1/32
689 * 0 | 1 | 0 | 1 | 1 | 512 KB | Lower 1/16
690 * 0 | 1 | 1 | 0 | 0 | 1 MB | Lower 1/8
691 * 0 | 1 | 1 | 0 | 1 | 2 MB | Lower 1/4
692 * 0 | 1 | 1 | 1 | 0 | 4 MB | Lower 1/2
694 * Returns negative on errors, 0 on success.
696 static int stm_lock(struct spi_nor *nor, loff_t ofs, uint64_t len)
698 struct mtd_info *mtd = &nor->mtd;
699 int status_old, status_new;
700 u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
701 u8 shift = ffs(mask) - 1, pow, val;
703 bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB;
706 status_old = read_sr(nor);
710 /* If nothing in our range is unlocked, we don't need to do anything */
711 if (stm_is_locked_sr(nor, ofs, len, status_old))
714 /* If anything below us is unlocked, we can't use 'bottom' protection */
715 if (!stm_is_locked_sr(nor, 0, ofs, status_old))
716 can_be_bottom = false;
718 /* If anything above us is unlocked, we can't use 'top' protection */
719 if (!stm_is_locked_sr(nor, ofs + len, mtd->size - (ofs + len),
723 if (!can_be_bottom && !can_be_top)
726 /* Prefer top, if both are valid */
727 use_top = can_be_top;
729 /* lock_len: length of region that should end up locked */
731 lock_len = mtd->size - ofs;
733 lock_len = ofs + len;
736 * Need smallest pow such that:
738 * 1 / (2^pow) <= (len / size)
740 * so (assuming power-of-2 size) we do:
742 * pow = ceil(log2(size / len)) = log2(size) - floor(log2(len))
744 pow = ilog2(mtd->size) - ilog2(lock_len);
745 val = mask - (pow << shift);
748 /* Don't "lock" with no region! */
752 status_new = (status_old & ~mask & ~SR_TB) | val;
754 /* Disallow further writes if WP pin is asserted */
755 status_new |= SR_SRWD;
760 /* Don't bother if they're the same */
761 if (status_new == status_old)
764 /* Only modify protection if it will not unlock other areas */
765 if ((status_new & mask) < (status_old & mask))
768 return write_sr_and_check(nor, status_new, mask);
772 * Unlock a region of the flash. See stm_lock() for more info
774 * Returns negative on errors, 0 on success.
776 static int stm_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len)
778 struct mtd_info *mtd = &nor->mtd;
779 int status_old, status_new;
780 u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
781 u8 shift = ffs(mask) - 1, pow, val;
783 bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB;
786 status_old = read_sr(nor);
790 /* If nothing in our range is locked, we don't need to do anything */
791 if (stm_is_unlocked_sr(nor, ofs, len, status_old))
794 /* If anything below us is locked, we can't use 'top' protection */
795 if (!stm_is_unlocked_sr(nor, 0, ofs, status_old))
798 /* If anything above us is locked, we can't use 'bottom' protection */
799 if (!stm_is_unlocked_sr(nor, ofs + len, mtd->size - (ofs + len),
801 can_be_bottom = false;
803 if (!can_be_bottom && !can_be_top)
806 /* Prefer top, if both are valid */
807 use_top = can_be_top;
809 /* lock_len: length of region that should remain locked */
811 lock_len = mtd->size - (ofs + len);
816 * Need largest pow such that:
818 * 1 / (2^pow) >= (len / size)
820 * so (assuming power-of-2 size) we do:
822 * pow = floor(log2(size / len)) = log2(size) - ceil(log2(len))
824 pow = ilog2(mtd->size) - order_base_2(lock_len);
826 val = 0; /* fully unlocked */
828 val = mask - (pow << shift);
829 /* Some power-of-two sizes are not supported */
834 status_new = (status_old & ~mask & ~SR_TB) | val;
836 /* Don't protect status register if we're fully unlocked */
838 status_new &= ~SR_SRWD;
843 /* Don't bother if they're the same */
844 if (status_new == status_old)
847 /* Only modify protection if it will not lock other areas */
848 if ((status_new & mask) > (status_old & mask))
851 return write_sr_and_check(nor, status_new, mask);
855 * Check if a region of the flash is (completely) locked. See stm_lock() for
858 * Returns 1 if entire region is locked, 0 if any portion is unlocked, and
859 * negative on errors.
861 static int stm_is_locked(struct spi_nor *nor, loff_t ofs, uint64_t len)
865 status = read_sr(nor);
869 return stm_is_locked_sr(nor, ofs, len, status);
871 #endif /* CONFIG_SPI_FLASH_STMICRO */
873 static const struct flash_info *spi_nor_read_id(struct spi_nor *nor)
876 u8 id[SPI_NOR_MAX_ID_LEN];
877 const struct flash_info *info;
879 tmp = nor->read_reg(nor, SPINOR_OP_RDID, id, SPI_NOR_MAX_ID_LEN);
881 dev_dbg(nor->dev, "error %d reading JEDEC ID\n", tmp);
886 for (; info->name; info++) {
888 if (!memcmp(info->id, id, info->id_len))
893 dev_err(nor->dev, "unrecognized JEDEC id bytes: %02x, %02x, %02x\n",
894 id[0], id[1], id[2]);
895 return ERR_PTR(-ENODEV);
898 static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len,
899 size_t *retlen, u_char *buf)
901 struct spi_nor *nor = mtd_to_spi_nor(mtd);
904 dev_dbg(nor->dev, "from 0x%08x, len %zd\n", (u32)from, len);
908 size_t read_len = len;
910 #ifdef CONFIG_SPI_FLASH_BAR
913 ret = write_bar(nor, addr);
916 remain_len = (SZ_16M * (nor->bank_curr + 1)) - addr;
918 if (len < remain_len)
921 read_len = remain_len;
924 ret = nor->read(nor, addr, read_len, buf);
926 /* We shouldn't see 0-length reads */
941 #ifdef CONFIG_SPI_FLASH_BAR
942 ret = clean_bar(nor);
947 #ifdef CONFIG_SPI_FLASH_SST
949 * sst26 flash series has its own block protection implementation:
950 * 4x - 8 KByte blocks - read & write protection bits - upper addresses
951 * 1x - 32 KByte blocks - write protection bits
952 * rest - 64 KByte blocks - write protection bits
953 * 1x - 32 KByte blocks - write protection bits
954 * 4x - 8 KByte blocks - read & write protection bits - lower addresses
956 * We'll support only per 64k lock/unlock so lower and upper 64 KByte region
957 * will be treated as single block.
959 #define SST26_BPR_8K_NUM 4
960 #define SST26_MAX_BPR_REG_LEN (18 + 1)
961 #define SST26_BOUND_REG_SIZE ((32 + SST26_BPR_8K_NUM * 8) * SZ_1K)
969 static bool sst26_process_bpr(u32 bpr_size, u8 *cmd, u32 bit, enum lock_ctl ctl)
973 cmd[bpr_size - (bit / 8) - 1] |= BIT(bit % 8);
975 case SST26_CTL_UNLOCK:
976 cmd[bpr_size - (bit / 8) - 1] &= ~BIT(bit % 8);
978 case SST26_CTL_CHECK:
979 return !!(cmd[bpr_size - (bit / 8) - 1] & BIT(bit % 8));
986 * Lock, unlock or check lock status of the flash region of the flash (depending
987 * on the lock_ctl value)
989 static int sst26_lock_ctl(struct spi_nor *nor, loff_t ofs, uint64_t len, enum lock_ctl ctl)
991 struct mtd_info *mtd = &nor->mtd;
992 u32 i, bpr_ptr, rptr_64k, lptr_64k, bpr_size;
993 bool lower_64k = false, upper_64k = false;
994 u8 bpr_buff[SST26_MAX_BPR_REG_LEN] = {};
997 /* Check length and offset for 64k alignment */
998 if ((ofs & (SZ_64K - 1)) || (len & (SZ_64K - 1))) {
999 dev_err(nor->dev, "length or offset is not 64KiB allighned\n");
1003 if (ofs + len > mtd->size) {
1004 dev_err(nor->dev, "range is more than device size: %#llx + %#llx > %#llx\n",
1005 ofs, len, mtd->size);
1009 /* SST26 family has only 16 Mbit, 32 Mbit and 64 Mbit IC */
1010 if (mtd->size != SZ_2M &&
1011 mtd->size != SZ_4M &&
1015 bpr_size = 2 + (mtd->size / SZ_64K / 8);
1017 ret = nor->read_reg(nor, SPINOR_OP_READ_BPR, bpr_buff, bpr_size);
1019 dev_err(nor->dev, "fail to read block-protection register\n");
1023 rptr_64k = min_t(u32, ofs + len, mtd->size - SST26_BOUND_REG_SIZE);
1024 lptr_64k = max_t(u32, ofs, SST26_BOUND_REG_SIZE);
1026 upper_64k = ((ofs + len) > (mtd->size - SST26_BOUND_REG_SIZE));
1027 lower_64k = (ofs < SST26_BOUND_REG_SIZE);
1029 /* Lower bits in block-protection register are about 64k region */
1030 bpr_ptr = lptr_64k / SZ_64K - 1;
1032 /* Process 64K blocks region */
1033 while (lptr_64k < rptr_64k) {
1034 if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl))
1041 /* 32K and 8K region bits in BPR are after 64k region bits */
1042 bpr_ptr = (mtd->size - 2 * SST26_BOUND_REG_SIZE) / SZ_64K;
1044 /* Process lower 32K block region */
1046 if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl))
1051 /* Process upper 32K block region */
1053 if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl))
1058 /* Process lower 8K block regions */
1059 for (i = 0; i < SST26_BPR_8K_NUM; i++) {
1061 if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl))
1064 /* In 8K area BPR has both read and write protection bits */
1068 /* Process upper 8K block regions */
1069 for (i = 0; i < SST26_BPR_8K_NUM; i++) {
1071 if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl))
1074 /* In 8K area BPR has both read and write protection bits */
1078 /* If we check region status we don't need to write BPR back */
1079 if (ctl == SST26_CTL_CHECK)
1082 ret = nor->write_reg(nor, SPINOR_OP_WRITE_BPR, bpr_buff, bpr_size);
1084 dev_err(nor->dev, "fail to write block-protection register\n");
1091 static int sst26_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len)
1093 return sst26_lock_ctl(nor, ofs, len, SST26_CTL_UNLOCK);
1096 static int sst26_lock(struct spi_nor *nor, loff_t ofs, uint64_t len)
1098 return sst26_lock_ctl(nor, ofs, len, SST26_CTL_LOCK);
1102 * Returns EACCES (positive value) if region is locked, 0 if region is unlocked,
1103 * and negative on errors.
1105 static int sst26_is_locked(struct spi_nor *nor, loff_t ofs, uint64_t len)
1108 * is_locked function is used for check before reading or erasing flash
1109 * region, so offset and length might be not 64k allighned, so adjust
1110 * them to be 64k allighned as sst26_lock_ctl works only with 64k
1111 * allighned regions.
1113 ofs -= ofs & (SZ_64K - 1);
1114 len = len & (SZ_64K - 1) ? (len & ~(SZ_64K - 1)) + SZ_64K : len;
1116 return sst26_lock_ctl(nor, ofs, len, SST26_CTL_CHECK);
1119 static int sst_write_byteprogram(struct spi_nor *nor, loff_t to, size_t len,
1120 size_t *retlen, const u_char *buf)
1125 for (actual = 0; actual < len; actual++) {
1126 nor->program_opcode = SPINOR_OP_BP;
1129 /* write one byte. */
1130 ret = nor->write(nor, to, 1, buf + actual);
1133 ret = spi_nor_wait_till_ready(nor);
1144 static int sst_write(struct mtd_info *mtd, loff_t to, size_t len,
1145 size_t *retlen, const u_char *buf)
1147 struct spi_nor *nor = mtd_to_spi_nor(mtd);
1148 struct spi_slave *spi = nor->spi;
1152 dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len);
1153 if (spi->mode & SPI_TX_BYTE)
1154 return sst_write_byteprogram(nor, to, len, retlen, buf);
1158 nor->sst_write_second = false;
1161 /* Start write from odd address. */
1163 nor->program_opcode = SPINOR_OP_BP;
1165 /* write one byte. */
1166 ret = nor->write(nor, to, 1, buf);
1169 ret = spi_nor_wait_till_ready(nor);
1175 /* Write out most of the data here. */
1176 for (; actual < len - 1; actual += 2) {
1177 nor->program_opcode = SPINOR_OP_AAI_WP;
1179 /* write two bytes. */
1180 ret = nor->write(nor, to, 2, buf + actual);
1183 ret = spi_nor_wait_till_ready(nor);
1187 nor->sst_write_second = true;
1189 nor->sst_write_second = false;
1192 ret = spi_nor_wait_till_ready(nor);
1196 /* Write out trailing byte if it exists. */
1197 if (actual != len) {
1200 nor->program_opcode = SPINOR_OP_BP;
1201 ret = nor->write(nor, to, 1, buf + actual);
1204 ret = spi_nor_wait_till_ready(nor);
1216 * Write an address range to the nor chip. Data must be written in
1217 * FLASH_PAGESIZE chunks. The address range may be any size provided
1218 * it is within the physical boundaries.
1220 static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len,
1221 size_t *retlen, const u_char *buf)
1223 struct spi_nor *nor = mtd_to_spi_nor(mtd);
1224 size_t page_offset, page_remain, i;
1227 dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len);
1229 for (i = 0; i < len; ) {
1231 loff_t addr = to + i;
1234 * If page_size is a power of two, the offset can be quickly
1235 * calculated with an AND operation. On the other cases we
1236 * need to do a modulus operation (more expensive).
1237 * Power of two numbers have only one bit set and we can use
1238 * the instruction hweight32 to detect if we need to do a
1239 * modulus (do_div()) or not.
1241 if (hweight32(nor->page_size) == 1) {
1242 page_offset = addr & (nor->page_size - 1);
1246 page_offset = do_div(aux, nor->page_size);
1248 /* the size of data remaining on the first page */
1249 page_remain = min_t(size_t,
1250 nor->page_size - page_offset, len - i);
1252 #ifdef CONFIG_SPI_FLASH_BAR
1253 ret = write_bar(nor, addr);
1258 ret = nor->write(nor, addr, page_remain, buf + i);
1263 ret = spi_nor_wait_till_ready(nor);
1271 #ifdef CONFIG_SPI_FLASH_BAR
1272 ret = clean_bar(nor);
1277 #ifdef CONFIG_SPI_FLASH_MACRONIX
1279 * macronix_quad_enable() - set QE bit in Status Register.
1280 * @nor: pointer to a 'struct spi_nor'
1282 * Set the Quad Enable (QE) bit in the Status Register.
1284 * bit 6 of the Status Register is the QE bit for Macronix like QSPI memories.
1286 * Return: 0 on success, -errno otherwise.
1288 static int macronix_quad_enable(struct spi_nor *nor)
1295 if (val & SR_QUAD_EN_MX)
1300 write_sr(nor, val | SR_QUAD_EN_MX);
1302 ret = spi_nor_wait_till_ready(nor);
1307 if (!(ret > 0 && (ret & SR_QUAD_EN_MX))) {
1308 dev_err(nor->dev, "Macronix Quad bit not set\n");
1316 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
1318 * Write status Register and configuration register with 2 bytes
1319 * The first byte will be written to the status register, while the
1320 * second byte will be written to the configuration register.
1321 * Return negative if error occurred.
1323 static int write_sr_cr(struct spi_nor *nor, u8 *sr_cr)
1329 ret = nor->write_reg(nor, SPINOR_OP_WRSR, sr_cr, 2);
1332 "error while writing configuration register\n");
1336 ret = spi_nor_wait_till_ready(nor);
1339 "timeout while writing configuration register\n");
1347 * spansion_read_cr_quad_enable() - set QE bit in Configuration Register.
1348 * @nor: pointer to a 'struct spi_nor'
1350 * Set the Quad Enable (QE) bit in the Configuration Register.
1351 * This function should be used with QSPI memories supporting the Read
1352 * Configuration Register (35h) instruction.
1354 * bit 1 of the Configuration Register is the QE bit for Spansion like QSPI
1357 * Return: 0 on success, -errno otherwise.
1359 static int spansion_read_cr_quad_enable(struct spi_nor *nor)
1364 /* Check current Quad Enable bit value. */
1367 dev_dbg(dev, "error while reading configuration register\n");
1371 if (ret & CR_QUAD_EN_SPAN)
1374 sr_cr[1] = ret | CR_QUAD_EN_SPAN;
1376 /* Keep the current value of the Status Register. */
1379 dev_dbg(dev, "error while reading status register\n");
1384 ret = write_sr_cr(nor, sr_cr);
1388 /* Read back and check it. */
1390 if (!(ret > 0 && (ret & CR_QUAD_EN_SPAN))) {
1391 dev_dbg(nor->dev, "Spansion Quad bit not set\n");
1398 #if CONFIG_IS_ENABLED(SPI_FLASH_SFDP_SUPPORT)
1400 * spansion_no_read_cr_quad_enable() - set QE bit in Configuration Register.
1401 * @nor: pointer to a 'struct spi_nor'
1403 * Set the Quad Enable (QE) bit in the Configuration Register.
1404 * This function should be used with QSPI memories not supporting the Read
1405 * Configuration Register (35h) instruction.
1407 * bit 1 of the Configuration Register is the QE bit for Spansion like QSPI
1410 * Return: 0 on success, -errno otherwise.
1412 static int spansion_no_read_cr_quad_enable(struct spi_nor *nor)
1417 /* Keep the current value of the Status Register. */
1420 dev_dbg(nor->dev, "error while reading status register\n");
1424 sr_cr[1] = CR_QUAD_EN_SPAN;
1426 return write_sr_cr(nor, sr_cr);
1429 #endif /* CONFIG_SPI_FLASH_SFDP_SUPPORT */
1430 #endif /* CONFIG_SPI_FLASH_SPANSION */
1432 struct spi_nor_read_command {
1436 enum spi_nor_protocol proto;
1439 struct spi_nor_pp_command {
1441 enum spi_nor_protocol proto;
1444 enum spi_nor_read_command_index {
1447 SNOR_CMD_READ_1_1_1_DTR,
1450 SNOR_CMD_READ_1_1_2,
1451 SNOR_CMD_READ_1_2_2,
1452 SNOR_CMD_READ_2_2_2,
1453 SNOR_CMD_READ_1_2_2_DTR,
1456 SNOR_CMD_READ_1_1_4,
1457 SNOR_CMD_READ_1_4_4,
1458 SNOR_CMD_READ_4_4_4,
1459 SNOR_CMD_READ_1_4_4_DTR,
1462 SNOR_CMD_READ_1_1_8,
1463 SNOR_CMD_READ_1_8_8,
1464 SNOR_CMD_READ_8_8_8,
1465 SNOR_CMD_READ_1_8_8_DTR,
1470 enum spi_nor_pp_command_index {
1486 struct spi_nor_flash_parameter {
1490 struct spi_nor_hwcaps hwcaps;
1491 struct spi_nor_read_command reads[SNOR_CMD_READ_MAX];
1492 struct spi_nor_pp_command page_programs[SNOR_CMD_PP_MAX];
1494 int (*quad_enable)(struct spi_nor *nor);
1498 spi_nor_set_read_settings(struct spi_nor_read_command *read,
1502 enum spi_nor_protocol proto)
1504 read->num_mode_clocks = num_mode_clocks;
1505 read->num_wait_states = num_wait_states;
1506 read->opcode = opcode;
1507 read->proto = proto;
1511 spi_nor_set_pp_settings(struct spi_nor_pp_command *pp,
1513 enum spi_nor_protocol proto)
1515 pp->opcode = opcode;
1519 #if CONFIG_IS_ENABLED(SPI_FLASH_SFDP_SUPPORT)
1521 * Serial Flash Discoverable Parameters (SFDP) parsing.
1525 * spi_nor_read_sfdp() - read Serial Flash Discoverable Parameters.
1526 * @nor: pointer to a 'struct spi_nor'
1527 * @addr: offset in the SFDP area to start reading data from
1528 * @len: number of bytes to read
1529 * @buf: buffer where the SFDP data are copied into (dma-safe memory)
1531 * Whatever the actual numbers of bytes for address and dummy cycles are
1532 * for (Fast) Read commands, the Read SFDP (5Ah) instruction is always
1533 * followed by a 3-byte address and 8 dummy clock cycles.
1535 * Return: 0 on success, -errno otherwise.
1537 static int spi_nor_read_sfdp(struct spi_nor *nor, u32 addr,
1538 size_t len, void *buf)
1540 u8 addr_width, read_opcode, read_dummy;
1543 read_opcode = nor->read_opcode;
1544 addr_width = nor->addr_width;
1545 read_dummy = nor->read_dummy;
1547 nor->read_opcode = SPINOR_OP_RDSFDP;
1548 nor->addr_width = 3;
1549 nor->read_dummy = 8;
1552 ret = nor->read(nor, addr, len, (u8 *)buf);
1553 if (!ret || ret > len) {
1567 nor->read_opcode = read_opcode;
1568 nor->addr_width = addr_width;
1569 nor->read_dummy = read_dummy;
1574 struct sfdp_parameter_header {
1578 u8 length; /* in double words */
1579 u8 parameter_table_pointer[3]; /* byte address */
1583 #define SFDP_PARAM_HEADER_ID(p) (((p)->id_msb << 8) | (p)->id_lsb)
1584 #define SFDP_PARAM_HEADER_PTP(p) \
1585 (((p)->parameter_table_pointer[2] << 16) | \
1586 ((p)->parameter_table_pointer[1] << 8) | \
1587 ((p)->parameter_table_pointer[0] << 0))
1589 #define SFDP_BFPT_ID 0xff00 /* Basic Flash Parameter Table */
1590 #define SFDP_SECTOR_MAP_ID 0xff81 /* Sector Map Table */
1591 #define SFDP_SST_ID 0x01bf /* Manufacturer specific Table */
1593 #define SFDP_SIGNATURE 0x50444653U
1594 #define SFDP_JESD216_MAJOR 1
1595 #define SFDP_JESD216_MINOR 0
1596 #define SFDP_JESD216A_MINOR 5
1597 #define SFDP_JESD216B_MINOR 6
1599 struct sfdp_header {
1600 u32 signature; /* Ox50444653U <=> "SFDP" */
1603 u8 nph; /* 0-base number of parameter headers */
1606 /* Basic Flash Parameter Table. */
1607 struct sfdp_parameter_header bfpt_header;
1610 /* Basic Flash Parameter Table */
1613 * JESD216 rev B defines a Basic Flash Parameter Table of 16 DWORDs.
1614 * They are indexed from 1 but C arrays are indexed from 0.
1616 #define BFPT_DWORD(i) ((i) - 1)
1617 #define BFPT_DWORD_MAX 16
1619 /* The first version of JESB216 defined only 9 DWORDs. */
1620 #define BFPT_DWORD_MAX_JESD216 9
1623 #define BFPT_DWORD1_FAST_READ_1_1_2 BIT(16)
1624 #define BFPT_DWORD1_ADDRESS_BYTES_MASK GENMASK(18, 17)
1625 #define BFPT_DWORD1_ADDRESS_BYTES_3_ONLY (0x0UL << 17)
1626 #define BFPT_DWORD1_ADDRESS_BYTES_3_OR_4 (0x1UL << 17)
1627 #define BFPT_DWORD1_ADDRESS_BYTES_4_ONLY (0x2UL << 17)
1628 #define BFPT_DWORD1_DTR BIT(19)
1629 #define BFPT_DWORD1_FAST_READ_1_2_2 BIT(20)
1630 #define BFPT_DWORD1_FAST_READ_1_4_4 BIT(21)
1631 #define BFPT_DWORD1_FAST_READ_1_1_4 BIT(22)
1634 #define BFPT_DWORD5_FAST_READ_2_2_2 BIT(0)
1635 #define BFPT_DWORD5_FAST_READ_4_4_4 BIT(4)
1638 #define BFPT_DWORD11_PAGE_SIZE_SHIFT 4
1639 #define BFPT_DWORD11_PAGE_SIZE_MASK GENMASK(7, 4)
1644 * (from JESD216 rev B)
1645 * Quad Enable Requirements (QER):
1646 * - 000b: Device does not have a QE bit. Device detects 1-1-4 and 1-4-4
1647 * reads based on instruction. DQ3/HOLD# functions are hold during
1648 * instruction phase.
1649 * - 001b: QE is bit 1 of status register 2. It is set via Write Status with
1650 * two data bytes where bit 1 of the second byte is one.
1652 * Writing only one byte to the status register has the side-effect of
1653 * clearing status register 2, including the QE bit. The 100b code is
1654 * used if writing one byte to the status register does not modify
1655 * status register 2.
1656 * - 010b: QE is bit 6 of status register 1. It is set via Write Status with
1657 * one data byte where bit 6 is one.
1659 * - 011b: QE is bit 7 of status register 2. It is set via Write status
1660 * register 2 instruction 3Eh with one data byte where bit 7 is one.
1662 * The status register 2 is read using instruction 3Fh.
1663 * - 100b: QE is bit 1 of status register 2. It is set via Write Status with
1664 * two data bytes where bit 1 of the second byte is one.
1666 * In contrast to the 001b code, writing one byte to the status
1667 * register does not modify status register 2.
1668 * - 101b: QE is bit 1 of status register 2. Status register 1 is read using
1669 * Read Status instruction 05h. Status register2 is read using
1670 * instruction 35h. QE is set via Writ Status instruction 01h with
1671 * two data bytes where bit 1 of the second byte is one.
1674 #define BFPT_DWORD15_QER_MASK GENMASK(22, 20)
1675 #define BFPT_DWORD15_QER_NONE (0x0UL << 20) /* Micron */
1676 #define BFPT_DWORD15_QER_SR2_BIT1_BUGGY (0x1UL << 20)
1677 #define BFPT_DWORD15_QER_SR1_BIT6 (0x2UL << 20) /* Macronix */
1678 #define BFPT_DWORD15_QER_SR2_BIT7 (0x3UL << 20)
1679 #define BFPT_DWORD15_QER_SR2_BIT1_NO_RD (0x4UL << 20)
1680 #define BFPT_DWORD15_QER_SR2_BIT1 (0x5UL << 20) /* Spansion */
1683 u32 dwords[BFPT_DWORD_MAX];
1686 /* Fast Read settings. */
1689 spi_nor_set_read_settings_from_bfpt(struct spi_nor_read_command *read,
1691 enum spi_nor_protocol proto)
1693 read->num_mode_clocks = (half >> 5) & 0x07;
1694 read->num_wait_states = (half >> 0) & 0x1f;
1695 read->opcode = (half >> 8) & 0xff;
1696 read->proto = proto;
1699 struct sfdp_bfpt_read {
1700 /* The Fast Read x-y-z hardware capability in params->hwcaps.mask. */
1704 * The <supported_bit> bit in <supported_dword> BFPT DWORD tells us
1705 * whether the Fast Read x-y-z command is supported.
1707 u32 supported_dword;
1711 * The half-word at offset <setting_shift> in <setting_dword> BFPT DWORD
1712 * encodes the op code, the number of mode clocks and the number of wait
1713 * states to be used by Fast Read x-y-z command.
1718 /* The SPI protocol for this Fast Read x-y-z command. */
1719 enum spi_nor_protocol proto;
1722 static const struct sfdp_bfpt_read sfdp_bfpt_reads[] = {
1723 /* Fast Read 1-1-2 */
1725 SNOR_HWCAPS_READ_1_1_2,
1726 BFPT_DWORD(1), BIT(16), /* Supported bit */
1727 BFPT_DWORD(4), 0, /* Settings */
1731 /* Fast Read 1-2-2 */
1733 SNOR_HWCAPS_READ_1_2_2,
1734 BFPT_DWORD(1), BIT(20), /* Supported bit */
1735 BFPT_DWORD(4), 16, /* Settings */
1739 /* Fast Read 2-2-2 */
1741 SNOR_HWCAPS_READ_2_2_2,
1742 BFPT_DWORD(5), BIT(0), /* Supported bit */
1743 BFPT_DWORD(6), 16, /* Settings */
1747 /* Fast Read 1-1-4 */
1749 SNOR_HWCAPS_READ_1_1_4,
1750 BFPT_DWORD(1), BIT(22), /* Supported bit */
1751 BFPT_DWORD(3), 16, /* Settings */
1755 /* Fast Read 1-4-4 */
1757 SNOR_HWCAPS_READ_1_4_4,
1758 BFPT_DWORD(1), BIT(21), /* Supported bit */
1759 BFPT_DWORD(3), 0, /* Settings */
1763 /* Fast Read 4-4-4 */
1765 SNOR_HWCAPS_READ_4_4_4,
1766 BFPT_DWORD(5), BIT(4), /* Supported bit */
1767 BFPT_DWORD(7), 16, /* Settings */
1772 struct sfdp_bfpt_erase {
1774 * The half-word at offset <shift> in DWORD <dwoard> encodes the
1775 * op code and erase sector size to be used by Sector Erase commands.
1781 static const struct sfdp_bfpt_erase sfdp_bfpt_erases[] = {
1782 /* Erase Type 1 in DWORD8 bits[15:0] */
1785 /* Erase Type 2 in DWORD8 bits[31:16] */
1786 {BFPT_DWORD(8), 16},
1788 /* Erase Type 3 in DWORD9 bits[15:0] */
1791 /* Erase Type 4 in DWORD9 bits[31:16] */
1792 {BFPT_DWORD(9), 16},
1795 static int spi_nor_hwcaps_read2cmd(u32 hwcaps);
1798 * spi_nor_parse_bfpt() - read and parse the Basic Flash Parameter Table.
1799 * @nor: pointer to a 'struct spi_nor'
1800 * @bfpt_header: pointer to the 'struct sfdp_parameter_header' describing
1801 * the Basic Flash Parameter Table length and version
1802 * @params: pointer to the 'struct spi_nor_flash_parameter' to be
1805 * The Basic Flash Parameter Table is the main and only mandatory table as
1806 * defined by the SFDP (JESD216) specification.
1807 * It provides us with the total size (memory density) of the data array and
1808 * the number of address bytes for Fast Read, Page Program and Sector Erase
1810 * For Fast READ commands, it also gives the number of mode clock cycles and
1811 * wait states (regrouped in the number of dummy clock cycles) for each
1812 * supported instruction op code.
1813 * For Page Program, the page size is now available since JESD216 rev A, however
1814 * the supported instruction op codes are still not provided.
1815 * For Sector Erase commands, this table stores the supported instruction op
1816 * codes and the associated sector sizes.
1817 * Finally, the Quad Enable Requirements (QER) are also available since JESD216
1818 * rev A. The QER bits encode the manufacturer dependent procedure to be
1819 * executed to set the Quad Enable (QE) bit in some internal register of the
1820 * Quad SPI memory. Indeed the QE bit, when it exists, must be set before
1821 * sending any Quad SPI command to the memory. Actually, setting the QE bit
1822 * tells the memory to reassign its WP# and HOLD#/RESET# pins to functions IO2
1823 * and IO3 hence enabling 4 (Quad) I/O lines.
1825 * Return: 0 on success, -errno otherwise.
1827 static int spi_nor_parse_bfpt(struct spi_nor *nor,
1828 const struct sfdp_parameter_header *bfpt_header,
1829 struct spi_nor_flash_parameter *params)
1831 struct mtd_info *mtd = &nor->mtd;
1832 struct sfdp_bfpt bfpt;
1838 /* JESD216 Basic Flash Parameter Table length is at least 9 DWORDs. */
1839 if (bfpt_header->length < BFPT_DWORD_MAX_JESD216)
1842 /* Read the Basic Flash Parameter Table. */
1843 len = min_t(size_t, sizeof(bfpt),
1844 bfpt_header->length * sizeof(u32));
1845 addr = SFDP_PARAM_HEADER_PTP(bfpt_header);
1846 memset(&bfpt, 0, sizeof(bfpt));
1847 err = spi_nor_read_sfdp(nor, addr, len, &bfpt);
1851 /* Fix endianness of the BFPT DWORDs. */
1852 for (i = 0; i < BFPT_DWORD_MAX; i++)
1853 bfpt.dwords[i] = le32_to_cpu(bfpt.dwords[i]);
1855 /* Number of address bytes. */
1856 switch (bfpt.dwords[BFPT_DWORD(1)] & BFPT_DWORD1_ADDRESS_BYTES_MASK) {
1857 case BFPT_DWORD1_ADDRESS_BYTES_3_ONLY:
1858 nor->addr_width = 3;
1861 case BFPT_DWORD1_ADDRESS_BYTES_4_ONLY:
1862 nor->addr_width = 4;
1869 /* Flash Memory Density (in bits). */
1870 params->size = bfpt.dwords[BFPT_DWORD(2)];
1871 if (params->size & BIT(31)) {
1872 params->size &= ~BIT(31);
1875 * Prevent overflows on params->size. Anyway, a NOR of 2^64
1876 * bits is unlikely to exist so this error probably means
1877 * the BFPT we are reading is corrupted/wrong.
1879 if (params->size > 63)
1882 params->size = 1ULL << params->size;
1886 params->size >>= 3; /* Convert to bytes. */
1888 /* Fast Read settings. */
1889 for (i = 0; i < ARRAY_SIZE(sfdp_bfpt_reads); i++) {
1890 const struct sfdp_bfpt_read *rd = &sfdp_bfpt_reads[i];
1891 struct spi_nor_read_command *read;
1893 if (!(bfpt.dwords[rd->supported_dword] & rd->supported_bit)) {
1894 params->hwcaps.mask &= ~rd->hwcaps;
1898 params->hwcaps.mask |= rd->hwcaps;
1899 cmd = spi_nor_hwcaps_read2cmd(rd->hwcaps);
1900 read = ¶ms->reads[cmd];
1901 half = bfpt.dwords[rd->settings_dword] >> rd->settings_shift;
1902 spi_nor_set_read_settings_from_bfpt(read, half, rd->proto);
1905 /* Sector Erase settings. */
1906 for (i = 0; i < ARRAY_SIZE(sfdp_bfpt_erases); i++) {
1907 const struct sfdp_bfpt_erase *er = &sfdp_bfpt_erases[i];
1911 half = bfpt.dwords[er->dword] >> er->shift;
1912 erasesize = half & 0xff;
1914 /* erasesize == 0 means this Erase Type is not supported. */
1918 erasesize = 1U << erasesize;
1919 opcode = (half >> 8) & 0xff;
1920 #ifdef CONFIG_SPI_FLASH_USE_4K_SECTORS
1921 if (erasesize == SZ_4K) {
1922 nor->erase_opcode = opcode;
1923 mtd->erasesize = erasesize;
1927 if (!mtd->erasesize || mtd->erasesize < erasesize) {
1928 nor->erase_opcode = opcode;
1929 mtd->erasesize = erasesize;
1933 /* Stop here if not JESD216 rev A or later. */
1934 if (bfpt_header->length < BFPT_DWORD_MAX)
1937 /* Page size: this field specifies 'N' so the page size = 2^N bytes. */
1938 params->page_size = bfpt.dwords[BFPT_DWORD(11)];
1939 params->page_size &= BFPT_DWORD11_PAGE_SIZE_MASK;
1940 params->page_size >>= BFPT_DWORD11_PAGE_SIZE_SHIFT;
1941 params->page_size = 1U << params->page_size;
1943 /* Quad Enable Requirements. */
1944 switch (bfpt.dwords[BFPT_DWORD(15)] & BFPT_DWORD15_QER_MASK) {
1945 case BFPT_DWORD15_QER_NONE:
1946 params->quad_enable = NULL;
1948 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
1949 case BFPT_DWORD15_QER_SR2_BIT1_BUGGY:
1950 case BFPT_DWORD15_QER_SR2_BIT1_NO_RD:
1951 params->quad_enable = spansion_no_read_cr_quad_enable;
1954 #ifdef CONFIG_SPI_FLASH_MACRONIX
1955 case BFPT_DWORD15_QER_SR1_BIT6:
1956 params->quad_enable = macronix_quad_enable;
1959 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
1960 case BFPT_DWORD15_QER_SR2_BIT1:
1961 params->quad_enable = spansion_read_cr_quad_enable;
1972 * spi_nor_parse_microchip_sfdp() - parse the Microchip manufacturer specific
1974 * @nor: pointer to a 'struct spi_nor'.
1975 * @param_header: pointer to the SFDP parameter header.
1977 * Return: 0 on success, -errno otherwise.
1980 spi_nor_parse_microchip_sfdp(struct spi_nor *nor,
1981 const struct sfdp_parameter_header *param_header)
1987 size = param_header->length * sizeof(u32);
1988 addr = SFDP_PARAM_HEADER_PTP(param_header);
1990 nor->manufacturer_sfdp = devm_kmalloc(nor->dev, size, GFP_KERNEL);
1991 if (!nor->manufacturer_sfdp)
1994 ret = spi_nor_read_sfdp(nor, addr, size, nor->manufacturer_sfdp);
2000 * spi_nor_parse_sfdp() - parse the Serial Flash Discoverable Parameters.
2001 * @nor: pointer to a 'struct spi_nor'
2002 * @params: pointer to the 'struct spi_nor_flash_parameter' to be
2005 * The Serial Flash Discoverable Parameters are described by the JEDEC JESD216
2006 * specification. This is a standard which tends to supported by almost all
2007 * (Q)SPI memory manufacturers. Those hard-coded tables allow us to learn at
2008 * runtime the main parameters needed to perform basic SPI flash operations such
2009 * as Fast Read, Page Program or Sector Erase commands.
2011 * Return: 0 on success, -errno otherwise.
2013 static int spi_nor_parse_sfdp(struct spi_nor *nor,
2014 struct spi_nor_flash_parameter *params)
2016 const struct sfdp_parameter_header *param_header, *bfpt_header;
2017 struct sfdp_parameter_header *param_headers = NULL;
2018 struct sfdp_header header;
2022 /* Get the SFDP header. */
2023 err = spi_nor_read_sfdp(nor, 0, sizeof(header), &header);
2027 /* Check the SFDP header version. */
2028 if (le32_to_cpu(header.signature) != SFDP_SIGNATURE ||
2029 header.major != SFDP_JESD216_MAJOR)
2033 * Verify that the first and only mandatory parameter header is a
2034 * Basic Flash Parameter Table header as specified in JESD216.
2036 bfpt_header = &header.bfpt_header;
2037 if (SFDP_PARAM_HEADER_ID(bfpt_header) != SFDP_BFPT_ID ||
2038 bfpt_header->major != SFDP_JESD216_MAJOR)
2042 * Allocate memory then read all parameter headers with a single
2043 * Read SFDP command. These parameter headers will actually be parsed
2044 * twice: a first time to get the latest revision of the basic flash
2045 * parameter table, then a second time to handle the supported optional
2047 * Hence we read the parameter headers once for all to reduce the
2048 * processing time. Also we use kmalloc() instead of devm_kmalloc()
2049 * because we don't need to keep these parameter headers: the allocated
2050 * memory is always released with kfree() before exiting this function.
2053 psize = header.nph * sizeof(*param_headers);
2055 param_headers = kmalloc(psize, GFP_KERNEL);
2059 err = spi_nor_read_sfdp(nor, sizeof(header),
2060 psize, param_headers);
2062 dev_err(dev, "failed to read SFDP parameter headers\n");
2068 * Check other parameter headers to get the latest revision of
2069 * the basic flash parameter table.
2071 for (i = 0; i < header.nph; i++) {
2072 param_header = ¶m_headers[i];
2074 if (SFDP_PARAM_HEADER_ID(param_header) == SFDP_BFPT_ID &&
2075 param_header->major == SFDP_JESD216_MAJOR &&
2076 (param_header->minor > bfpt_header->minor ||
2077 (param_header->minor == bfpt_header->minor &&
2078 param_header->length > bfpt_header->length)))
2079 bfpt_header = param_header;
2082 err = spi_nor_parse_bfpt(nor, bfpt_header, params);
2086 /* Parse other parameter headers. */
2087 for (i = 0; i < header.nph; i++) {
2088 param_header = ¶m_headers[i];
2090 switch (SFDP_PARAM_HEADER_ID(param_header)) {
2091 case SFDP_SECTOR_MAP_ID:
2092 dev_info(dev, "non-uniform erase sector maps are not supported yet.\n");
2096 err = spi_nor_parse_microchip_sfdp(nor, param_header);
2104 dev_warn(dev, "Failed to parse optional parameter table: %04x\n",
2105 SFDP_PARAM_HEADER_ID(param_header));
2107 * Let's not drop all information we extracted so far
2108 * if optional table parsers fail. In case of failing,
2109 * each optional parser is responsible to roll back to
2110 * the previously known spi_nor data.
2117 kfree(param_headers);
2121 static int spi_nor_parse_sfdp(struct spi_nor *nor,
2122 struct spi_nor_flash_parameter *params)
2126 #endif /* SPI_FLASH_SFDP_SUPPORT */
2128 static int spi_nor_init_params(struct spi_nor *nor,
2129 const struct flash_info *info,
2130 struct spi_nor_flash_parameter *params)
2132 /* Set legacy flash parameters as default. */
2133 memset(params, 0, sizeof(*params));
2135 /* Set SPI NOR sizes. */
2136 params->size = info->sector_size * info->n_sectors;
2137 params->page_size = info->page_size;
2139 /* (Fast) Read settings. */
2140 params->hwcaps.mask |= SNOR_HWCAPS_READ;
2141 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ],
2142 0, 0, SPINOR_OP_READ,
2145 if (!(info->flags & SPI_NOR_NO_FR)) {
2146 params->hwcaps.mask |= SNOR_HWCAPS_READ_FAST;
2147 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_FAST],
2148 0, 8, SPINOR_OP_READ_FAST,
2152 if (info->flags & SPI_NOR_DUAL_READ) {
2153 params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_2;
2154 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_2],
2155 0, 8, SPINOR_OP_READ_1_1_2,
2159 if (info->flags & SPI_NOR_QUAD_READ) {
2160 params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4;
2161 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_4],
2162 0, 8, SPINOR_OP_READ_1_1_4,
2166 /* Page Program settings. */
2167 params->hwcaps.mask |= SNOR_HWCAPS_PP;
2168 spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP],
2169 SPINOR_OP_PP, SNOR_PROTO_1_1_1);
2171 if (info->flags & SPI_NOR_QUAD_READ) {
2172 params->hwcaps.mask |= SNOR_HWCAPS_PP_1_1_4;
2173 spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP_1_1_4],
2174 SPINOR_OP_PP_1_1_4, SNOR_PROTO_1_1_4);
2177 /* Select the procedure to set the Quad Enable bit. */
2178 if (params->hwcaps.mask & (SNOR_HWCAPS_READ_QUAD |
2179 SNOR_HWCAPS_PP_QUAD)) {
2180 switch (JEDEC_MFR(info)) {
2181 #ifdef CONFIG_SPI_FLASH_MACRONIX
2182 case SNOR_MFR_MACRONIX:
2183 params->quad_enable = macronix_quad_enable;
2187 case SNOR_MFR_MICRON:
2191 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
2192 /* Kept only for backward compatibility purpose. */
2193 params->quad_enable = spansion_read_cr_quad_enable;
2199 /* Override the parameters with data read from SFDP tables. */
2200 nor->addr_width = 0;
2201 nor->mtd.erasesize = 0;
2202 if ((info->flags & (SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)) &&
2203 !(info->flags & SPI_NOR_SKIP_SFDP)) {
2204 struct spi_nor_flash_parameter sfdp_params;
2206 memcpy(&sfdp_params, params, sizeof(sfdp_params));
2207 if (spi_nor_parse_sfdp(nor, &sfdp_params)) {
2208 nor->addr_width = 0;
2209 nor->mtd.erasesize = 0;
2211 memcpy(params, &sfdp_params, sizeof(*params));
2218 static int spi_nor_hwcaps2cmd(u32 hwcaps, const int table[][2], size_t size)
2222 for (i = 0; i < size; i++)
2223 if (table[i][0] == (int)hwcaps)
2229 static int spi_nor_hwcaps_read2cmd(u32 hwcaps)
2231 static const int hwcaps_read2cmd[][2] = {
2232 { SNOR_HWCAPS_READ, SNOR_CMD_READ },
2233 { SNOR_HWCAPS_READ_FAST, SNOR_CMD_READ_FAST },
2234 { SNOR_HWCAPS_READ_1_1_1_DTR, SNOR_CMD_READ_1_1_1_DTR },
2235 { SNOR_HWCAPS_READ_1_1_2, SNOR_CMD_READ_1_1_2 },
2236 { SNOR_HWCAPS_READ_1_2_2, SNOR_CMD_READ_1_2_2 },
2237 { SNOR_HWCAPS_READ_2_2_2, SNOR_CMD_READ_2_2_2 },
2238 { SNOR_HWCAPS_READ_1_2_2_DTR, SNOR_CMD_READ_1_2_2_DTR },
2239 { SNOR_HWCAPS_READ_1_1_4, SNOR_CMD_READ_1_1_4 },
2240 { SNOR_HWCAPS_READ_1_4_4, SNOR_CMD_READ_1_4_4 },
2241 { SNOR_HWCAPS_READ_4_4_4, SNOR_CMD_READ_4_4_4 },
2242 { SNOR_HWCAPS_READ_1_4_4_DTR, SNOR_CMD_READ_1_4_4_DTR },
2243 { SNOR_HWCAPS_READ_1_1_8, SNOR_CMD_READ_1_1_8 },
2244 { SNOR_HWCAPS_READ_1_8_8, SNOR_CMD_READ_1_8_8 },
2245 { SNOR_HWCAPS_READ_8_8_8, SNOR_CMD_READ_8_8_8 },
2246 { SNOR_HWCAPS_READ_1_8_8_DTR, SNOR_CMD_READ_1_8_8_DTR },
2249 return spi_nor_hwcaps2cmd(hwcaps, hwcaps_read2cmd,
2250 ARRAY_SIZE(hwcaps_read2cmd));
2253 static int spi_nor_hwcaps_pp2cmd(u32 hwcaps)
2255 static const int hwcaps_pp2cmd[][2] = {
2256 { SNOR_HWCAPS_PP, SNOR_CMD_PP },
2257 { SNOR_HWCAPS_PP_1_1_4, SNOR_CMD_PP_1_1_4 },
2258 { SNOR_HWCAPS_PP_1_4_4, SNOR_CMD_PP_1_4_4 },
2259 { SNOR_HWCAPS_PP_4_4_4, SNOR_CMD_PP_4_4_4 },
2260 { SNOR_HWCAPS_PP_1_1_8, SNOR_CMD_PP_1_1_8 },
2261 { SNOR_HWCAPS_PP_1_8_8, SNOR_CMD_PP_1_8_8 },
2262 { SNOR_HWCAPS_PP_8_8_8, SNOR_CMD_PP_8_8_8 },
2265 return spi_nor_hwcaps2cmd(hwcaps, hwcaps_pp2cmd,
2266 ARRAY_SIZE(hwcaps_pp2cmd));
2269 static int spi_nor_select_read(struct spi_nor *nor,
2270 const struct spi_nor_flash_parameter *params,
2273 int cmd, best_match = fls(shared_hwcaps & SNOR_HWCAPS_READ_MASK) - 1;
2274 const struct spi_nor_read_command *read;
2279 cmd = spi_nor_hwcaps_read2cmd(BIT(best_match));
2283 read = ¶ms->reads[cmd];
2284 nor->read_opcode = read->opcode;
2285 nor->read_proto = read->proto;
2288 * In the spi-nor framework, we don't need to make the difference
2289 * between mode clock cycles and wait state clock cycles.
2290 * Indeed, the value of the mode clock cycles is used by a QSPI
2291 * flash memory to know whether it should enter or leave its 0-4-4
2292 * (Continuous Read / XIP) mode.
2293 * eXecution In Place is out of the scope of the mtd sub-system.
2294 * Hence we choose to merge both mode and wait state clock cycles
2295 * into the so called dummy clock cycles.
2297 nor->read_dummy = read->num_mode_clocks + read->num_wait_states;
2301 static int spi_nor_select_pp(struct spi_nor *nor,
2302 const struct spi_nor_flash_parameter *params,
2305 int cmd, best_match = fls(shared_hwcaps & SNOR_HWCAPS_PP_MASK) - 1;
2306 const struct spi_nor_pp_command *pp;
2311 cmd = spi_nor_hwcaps_pp2cmd(BIT(best_match));
2315 pp = ¶ms->page_programs[cmd];
2316 nor->program_opcode = pp->opcode;
2317 nor->write_proto = pp->proto;
2321 static int spi_nor_select_erase(struct spi_nor *nor,
2322 const struct flash_info *info)
2324 struct mtd_info *mtd = &nor->mtd;
2326 /* Do nothing if already configured from SFDP. */
2330 #ifdef CONFIG_SPI_FLASH_USE_4K_SECTORS
2331 /* prefer "small sector" erase if possible */
2332 if (info->flags & SECT_4K) {
2333 nor->erase_opcode = SPINOR_OP_BE_4K;
2334 mtd->erasesize = 4096;
2335 } else if (info->flags & SECT_4K_PMC) {
2336 nor->erase_opcode = SPINOR_OP_BE_4K_PMC;
2337 mtd->erasesize = 4096;
2341 nor->erase_opcode = SPINOR_OP_SE;
2342 mtd->erasesize = info->sector_size;
2347 static int spi_nor_setup(struct spi_nor *nor, const struct flash_info *info,
2348 const struct spi_nor_flash_parameter *params,
2349 const struct spi_nor_hwcaps *hwcaps)
2351 u32 ignored_mask, shared_mask;
2352 bool enable_quad_io;
2356 * Keep only the hardware capabilities supported by both the SPI
2357 * controller and the SPI flash memory.
2359 shared_mask = hwcaps->mask & params->hwcaps.mask;
2361 /* SPI n-n-n protocols are not supported yet. */
2362 ignored_mask = (SNOR_HWCAPS_READ_2_2_2 |
2363 SNOR_HWCAPS_READ_4_4_4 |
2364 SNOR_HWCAPS_READ_8_8_8 |
2365 SNOR_HWCAPS_PP_4_4_4 |
2366 SNOR_HWCAPS_PP_8_8_8);
2367 if (shared_mask & ignored_mask) {
2369 "SPI n-n-n protocols are not supported yet.\n");
2370 shared_mask &= ~ignored_mask;
2373 /* Select the (Fast) Read command. */
2374 err = spi_nor_select_read(nor, params, shared_mask);
2377 "can't select read settings supported by both the SPI controller and memory.\n");
2381 /* Select the Page Program command. */
2382 err = spi_nor_select_pp(nor, params, shared_mask);
2385 "can't select write settings supported by both the SPI controller and memory.\n");
2389 /* Select the Sector Erase command. */
2390 err = spi_nor_select_erase(nor, info);
2393 "can't select erase settings supported by both the SPI controller and memory.\n");
2397 /* Enable Quad I/O if needed. */
2398 enable_quad_io = (spi_nor_get_protocol_width(nor->read_proto) == 4 ||
2399 spi_nor_get_protocol_width(nor->write_proto) == 4);
2400 if (enable_quad_io && params->quad_enable)
2401 nor->quad_enable = params->quad_enable;
2403 nor->quad_enable = NULL;
2408 static int spi_nor_init(struct spi_nor *nor)
2413 * Atmel, SST, Intel/Numonyx, and others serial NOR tend to power up
2414 * with the software protection bits set
2416 if (JEDEC_MFR(nor->info) == SNOR_MFR_ATMEL ||
2417 JEDEC_MFR(nor->info) == SNOR_MFR_INTEL ||
2418 JEDEC_MFR(nor->info) == SNOR_MFR_SST ||
2419 nor->info->flags & SPI_NOR_HAS_LOCK) {
2422 spi_nor_wait_till_ready(nor);
2425 if (nor->quad_enable) {
2426 err = nor->quad_enable(nor);
2428 dev_dbg(nor->dev, "quad mode not supported\n");
2433 if (nor->addr_width == 4 &&
2434 (JEDEC_MFR(nor->info) != SNOR_MFR_SPANSION) &&
2435 !(nor->info->flags & SPI_NOR_4B_OPCODES)) {
2437 * If the RESET# pin isn't hooked up properly, or the system
2438 * otherwise doesn't perform a reset command in the boot
2439 * sequence, it's impossible to 100% protect against unexpected
2440 * reboots (e.g., crashes). Warn the user (or hopefully, system
2441 * designer) that this is bad.
2443 if (nor->flags & SNOR_F_BROKEN_RESET)
2444 printf("enabling reset hack; may not recover from unexpected reboots\n");
2445 set_4byte(nor, nor->info, 1);
2451 int spi_nor_scan(struct spi_nor *nor)
2453 struct spi_nor_flash_parameter params;
2454 const struct flash_info *info = NULL;
2455 struct mtd_info *mtd = &nor->mtd;
2456 struct spi_nor_hwcaps hwcaps = {
2457 .mask = SNOR_HWCAPS_READ |
2458 SNOR_HWCAPS_READ_FAST |
2461 struct spi_slave *spi = nor->spi;
2464 /* Reset SPI protocol for all commands. */
2465 nor->reg_proto = SNOR_PROTO_1_1_1;
2466 nor->read_proto = SNOR_PROTO_1_1_1;
2467 nor->write_proto = SNOR_PROTO_1_1_1;
2468 nor->read = spi_nor_read_data;
2469 nor->write = spi_nor_write_data;
2470 nor->read_reg = spi_nor_read_reg;
2471 nor->write_reg = spi_nor_write_reg;
2473 if (spi->mode & SPI_RX_QUAD) {
2474 hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4;
2476 if (spi->mode & SPI_TX_QUAD)
2477 hwcaps.mask |= (SNOR_HWCAPS_READ_1_4_4 |
2478 SNOR_HWCAPS_PP_1_1_4 |
2479 SNOR_HWCAPS_PP_1_4_4);
2480 } else if (spi->mode & SPI_RX_DUAL) {
2481 hwcaps.mask |= SNOR_HWCAPS_READ_1_1_2;
2483 if (spi->mode & SPI_TX_DUAL)
2484 hwcaps.mask |= SNOR_HWCAPS_READ_1_2_2;
2487 info = spi_nor_read_id(nor);
2488 if (IS_ERR_OR_NULL(info))
2490 /* Parse the Serial Flash Discoverable Parameters table. */
2491 ret = spi_nor_init_params(nor, info, ¶ms);
2496 mtd->name = info->name;
2498 mtd->type = MTD_NORFLASH;
2500 mtd->flags = MTD_CAP_NORFLASH;
2501 mtd->size = params.size;
2502 mtd->_erase = spi_nor_erase;
2503 mtd->_read = spi_nor_read;
2505 #if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST)
2506 /* NOR protection support for STmicro/Micron chips and similar */
2507 if (JEDEC_MFR(info) == SNOR_MFR_ST ||
2508 JEDEC_MFR(info) == SNOR_MFR_MICRON ||
2509 JEDEC_MFR(info) == SNOR_MFR_SST ||
2510 info->flags & SPI_NOR_HAS_LOCK) {
2511 nor->flash_lock = stm_lock;
2512 nor->flash_unlock = stm_unlock;
2513 nor->flash_is_locked = stm_is_locked;
2517 #ifdef CONFIG_SPI_FLASH_SST
2519 * sst26 series block protection implementation differs from other
2522 if (info->flags & SPI_NOR_HAS_SST26LOCK) {
2523 nor->flash_lock = sst26_lock;
2524 nor->flash_unlock = sst26_unlock;
2525 nor->flash_is_locked = sst26_is_locked;
2528 /* sst nor chips use AAI word program */
2529 if (info->flags & SST_WRITE)
2530 mtd->_write = sst_write;
2533 mtd->_write = spi_nor_write;
2535 if (info->flags & USE_FSR)
2536 nor->flags |= SNOR_F_USE_FSR;
2537 if (info->flags & SPI_NOR_HAS_TB)
2538 nor->flags |= SNOR_F_HAS_SR_TB;
2539 if (info->flags & NO_CHIP_ERASE)
2540 nor->flags |= SNOR_F_NO_OP_CHIP_ERASE;
2541 if (info->flags & USE_CLSR)
2542 nor->flags |= SNOR_F_USE_CLSR;
2544 if (info->flags & SPI_NOR_NO_ERASE)
2545 mtd->flags |= MTD_NO_ERASE;
2547 nor->page_size = params.page_size;
2548 mtd->writebufsize = nor->page_size;
2550 /* Some devices cannot do fast-read, no matter what DT tells us */
2551 if ((info->flags & SPI_NOR_NO_FR) || (spi->mode & SPI_RX_SLOW))
2552 params.hwcaps.mask &= ~SNOR_HWCAPS_READ_FAST;
2555 * Configure the SPI memory:
2556 * - select op codes for (Fast) Read, Page Program and Sector Erase.
2557 * - set the number of dummy cycles (mode cycles + wait states).
2558 * - set the SPI protocols for register and memory accesses.
2559 * - set the Quad Enable bit if needed (required by SPI x-y-4 protos).
2561 ret = spi_nor_setup(nor, info, ¶ms, &hwcaps);
2565 if (nor->addr_width) {
2566 /* already configured from SFDP */
2567 } else if (info->addr_width) {
2568 nor->addr_width = info->addr_width;
2569 } else if (mtd->size > SZ_16M) {
2570 #ifndef CONFIG_SPI_FLASH_BAR
2571 /* enable 4-byte addressing if the device exceeds 16MiB */
2572 nor->addr_width = 4;
2573 if (JEDEC_MFR(info) == SNOR_MFR_SPANSION ||
2574 info->flags & SPI_NOR_4B_OPCODES)
2575 spi_nor_set_4byte_opcodes(nor, info);
2577 /* Configure the BAR - discover bank cmds and read current bank */
2578 nor->addr_width = 3;
2579 ret = read_bar(nor, info);
2584 nor->addr_width = 3;
2587 if (nor->addr_width > SPI_NOR_MAX_ADDR_WIDTH) {
2588 dev_dbg(dev, "address width is too large: %u\n",
2593 /* Send all the required SPI flash commands to initialize device */
2595 ret = spi_nor_init(nor);
2599 nor->name = mtd->name;
2600 nor->size = mtd->size;
2601 nor->erase_size = mtd->erasesize;
2602 nor->sector_size = mtd->erasesize;
2604 #ifndef CONFIG_SPL_BUILD
2605 printf("SF: Detected %s with page size ", nor->name);
2606 print_size(nor->page_size, ", erase size ");
2607 print_size(nor->erase_size, ", total ");
2608 print_size(nor->size, "");
2615 /* U-Boot specific functions, need to extend MTD to support these */
2616 int spi_flash_cmd_get_sw_write_prot(struct spi_nor *nor)
2618 int sr = read_sr(nor);
2623 return (sr >> 2) & 7;