4 * Copyright (C) 2008 Atmel Corporation
5 * Copyright (C) 2010 Reinhard Meyer, EMK Elektronik
6 * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc.
8 * SPDX-License-Identifier: GPL-2.0+
13 #include <spi_flash.h>
16 #include "sf_internal.h"
18 static void spi_flash_addr(u32 addr, u8 *cmd)
20 /* cmd[0] is actual command */
26 int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr)
31 cmd = CMD_WRITE_STATUS;
32 ret = spi_flash_write_common(flash, &cmd, 1, &sr, 1);
34 debug("SF: fail to write status register\n");
41 static int spi_flash_cmd_write_config(struct spi_flash *flash, u8 cr)
47 cmd = CMD_READ_STATUS;
48 ret = spi_flash_read_common(flash, &cmd, 1, &data[0], 1);
50 debug("SF: fail to read status register\n");
54 cmd = CMD_WRITE_STATUS;
56 ret = spi_flash_write_common(flash, &cmd, 1, &data, 2);
58 debug("SF: fail to write config register\n");
65 #ifdef CONFIG_SPI_FLASH_BAR
66 static int spi_flash_cmd_bankaddr_write(struct spi_flash *flash, u8 bank_sel)
71 if (flash->bank_curr == bank_sel) {
72 debug("SF: not require to enable bank%d\n", bank_sel);
76 cmd = flash->bank_write_cmd;
77 ret = spi_flash_write_common(flash, &cmd, 1, &bank_sel, 1);
79 debug("SF: fail to write bank register\n");
82 flash->bank_curr = bank_sel;
87 static int spi_flash_bank(struct spi_flash *flash, u32 offset)
92 bank_sel = offset / SPI_FLASH_16MB_BOUN;
94 ret = spi_flash_cmd_bankaddr_write(flash, bank_sel);
96 debug("SF: fail to set bank%d\n", bank_sel);
104 int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout)
106 struct spi_slave *spi = flash->spi;
107 unsigned long timebase;
110 u8 check_status = 0x0;
111 u8 poll_bit = STATUS_WIP;
112 u8 cmd = flash->poll_cmd;
114 if (cmd == CMD_FLAG_STATUS) {
115 poll_bit = STATUS_PEC;
116 check_status = poll_bit;
119 ret = spi_xfer(spi, 8, &cmd, NULL, SPI_XFER_BEGIN);
121 debug("SF: fail to read %s status register\n",
122 cmd == CMD_READ_STATUS ? "read" : "flag");
126 timebase = get_timer(0);
130 ret = spi_xfer(spi, 8, NULL, &status, 0);
134 if ((status & poll_bit) == check_status)
137 } while (get_timer(timebase) < timeout);
139 spi_xfer(spi, 0, NULL, NULL, SPI_XFER_END);
141 if ((status & poll_bit) == check_status)
145 debug("SF: time out!\n");
149 int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd,
150 size_t cmd_len, const void *buf, size_t buf_len)
152 struct spi_slave *spi = flash->spi;
153 unsigned long timeout = SPI_FLASH_PROG_TIMEOUT;
157 timeout = SPI_FLASH_PAGE_ERASE_TIMEOUT;
159 ret = spi_claim_bus(flash->spi);
161 debug("SF: unable to claim SPI bus\n");
165 ret = spi_flash_cmd_write_enable(flash);
167 debug("SF: enabling write failed\n");
171 ret = spi_flash_cmd_write(spi, cmd, cmd_len, buf, buf_len);
173 debug("SF: write cmd failed\n");
177 ret = spi_flash_cmd_wait_ready(flash, timeout);
179 debug("SF: write %s timed out\n",
180 timeout == SPI_FLASH_PROG_TIMEOUT ?
181 "program" : "page erase");
185 spi_release_bus(spi);
190 int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len)
196 erase_size = flash->erase_size;
197 if (offset % erase_size || len % erase_size) {
198 debug("SF: Erase offset/length not multiple of erase size\n");
202 cmd[0] = flash->erase_cmd;
204 #ifdef CONFIG_SPI_FLASH_BAR
205 ret = spi_flash_bank(flash, offset);
209 spi_flash_addr(offset, cmd);
211 debug("SF: erase %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1],
212 cmd[2], cmd[3], offset);
214 ret = spi_flash_write_common(flash, cmd, sizeof(cmd), NULL, 0);
216 debug("SF: erase failed\n");
220 offset += erase_size;
227 int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,
228 size_t len, const void *buf)
230 unsigned long byte_addr, page_size;
231 size_t chunk_len, actual;
235 page_size = flash->page_size;
237 cmd[0] = flash->write_cmd;
238 for (actual = 0; actual < len; actual += chunk_len) {
239 #ifdef CONFIG_SPI_FLASH_BAR
240 ret = spi_flash_bank(flash, offset);
244 byte_addr = offset % page_size;
245 chunk_len = min(len - actual, page_size - byte_addr);
247 if (flash->spi->max_write_size)
248 chunk_len = min(chunk_len, flash->spi->max_write_size);
250 spi_flash_addr(offset, cmd);
252 debug("PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu\n",
253 buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len);
255 ret = spi_flash_write_common(flash, cmd, sizeof(cmd),
256 buf + actual, chunk_len);
258 debug("SF: write failed\n");
268 int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd,
269 size_t cmd_len, void *data, size_t data_len)
271 struct spi_slave *spi = flash->spi;
274 ret = spi_claim_bus(flash->spi);
276 debug("SF: unable to claim SPI bus\n");
280 ret = spi_flash_cmd_read(spi, cmd, cmd_len, data, data_len);
282 debug("SF: read cmd failed\n");
286 spi_release_bus(spi);
291 int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
292 size_t len, void *data)
294 u8 cmd[5], bank_sel = 0;
295 u32 remain_len, read_len;
298 /* Handle memory-mapped SPI */
299 if (flash->memory_map) {
300 ret = spi_claim_bus(flash->spi);
302 debug("SF: unable to claim SPI bus\n");
305 spi_xfer(flash->spi, 0, NULL, NULL, SPI_XFER_MMAP);
306 memcpy(data, flash->memory_map + offset, len);
307 spi_xfer(flash->spi, 0, NULL, NULL, SPI_XFER_MMAP_END);
308 spi_release_bus(flash->spi);
312 cmd[0] = flash->read_cmd;
316 #ifdef CONFIG_SPI_FLASH_BAR
317 bank_sel = offset / SPI_FLASH_16MB_BOUN;
319 ret = spi_flash_cmd_bankaddr_write(flash, bank_sel);
321 debug("SF: fail to set bank%d\n", bank_sel);
325 remain_len = (SPI_FLASH_16MB_BOUN * (bank_sel + 1)) - offset;
326 if (len < remain_len)
329 read_len = remain_len;
331 spi_flash_addr(offset, cmd);
333 ret = spi_flash_read_common(flash, cmd, sizeof(cmd),
336 debug("SF: read failed\n");
348 #ifdef CONFIG_SPI_FLASH_SST
349 static int sst_byte_write(struct spi_flash *flash, u32 offset, const void *buf)
359 debug("BP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x }\n",
360 spi_w8r8(flash->spi, CMD_READ_STATUS), buf, cmd[0], offset);
362 ret = spi_flash_cmd_write_enable(flash);
366 ret = spi_flash_cmd_write(flash->spi, cmd, sizeof(cmd), buf, 1);
370 return spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT);
373 int sst_write_wp(struct spi_flash *flash, u32 offset, size_t len,
376 size_t actual, cmd_len;
380 ret = spi_claim_bus(flash->spi);
382 debug("SF: Unable to claim SPI bus\n");
386 /* If the data is not word aligned, write out leading single byte */
389 ret = sst_byte_write(flash, offset, buf);
395 ret = spi_flash_cmd_write_enable(flash);
400 cmd[0] = CMD_SST_AAI_WP;
401 cmd[1] = offset >> 16;
402 cmd[2] = offset >> 8;
405 for (; actual < len - 1; actual += 2) {
406 debug("WP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x }\n",
407 spi_w8r8(flash->spi, CMD_READ_STATUS), buf + actual,
410 ret = spi_flash_cmd_write(flash->spi, cmd, cmd_len,
413 debug("SF: sst word program failed\n");
417 ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT);
426 ret = spi_flash_cmd_write_disable(flash);
428 /* If there is a single trailing byte, write it out */
429 if (!ret && actual != len)
430 ret = sst_byte_write(flash, offset, buf + actual);
433 debug("SF: sst: program %s %zu bytes @ 0x%zx\n",
434 ret ? "failure" : "success", len, offset - actual);
436 spi_release_bus(flash->spi);