2 * SPI flash internal definitions
4 * Copyright (C) 2008 Atmel Corporation
5 * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc.
7 * SPDX-License-Identifier: GPL-2.0+
10 #ifndef _SF_INTERNAL_H_
11 #define _SF_INTERNAL_H_
13 #include <linux/types.h>
14 #include <linux/compiler.h>
16 /* Dual SPI flash memories - see SPI_COMM_DUAL_... */
19 SF_DUAL_STACKED_FLASH = 1 << 0,
20 SF_DUAL_PARALLEL_FLASH = 1 << 1,
23 /* Enum list - Full read commands */
27 DUAL_OUTPUT_FAST = 1 << 2,
28 DUAL_IO_FAST = 1 << 3,
29 QUAD_OUTPUT_FAST = 1 << 4,
30 QUAD_IO_FAST = 1 << 5,
33 /* Normal - Extended - Full command set */
34 #define RD_NORM (ARRAY_SLOW | ARRAY_FAST)
35 #define RD_EXTN (RD_NORM | DUAL_OUTPUT_FAST | DUAL_IO_FAST)
36 #define RD_FULL (RD_EXTN | QUAD_OUTPUT_FAST | QUAD_IO_FAST)
48 #define SST_WR (SST_BP | SST_WP)
50 #define SPI_FLASH_3B_ADDR_LEN 3
51 #define SPI_FLASH_CMD_LEN (1 + SPI_FLASH_3B_ADDR_LEN)
52 #define SPI_FLASH_16MB_BOUN 0x1000000
54 /* CFI Manufacture ID's */
55 #define SPI_FLASH_CFI_MFR_SPANSION 0x01
56 #define SPI_FLASH_CFI_MFR_STMICRO 0x20
57 #define SPI_FLASH_CFI_MFR_MACRONIX 0xc2
58 #define SPI_FLASH_CFI_MFR_WINBOND 0xef
61 #define CMD_ERASE_4K 0x20
62 #define CMD_ERASE_32K 0x52
63 #define CMD_ERASE_CHIP 0xc7
64 #define CMD_ERASE_64K 0xd8
67 #define CMD_WRITE_STATUS 0x01
68 #define CMD_PAGE_PROGRAM 0x02
69 #define CMD_WRITE_DISABLE 0x04
70 #define CMD_READ_STATUS 0x05
71 #define CMD_QUAD_PAGE_PROGRAM 0x32
72 #define CMD_READ_STATUS1 0x35
73 #define CMD_WRITE_ENABLE 0x06
74 #define CMD_READ_CONFIG 0x35
75 #define CMD_FLAG_STATUS 0x70
78 #define CMD_READ_ARRAY_SLOW 0x03
79 #define CMD_READ_ARRAY_FAST 0x0b
80 #define CMD_READ_DUAL_OUTPUT_FAST 0x3b
81 #define CMD_READ_DUAL_IO_FAST 0xbb
82 #define CMD_READ_QUAD_OUTPUT_FAST 0x6b
83 #define CMD_READ_QUAD_IO_FAST 0xeb
84 #define CMD_READ_ID 0x9f
86 /* Bank addr access commands */
87 #ifdef CONFIG_SPI_FLASH_BAR
88 # define CMD_BANKADDR_BRWR 0x17
89 # define CMD_BANKADDR_BRRD 0x16
90 # define CMD_EXTNADDR_WREAR 0xC5
91 # define CMD_EXTNADDR_RDEAR 0xC8
95 #define STATUS_WIP (1 << 0)
96 #define STATUS_QEB_WINSPAN (1 << 1)
97 #define STATUS_QEB_MXIC (1 << 6)
98 #define STATUS_PEC (1 << 7)
100 #ifdef CONFIG_SYS_SPI_ST_ENABLE_WP_PIN
101 #define STATUS_SRWD (1 << 7) /* SR write protect */
104 /* Flash timeout values */
105 #define SPI_FLASH_PROG_TIMEOUT (2 * CONFIG_SYS_HZ)
106 #define SPI_FLASH_PAGE_ERASE_TIMEOUT (5 * CONFIG_SYS_HZ)
107 #define SPI_FLASH_SECTOR_ERASE_TIMEOUT (10 * CONFIG_SYS_HZ)
110 #ifdef CONFIG_SPI_FLASH_SST
111 # define CMD_SST_BP 0x02 /* Byte Program */
112 # define CMD_SST_AAI_WP 0xAD /* Auto Address Incr Word Program */
114 int sst_write_wp(struct spi_flash *flash, u32 offset, size_t len,
116 int sst_write_bp(struct spi_flash *flash, u32 offset, size_t len,
121 * struct spi_flash_params - SPI/QSPI flash device params structure
123 * @name: Device name ([MANUFLETTER][DEVTYPE][DENSITY][EXTRAINFO])
124 * @jedec: Device jedec ID (0x[1byte_manuf_id][2byte_dev_id])
125 * @ext_jedec: Device ext_jedec ID
126 * @sector_size: Sector size of this device
127 * @nr_sectors: No.of sectors on this device
128 * @e_rd_cmd: Enum list for read commands
129 * @flags: Important param, for flash specific behaviour
131 struct spi_flash_params {
141 extern const struct spi_flash_params spi_flash_params_table[];
143 /* Send a single-byte command to the device and read the response */
144 int spi_flash_cmd(struct spi_slave *spi, u8 cmd, void *response, size_t len);
147 * Send a multi-byte command to the device and read the response. Used
148 * for flash array reads, etc.
150 int spi_flash_cmd_read(struct spi_slave *spi, const u8 *cmd,
151 size_t cmd_len, void *data, size_t data_len);
154 * Send a multi-byte command to the device followed by (optional)
155 * data. Used for programming the flash array, etc.
157 int spi_flash_cmd_write(struct spi_slave *spi, const u8 *cmd, size_t cmd_len,
158 const void *data, size_t data_len);
161 /* Flash erase(sectors) operation, support all possible erase commands */
162 int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len);
164 /* Read the status register */
165 int spi_flash_cmd_read_status(struct spi_flash *flash, u8 *rs);
167 /* Program the status register */
168 int spi_flash_cmd_write_status(struct spi_flash *flash, u8 ws);
170 /* Read the config register */
171 int spi_flash_cmd_read_config(struct spi_flash *flash, u8 *rc);
173 /* Program the config register */
174 int spi_flash_cmd_write_config(struct spi_flash *flash, u8 wc);
176 /* Enable writing on the SPI flash */
177 static inline int spi_flash_cmd_write_enable(struct spi_flash *flash)
179 return spi_flash_cmd(flash->spi, CMD_WRITE_ENABLE, NULL, 0);
182 /* Disable writing on the SPI flash */
183 static inline int spi_flash_cmd_write_disable(struct spi_flash *flash)
185 return spi_flash_cmd(flash->spi, CMD_WRITE_DISABLE, NULL, 0);
189 * Send the read status command to the device and wait for the wip
190 * (write-in-progress) bit to clear itself.
192 int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout);
195 * Used for spi_flash write operation
197 * - spi_flash_cmd_write_enable
198 * - spi_flash_cmd_write
199 * - spi_flash_cmd_wait_ready
202 int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd,
203 size_t cmd_len, const void *buf, size_t buf_len);
206 * Flash write operation, support all possible write commands.
207 * Write the requested data out breaking it up into multiple write
208 * commands as needed per the write size.
210 int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,
211 size_t len, const void *buf);
214 * Same as spi_flash_cmd_read() except it also claims/releases the SPI
215 * bus. Used as common part of the ->read() operation.
217 int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd,
218 size_t cmd_len, void *data, size_t data_len);
220 /* Flash read operation, support all possible read commands */
221 int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
222 size_t len, void *data);
224 #endif /* _SF_INTERNAL_H_ */