1 // SPDX-License-Identifier: GPL-2.0
3 * Renesas RCar Gen3 RPC Hyperflash driver
5 * Copyright (C) 2016 Renesas Electronics Corporation
6 * Copyright (C) 2016 Cogent Embedded, Inc.
7 * Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com>
15 #include <dm/device_compat.h>
16 #include <dm/of_access.h>
18 #include <fdt_support.h>
22 #include <mtd/cfi_flash.h>
24 #define RPC_CMNCR 0x0000 /* R/W */
25 #define RPC_CMNCR_MD BIT(31)
26 #define RPC_CMNCR_MOIIO0(val) (((val) & 0x3) << 16)
27 #define RPC_CMNCR_MOIIO1(val) (((val) & 0x3) << 18)
28 #define RPC_CMNCR_MOIIO2(val) (((val) & 0x3) << 20)
29 #define RPC_CMNCR_MOIIO3(val) (((val) & 0x3) << 22)
30 #define RPC_CMNCR_MOIIO_HIZ (RPC_CMNCR_MOIIO0(3) | RPC_CMNCR_MOIIO1(3) | \
31 RPC_CMNCR_MOIIO2(3) | RPC_CMNCR_MOIIO3(3))
32 #define RPC_CMNCR_IO0FV(val) (((val) & 0x3) << 8)
33 #define RPC_CMNCR_IO2FV(val) (((val) & 0x3) << 12)
34 #define RPC_CMNCR_IO3FV(val) (((val) & 0x3) << 14)
35 #define RPC_CMNCR_IOFV_HIZ (RPC_CMNCR_IO0FV(3) | RPC_CMNCR_IO2FV(3) | \
37 #define RPC_CMNCR_BSZ(val) (((val) & 0x3) << 0)
39 #define RPC_SSLDR 0x0004 /* R/W */
40 #define RPC_SSLDR_SPNDL(d) (((d) & 0x7) << 16)
41 #define RPC_SSLDR_SLNDL(d) (((d) & 0x7) << 8)
42 #define RPC_SSLDR_SCKDL(d) (((d) & 0x7) << 0)
44 #define RPC_DRCR 0x000C /* R/W */
45 #define RPC_DRCR_SSLN BIT(24)
46 #define RPC_DRCR_RBURST(v) (((v) & 0x1F) << 16)
47 #define RPC_DRCR_RCF BIT(9)
48 #define RPC_DRCR_RBE BIT(8)
49 #define RPC_DRCR_SSLE BIT(0)
51 #define RPC_DRCMR 0x0010 /* R/W */
52 #define RPC_DRCMR_CMD(c) (((c) & 0xFF) << 16)
53 #define RPC_DRCMR_OCMD(c) (((c) & 0xFF) << 0)
55 #define RPC_DREAR 0x0014 /* R/W */
56 #define RPC_DREAR_EAV(v) (((v) & 0xFF) << 16)
57 #define RPC_DREAR_EAC(v) (((v) & 0x7) << 0)
59 #define RPC_DROPR 0x0018 /* R/W */
60 #define RPC_DROPR_OPD3(o) (((o) & 0xFF) << 24)
61 #define RPC_DROPR_OPD2(o) (((o) & 0xFF) << 16)
62 #define RPC_DROPR_OPD1(o) (((o) & 0xFF) << 8)
63 #define RPC_DROPR_OPD0(o) (((o) & 0xFF) << 0)
65 #define RPC_DRENR 0x001C /* R/W */
66 #define RPC_DRENR_CDB(o) (u32)((((o) & 0x3) << 30))
67 #define RPC_DRENR_OCDB(o) (((o) & 0x3) << 28)
68 #define RPC_DRENR_ADB(o) (((o) & 0x3) << 24)
69 #define RPC_DRENR_OPDB(o) (((o) & 0x3) << 20)
70 #define RPC_DRENR_SPIDB(o) (((o) & 0x3) << 16)
71 #define RPC_DRENR_DME BIT(15)
72 #define RPC_DRENR_CDE BIT(14)
73 #define RPC_DRENR_OCDE BIT(12)
74 #define RPC_DRENR_ADE(v) (((v) & 0xF) << 8)
75 #define RPC_DRENR_OPDE(v) (((v) & 0xF) << 4)
77 #define RPC_SMCR 0x0020 /* R/W */
78 #define RPC_SMCR_SSLKP BIT(8)
79 #define RPC_SMCR_SPIRE BIT(2)
80 #define RPC_SMCR_SPIWE BIT(1)
81 #define RPC_SMCR_SPIE BIT(0)
83 #define RPC_SMCMR 0x0024 /* R/W */
84 #define RPC_SMCMR_CMD(c) (((c) & 0xFF) << 16)
85 #define RPC_SMCMR_OCMD(c) (((c) & 0xFF) << 0)
87 #define RPC_SMADR 0x0028 /* R/W */
88 #define RPC_SMOPR 0x002C /* R/W */
89 #define RPC_SMOPR_OPD0(o) (((o) & 0xFF) << 0)
90 #define RPC_SMOPR_OPD1(o) (((o) & 0xFF) << 8)
91 #define RPC_SMOPR_OPD2(o) (((o) & 0xFF) << 16)
92 #define RPC_SMOPR_OPD3(o) (((o) & 0xFF) << 24)
94 #define RPC_SMENR 0x0030 /* R/W */
95 #define RPC_SMENR_CDB(o) (((o) & 0x3) << 30)
96 #define RPC_SMENR_OCDB(o) (((o) & 0x3) << 28)
97 #define RPC_SMENR_ADB(o) (((o) & 0x3) << 24)
98 #define RPC_SMENR_OPDB(o) (((o) & 0x3) << 20)
99 #define RPC_SMENR_SPIDB(o) (((o) & 0x3) << 16)
100 #define RPC_SMENR_DME BIT(15)
101 #define RPC_SMENR_CDE BIT(14)
102 #define RPC_SMENR_OCDE BIT(12)
103 #define RPC_SMENR_ADE(v) (((v) & 0xF) << 8)
104 #define RPC_SMENR_OPDE(v) (((v) & 0xF) << 4)
105 #define RPC_SMENR_SPIDE(v) (((v) & 0xF) << 0)
107 #define RPC_SMRDR0 0x0038 /* R */
108 #define RPC_SMRDR1 0x003C /* R */
109 #define RPC_SMWDR0 0x0040 /* R/W */
110 #define RPC_SMWDR1 0x0044 /* R/W */
111 #define RPC_CMNSR 0x0048 /* R */
112 #define RPC_CMNSR_SSLF BIT(1)
113 #define RPC_CMNSR_TEND BIT(0)
115 #define RPC_DRDMCR 0x0058 /* R/W */
116 #define RPC_DRDMCR_DMCYC(v) (((v) & 0xF) << 0)
118 #define RPC_DRDRENR 0x005C /* R/W */
119 #define RPC_DRDRENR_HYPE (0x5 << 12)
120 #define RPC_DRDRENR_ADDRE BIT(8)
121 #define RPC_DRDRENR_OPDRE BIT(4)
122 #define RPC_DRDRENR_DRDRE BIT(0)
124 #define RPC_SMDMCR 0x0060 /* R/W */
125 #define RPC_SMDMCR_DMCYC(v) (((v) & 0xF) << 0)
127 #define RPC_SMDRENR 0x0064 /* R/W */
128 #define RPC_SMDRENR_HYPE (0x5 << 12)
129 #define RPC_SMDRENR_ADDRE BIT(8)
130 #define RPC_SMDRENR_OPDRE BIT(4)
131 #define RPC_SMDRENR_SPIDRE BIT(0)
133 #define RPC_PHYCNT 0x007C /* R/W */
134 #define RPC_PHYCNT_CAL BIT(31)
135 #define PRC_PHYCNT_OCTA_AA BIT(22)
136 #define PRC_PHYCNT_OCTA_SA BIT(23)
137 #define PRC_PHYCNT_EXDS BIT(21)
138 #define RPC_PHYCNT_OCT BIT(20)
139 #define RPC_PHYCNT_WBUF2 BIT(4)
140 #define RPC_PHYCNT_WBUF BIT(2)
141 #define RPC_PHYCNT_MEM(v) (((v) & 0x3) << 0)
143 #define RPC_PHYINT 0x0088 /* R/W */
144 #define RPC_PHYINT_RSTEN BIT(18)
145 #define RPC_PHYINT_WPEN BIT(17)
146 #define RPC_PHYINT_INTEN BIT(16)
147 #define RPC_PHYINT_RST BIT(2)
148 #define RPC_PHYINT_WP BIT(1)
149 #define RPC_PHYINT_INT BIT(0)
151 #define RPC_WBUF 0x8000 /* R/W size=4/8/16/32/64Bytes */
152 #define RPC_WBUF_SIZE 0x100
154 static phys_addr_t rpc_base;
157 RPC_HF_SIZE_16BIT = RPC_SMENR_SPIDE(0x8),
158 RPC_HF_SIZE_32BIT = RPC_SMENR_SPIDE(0xC),
159 RPC_HF_SIZE_64BIT = RPC_SMENR_SPIDE(0xF),
162 static int rpc_hf_wait_tend(void)
164 void __iomem *reg = (void __iomem *)rpc_base + RPC_CMNSR;
165 return wait_for_bit_le32(reg, RPC_CMNSR_TEND, true, 1000, 0);
168 static int rpc_hf_mode(bool man)
172 ret = rpc_hf_wait_tend();
176 clrsetbits_le32(rpc_base + RPC_PHYCNT,
177 RPC_PHYCNT_WBUF | RPC_PHYCNT_WBUF2 |
178 RPC_PHYCNT_CAL | RPC_PHYCNT_MEM(3),
179 RPC_PHYCNT_CAL | RPC_PHYCNT_MEM(3));
181 clrsetbits_le32(rpc_base + RPC_CMNCR,
182 RPC_CMNCR_MD | RPC_CMNCR_BSZ(3),
183 RPC_CMNCR_MOIIO_HIZ | RPC_CMNCR_IOFV_HIZ |
184 (man ? RPC_CMNCR_MD : 0) | RPC_CMNCR_BSZ(1));
189 writel(RPC_DRCR_RBURST(0x1F) | RPC_DRCR_RCF | RPC_DRCR_RBE,
190 rpc_base + RPC_DRCR);
192 writel(RPC_DRCMR_CMD(0xA0), rpc_base + RPC_DRCMR);
193 writel(RPC_DRENR_CDB(2) | RPC_DRENR_OCDB(2) | RPC_DRENR_ADB(2) |
194 RPC_DRENR_SPIDB(2) | RPC_DRENR_CDE | RPC_DRENR_OCDE |
195 RPC_DRENR_ADE(4), rpc_base + RPC_DRENR);
196 writel(RPC_DRDMCR_DMCYC(0xE), rpc_base + RPC_DRDMCR);
197 writel(RPC_DRDRENR_HYPE | RPC_DRDRENR_ADDRE | RPC_DRDRENR_DRDRE,
198 rpc_base + RPC_DRDRENR);
201 readl(rpc_base + RPC_DRCR);
206 static int rpc_hf_xfer(void *addr, u64 wdata, u64 *rdata,
207 enum rpc_hf_size size, bool write)
212 ret = rpc_hf_mode(1);
216 /* Submit HF address, SMCMR CMD[7] ~= CA Bit# 47 (R/nW) */
217 writel(write ? 0 : RPC_SMCMR_CMD(0x80), rpc_base + RPC_SMCMR);
218 writel((uintptr_t)addr >> 1, rpc_base + RPC_SMADR);
219 writel(0x0, rpc_base + RPC_SMOPR);
221 writel(RPC_SMDRENR_HYPE | RPC_SMDRENR_ADDRE | RPC_SMDRENR_SPIDRE,
222 rpc_base + RPC_SMDRENR);
224 val = RPC_SMENR_CDB(2) | RPC_SMENR_OCDB(2) |
225 RPC_SMENR_ADB(2) | RPC_SMENR_SPIDB(2) |
226 RPC_SMENR_CDE | RPC_SMENR_OCDE | RPC_SMENR_ADE(4) | size;
229 writel(val, rpc_base + RPC_SMENR);
231 if (size == RPC_HF_SIZE_64BIT)
232 writeq(cpu_to_be64(wdata), rpc_base + RPC_SMWDR0);
234 writel(cpu_to_be32(wdata), rpc_base + RPC_SMWDR0);
236 writel(RPC_SMCR_SPIWE | RPC_SMCR_SPIE, rpc_base + RPC_SMCR);
238 val |= RPC_SMENR_DME;
240 writel(RPC_SMDMCR_DMCYC(0xE), rpc_base + RPC_SMDMCR);
242 writel(val, rpc_base + RPC_SMENR);
244 writel(RPC_SMCR_SPIRE | RPC_SMCR_SPIE, rpc_base + RPC_SMCR);
246 ret = rpc_hf_wait_tend();
250 if (size == RPC_HF_SIZE_64BIT)
251 *rdata = be64_to_cpu(readq(rpc_base + RPC_SMRDR0));
253 *rdata = be32_to_cpu(readl(rpc_base + RPC_SMRDR0));
256 return rpc_hf_mode(0);
259 static void rpc_hf_write_cmd(void *addr, u64 wdata, enum rpc_hf_size size)
263 ret = rpc_hf_xfer(addr, wdata, NULL, size, 1);
265 printf("RPC: Write failed, ret=%i\n", ret);
268 static u64 rpc_hf_read_reg(void *addr, enum rpc_hf_size size)
273 ret = rpc_hf_xfer(addr, 0, &rdata, size, 0);
275 printf("RPC: Read failed, ret=%i\n", ret);
280 void flash_write8(u8 value, void *addr)
282 rpc_hf_write_cmd(addr, value, RPC_HF_SIZE_16BIT);
285 void flash_write16(u16 value, void *addr)
287 rpc_hf_write_cmd(addr, value, RPC_HF_SIZE_16BIT);
290 void flash_write32(u32 value, void *addr)
292 rpc_hf_write_cmd(addr, value, RPC_HF_SIZE_32BIT);
295 void flash_write64(u64 value, void *addr)
297 rpc_hf_write_cmd(addr, value, RPC_HF_SIZE_64BIT);
300 u8 flash_read8(void *addr)
302 return rpc_hf_read_reg(addr, RPC_HF_SIZE_16BIT);
305 u16 flash_read16(void *addr)
307 return rpc_hf_read_reg(addr, RPC_HF_SIZE_16BIT);
310 u32 flash_read32(void *addr)
312 return rpc_hf_read_reg(addr, RPC_HF_SIZE_32BIT);
315 u64 flash_read64(void *addr)
317 return rpc_hf_read_reg(addr, RPC_HF_SIZE_64BIT);
320 static int rpc_hf_bind(struct udevice *parent)
322 const void *fdt = gd->fdt_blob;
327 * Check if there are any SPI NOR child nodes, if so, do NOT bind
328 * as this controller will be operated by the QSPI driver instead.
330 dev_for_each_subnode(node, parent) {
331 off = ofnode_to_offset(node);
333 ret = fdt_node_check_compatible(fdt, off, "spi-flash");
337 ret = fdt_node_check_compatible(fdt, off, "jedec,spi-nor");
345 static int rpc_hf_probe(struct udevice *dev)
347 void *blob = (void *)gd->fdt_blob;
349 int node = dev_of_offset(dev);
350 int parent, addrc, sizec, len, ret;
352 phys_addr_t flash_base;
354 parent = fdt_parent_offset(blob, node);
355 fdt_support_default_count_cells(blob, parent, &addrc, &sizec);
356 cell = fdt_getprop(blob, node, "reg", &len);
360 if (addrc != 2 || sizec != 2)
364 ret = clk_get_by_index(dev, 0, &clk);
366 dev_err(dev, "Failed to get RPC clock\n");
370 ret = clk_enable(&clk);
373 dev_err(dev, "Failed to enable RPC clock\n");
377 rpc_base = fdt_translate_address(blob, node, cell);
378 flash_base = fdt_translate_address(blob, node, cell + addrc + sizec);
380 flash_info[0].dev = dev;
381 flash_info[0].base = flash_base;
382 cfi_flash_num_flash_banks = 1;
383 gd->bd->bi_flashstart = flash_base;
388 static const struct udevice_id rpc_hf_ids[] = {
389 { .compatible = "renesas,rpc" },
393 U_BOOT_DRIVER(rpc_hf) = {
396 .of_match = rpc_hf_ids,
398 .probe = rpc_hf_probe,