1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2016 Xilinx, Inc.
5 * Xilinx Zynq NAND Flash Controller Driver
6 * This driver is based on plat_nand.c and mxc_nand.c drivers
12 #include <linux/errno.h>
14 #include <linux/mtd/mtd.h>
15 #include <linux/mtd/rawnand.h>
16 #include <linux/mtd/partitions.h>
17 #include <linux/mtd/nand_ecc.h>
18 #include <asm/arch/hardware.h>
20 /* The NAND flash driver defines */
21 #define ZYNQ_NAND_CMD_PHASE 1
22 #define ZYNQ_NAND_DATA_PHASE 2
23 #define ZYNQ_NAND_ECC_SIZE 512
24 #define ZYNQ_NAND_SET_OPMODE_8BIT (0 << 0)
25 #define ZYNQ_NAND_SET_OPMODE_16BIT (1 << 0)
26 #define ZYNQ_NAND_ECC_STATUS (1 << 6)
27 #define ZYNQ_MEMC_CLRCR_INT_CLR1 (1 << 4)
28 #define ZYNQ_MEMC_SR_RAW_INT_ST1 (1 << 6)
29 #define ZYNQ_MEMC_SR_INT_ST1 (1 << 4)
30 #define ZYNQ_MEMC_NAND_ECC_MODE_MASK 0xC
32 /* Flash memory controller operating parameters */
33 #define ZYNQ_NAND_CLR_CONFIG ((0x1 << 1) | /* Disable interrupt */ \
34 (0x1 << 4) | /* Clear interrupt */ \
35 (0x1 << 6)) /* Disable ECC interrupt */
37 #ifndef CONFIG_NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS
39 /* Assuming 50MHz clock (20ns cycle time) and 3V operation */
40 #define ZYNQ_NAND_SET_CYCLES ((0x2 << 20) | /* t_rr from nand_cycles */ \
41 (0x2 << 17) | /* t_ar from nand_cycles */ \
42 (0x1 << 14) | /* t_clr from nand_cycles */ \
43 (0x3 << 11) | /* t_wp from nand_cycles */ \
44 (0x2 << 8) | /* t_rea from nand_cycles */ \
45 (0x5 << 4) | /* t_wc from nand_cycles */ \
46 (0x5 << 0)) /* t_rc from nand_cycles */
50 #define ZYNQ_NAND_DIRECT_CMD ((0x4 << 23) | /* Chip 0 from interface 1 */ \
51 (0x2 << 21)) /* UpdateRegs operation */
53 #define ZYNQ_NAND_ECC_CONFIG ((0x1 << 2) | /* ECC available on APB */ \
54 (0x1 << 4) | /* ECC read at end of page */ \
55 (0x0 << 5)) /* No Jumping */
57 #define ZYNQ_NAND_ECC_CMD1 ((0x80) | /* Write command */ \
58 (0x00 << 8) | /* Read command */ \
59 (0x30 << 16) | /* Read End command */ \
60 (0x1 << 24)) /* Read End command calid */
62 #define ZYNQ_NAND_ECC_CMD2 ((0x85) | /* Write col change cmd */ \
63 (0x05 << 8) | /* Read col change cmd */ \
64 (0xE0 << 16) | /* Read col change end cmd */ \
65 (0x1 << 24)) /* Read col change
67 /* AXI Address definitions */
68 #define START_CMD_SHIFT 3
69 #define END_CMD_SHIFT 11
70 #define END_CMD_VALID_SHIFT 20
71 #define ADDR_CYCLES_SHIFT 21
72 #define CLEAR_CS_SHIFT 21
73 #define ECC_LAST_SHIFT 10
74 #define COMMAND_PHASE (0 << 19)
75 #define DATA_PHASE (1 << 19)
76 #define ONDIE_ECC_FEATURE_ADDR 0x90
77 #define ONDIE_ECC_FEATURE_ENABLE 0x08
79 #define ZYNQ_NAND_ECC_LAST (1 << ECC_LAST_SHIFT) /* Set ECC_Last */
80 #define ZYNQ_NAND_CLEAR_CS (1 << CLEAR_CS_SHIFT) /* Clear chip select */
82 /* ECC block registers bit position and bit mask */
83 #define ZYNQ_NAND_ECC_BUSY (1 << 6) /* ECC block is busy */
84 #define ZYNQ_NAND_ECC_MASK 0x00FFFFFF /* ECC value mask */
86 #ifndef NAND_CMD_LOCK_TIGHT
87 #define NAND_CMD_LOCK_TIGHT 0x2c
90 #ifndef NAND_CMD_LOCK_STATUS
91 #define NAND_CMD_LOCK_STATUS 0x7a
94 /* SMC register set */
95 struct zynq_nand_smc_regs {
104 u32 emcr; /* 0x404 */
105 u32 emcmd1r; /* 0x408 */
106 u32 emcmd2r; /* 0x40C */
108 u32 eval0r; /* 0x418 */
110 #define zynq_nand_smc_base ((struct zynq_nand_smc_regs __iomem *)\
114 * struct zynq_nand_info - Defines the NAND flash driver instance
115 * @parts: Pointer to the mtd_partition structure
116 * @nand_base: Virtual address of the NAND flash device
117 * @end_cmd_pending: End command is pending
118 * @end_cmd: End command
120 struct zynq_nand_info {
121 void __iomem *nand_base;
127 * struct zynq_nand_command_format - Defines NAND flash command format
128 * @start_cmd: First cycle command (Start command)
129 * @end_cmd: Second cycle command (Last command)
130 * @addr_cycles: Number of address cycles required to send the address
131 * @end_cmd_valid: The second cycle command is valid for cmd or data phase
133 struct zynq_nand_command_format {
140 /* The NAND flash operations command format */
141 static const struct zynq_nand_command_format zynq_nand_commands[] = {
142 {NAND_CMD_READ0, NAND_CMD_READSTART, 5, ZYNQ_NAND_CMD_PHASE},
143 {NAND_CMD_RNDOUT, NAND_CMD_RNDOUTSTART, 2, ZYNQ_NAND_CMD_PHASE},
144 {NAND_CMD_READID, NAND_CMD_NONE, 1, 0},
145 {NAND_CMD_STATUS, NAND_CMD_NONE, 0, 0},
146 {NAND_CMD_SEQIN, NAND_CMD_PAGEPROG, 5, ZYNQ_NAND_DATA_PHASE},
147 {NAND_CMD_RNDIN, NAND_CMD_NONE, 2, 0},
148 {NAND_CMD_ERASE1, NAND_CMD_ERASE2, 3, ZYNQ_NAND_CMD_PHASE},
149 {NAND_CMD_RESET, NAND_CMD_NONE, 0, 0},
150 {NAND_CMD_PARAM, NAND_CMD_NONE, 1, 0},
151 {NAND_CMD_GET_FEATURES, NAND_CMD_NONE, 1, 0},
152 {NAND_CMD_SET_FEATURES, NAND_CMD_NONE, 1, 0},
153 {NAND_CMD_LOCK, NAND_CMD_NONE, 0, 0},
154 {NAND_CMD_LOCK_TIGHT, NAND_CMD_NONE, 0, 0},
155 {NAND_CMD_UNLOCK1, NAND_CMD_NONE, 3, 0},
156 {NAND_CMD_UNLOCK2, NAND_CMD_NONE, 3, 0},
157 {NAND_CMD_LOCK_STATUS, NAND_CMD_NONE, 3, 0},
158 {NAND_CMD_NONE, NAND_CMD_NONE, 0, 0},
159 /* Add all the flash commands supported by the flash device */
162 /* Define default oob placement schemes for large and small page devices */
163 static struct nand_ecclayout nand_oob_16 = {
167 { .offset = 8, .length = 8 }
171 static struct nand_ecclayout nand_oob_64 = {
174 52, 53, 54, 55, 56, 57,
175 58, 59, 60, 61, 62, 63},
177 { .offset = 2, .length = 50 }
181 static struct nand_ecclayout ondie_nand_oob_64 = {
185 8, 9, 10, 11, 12, 13, 14, 15,
186 24, 25, 26, 27, 28, 29, 30, 31,
187 40, 41, 42, 43, 44, 45, 46, 47,
188 56, 57, 58, 59, 60, 61, 62, 63
192 { .offset = 4, .length = 4 },
193 { .offset = 20, .length = 4 },
194 { .offset = 36, .length = 4 },
195 { .offset = 52, .length = 4 }
199 /* bbt decriptors for chips with on-die ECC and
200 chips with 64-byte OOB */
201 static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
202 static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
204 static struct nand_bbt_descr bbt_main_descr = {
205 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
206 NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
211 .pattern = bbt_pattern
214 static struct nand_bbt_descr bbt_mirror_descr = {
215 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
216 NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
221 .pattern = mirror_pattern
225 * zynq_nand_waitfor_ecc_completion - Wait for ECC completion
227 * returns: status for command completion, -1 for Timeout
229 static int zynq_nand_waitfor_ecc_completion(void)
231 unsigned long timeout;
236 status = readl(&zynq_nand_smc_base->esr);
237 while (status & ZYNQ_NAND_ECC_BUSY) {
238 status = readl(&zynq_nand_smc_base->esr);
249 * zynq_nand_init_nand_flash - Initialize NAND controller
250 * @option: Device property flags
252 * This function initializes the NAND flash interface on the NAND controller.
254 * returns: 0 on success or error value on failure
256 static int zynq_nand_init_nand_flash(int option)
260 /* disable interrupts */
261 writel(ZYNQ_NAND_CLR_CONFIG, &zynq_nand_smc_base->cfr);
262 #ifndef CONFIG_NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS
263 /* Initialize the NAND interface by setting cycles and operation mode */
264 writel(ZYNQ_NAND_SET_CYCLES, &zynq_nand_smc_base->scr);
266 if (option & NAND_BUSWIDTH_16)
267 writel(ZYNQ_NAND_SET_OPMODE_16BIT, &zynq_nand_smc_base->sor);
269 writel(ZYNQ_NAND_SET_OPMODE_8BIT, &zynq_nand_smc_base->sor);
271 writel(ZYNQ_NAND_DIRECT_CMD, &zynq_nand_smc_base->dcr);
273 /* Wait till the ECC operation is complete */
274 status = zynq_nand_waitfor_ecc_completion();
276 printf("%s: Timeout\n", __func__);
280 /* Set the command1 and command2 register */
281 writel(ZYNQ_NAND_ECC_CMD1, &zynq_nand_smc_base->emcmd1r);
282 writel(ZYNQ_NAND_ECC_CMD2, &zynq_nand_smc_base->emcmd2r);
288 * zynq_nand_calculate_hwecc - Calculate Hardware ECC
289 * @mtd: Pointer to the mtd_info structure
290 * @data: Pointer to the page data
291 * @ecc_code: Pointer to the ECC buffer where ECC data needs to be stored
293 * This function retrieves the Hardware ECC data from the controller and returns
294 * ECC data back to the MTD subsystem.
296 * returns: 0 on success or error value on failure
298 static int zynq_nand_calculate_hwecc(struct mtd_info *mtd, const u8 *data,
302 u8 ecc_reg, ecc_byte;
305 /* Wait till the ECC operation is complete */
306 ecc_status = zynq_nand_waitfor_ecc_completion();
307 if (ecc_status < 0) {
308 printf("%s: Timeout\n", __func__);
312 for (ecc_reg = 0; ecc_reg < 4; ecc_reg++) {
313 /* Read ECC value for each block */
314 ecc_value = readl(&zynq_nand_smc_base->eval0r + ecc_reg);
316 /* Get the ecc status from ecc read value */
317 ecc_status = (ecc_value >> 24) & 0xFF;
319 /* ECC value valid */
320 if (ecc_status & ZYNQ_NAND_ECC_STATUS) {
321 for (ecc_byte = 0; ecc_byte < 3; ecc_byte++) {
322 /* Copy ECC bytes to MTD buffer */
323 *ecc_code = ecc_value & 0xFF;
324 ecc_value = ecc_value >> 8;
328 debug("%s: ecc status failed\n", __func__);
336 * onehot - onehot function
337 * @value: value to check for onehot
339 * This function checks whether a value is onehot or not.
340 * onehot is if and only if one bit is set.
342 * FIXME: Try to move this in common.h
344 static bool onehot(unsigned short value)
348 onehot = value && !(value & (value - 1));
353 * zynq_nand_correct_data - ECC correction function
354 * @mtd: Pointer to the mtd_info structure
355 * @buf: Pointer to the page data
356 * @read_ecc: Pointer to the ECC value read from spare data area
357 * @calc_ecc: Pointer to the calculated ECC value
359 * This function corrects the ECC single bit errors & detects 2-bit errors.
361 * returns: 0 if no ECC errors found
362 * 1 if single bit error found and corrected.
363 * -1 if multiple ECC errors found.
365 static int zynq_nand_correct_data(struct mtd_info *mtd, unsigned char *buf,
366 unsigned char *read_ecc, unsigned char *calc_ecc)
368 unsigned char bit_addr;
369 unsigned int byte_addr;
370 unsigned short ecc_odd, ecc_even;
371 unsigned short read_ecc_lower, read_ecc_upper;
372 unsigned short calc_ecc_lower, calc_ecc_upper;
374 read_ecc_lower = (read_ecc[0] | (read_ecc[1] << 8)) & 0xfff;
375 read_ecc_upper = ((read_ecc[1] >> 4) | (read_ecc[2] << 4)) & 0xfff;
377 calc_ecc_lower = (calc_ecc[0] | (calc_ecc[1] << 8)) & 0xfff;
378 calc_ecc_upper = ((calc_ecc[1] >> 4) | (calc_ecc[2] << 4)) & 0xfff;
380 ecc_odd = read_ecc_lower ^ calc_ecc_lower;
381 ecc_even = read_ecc_upper ^ calc_ecc_upper;
383 if ((ecc_odd == 0) && (ecc_even == 0))
384 return 0; /* no error */
386 if (ecc_odd == (~ecc_even & 0xfff)) {
387 /* bits [11:3] of error code is byte offset */
388 byte_addr = (ecc_odd >> 3) & 0x1ff;
389 /* bits [2:0] of error code is bit offset */
390 bit_addr = ecc_odd & 0x7;
391 /* Toggling error bit */
392 buf[byte_addr] ^= (1 << bit_addr);
396 if (onehot(ecc_odd | ecc_even))
397 return 1; /* one error in parity */
399 return -1; /* Uncorrectable error */
403 * zynq_nand_read_oob - [REPLACABLE] the most common OOB data read function
404 * @mtd: mtd info structure
405 * @chip: nand chip info structure
406 * @page: page number to read
407 * @sndcmd: flag whether to issue read command or not
409 static int zynq_nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
412 unsigned long data_phase_addr = 0;
416 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
419 chip->read_buf(mtd, p, (mtd->oobsize - data_width));
420 p += mtd->oobsize - data_width;
422 data_phase_addr = (unsigned long)chip->IO_ADDR_R;
423 data_phase_addr |= ZYNQ_NAND_CLEAR_CS;
424 chip->IO_ADDR_R = (void __iomem *)data_phase_addr;
425 chip->read_buf(mtd, p, data_width);
431 * zynq_nand_write_oob - [REPLACABLE] the most common OOB data write function
432 * @mtd: mtd info structure
433 * @chip: nand chip info structure
434 * @page: page number to write
436 static int zynq_nand_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
439 int status = 0, data_width = 4;
440 const u8 *buf = chip->oob_poi;
441 unsigned long data_phase_addr = 0;
443 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
445 chip->write_buf(mtd, buf, (mtd->oobsize - data_width));
446 buf += mtd->oobsize - data_width;
448 data_phase_addr = (unsigned long)chip->IO_ADDR_W;
449 data_phase_addr |= ZYNQ_NAND_CLEAR_CS;
450 data_phase_addr |= (1 << END_CMD_VALID_SHIFT);
451 chip->IO_ADDR_W = (void __iomem *)data_phase_addr;
452 chip->write_buf(mtd, buf, data_width);
454 /* Send command to program the OOB data */
455 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
456 status = chip->waitfunc(mtd, chip);
458 return status & NAND_STATUS_FAIL ? -EIO : 0;
462 * zynq_nand_read_page_raw - [Intern] read raw page data without ecc
463 * @mtd: mtd info structure
464 * @chip: nand chip info structure
465 * @buf: buffer to store read data
466 * @oob_required: must write chip->oob_poi to OOB
467 * @page: page number to read
469 static int zynq_nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
470 u8 *buf, int oob_required, int page)
472 unsigned long data_width = 4;
473 unsigned long data_phase_addr = 0;
476 chip->read_buf(mtd, buf, mtd->writesize);
479 chip->read_buf(mtd, p, (mtd->oobsize - data_width));
480 p += (mtd->oobsize - data_width);
482 data_phase_addr = (unsigned long)chip->IO_ADDR_R;
483 data_phase_addr |= ZYNQ_NAND_CLEAR_CS;
484 chip->IO_ADDR_R = (void __iomem *)data_phase_addr;
486 chip->read_buf(mtd, p, data_width);
490 static int zynq_nand_read_page_raw_nooob(struct mtd_info *mtd,
491 struct nand_chip *chip, u8 *buf, int oob_required, int page)
493 chip->read_buf(mtd, buf, mtd->writesize);
497 static int zynq_nand_read_subpage_raw(struct mtd_info *mtd,
498 struct nand_chip *chip, u32 data_offs,
499 u32 readlen, u8 *buf, int page)
501 if (data_offs != 0) {
502 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_offs, -1);
505 chip->read_buf(mtd, buf, readlen);
511 * zynq_nand_write_page_raw - [Intern] raw page write function
512 * @mtd: mtd info structure
513 * @chip: nand chip info structure
515 * @oob_required: must write chip->oob_poi to OOB
517 static int zynq_nand_write_page_raw(struct mtd_info *mtd,
518 struct nand_chip *chip, const u8 *buf, int oob_required, int page)
520 unsigned long data_width = 4;
521 unsigned long data_phase_addr = 0;
524 chip->write_buf(mtd, buf, mtd->writesize);
527 chip->write_buf(mtd, p, (mtd->oobsize - data_width));
528 p += (mtd->oobsize - data_width);
530 data_phase_addr = (unsigned long)chip->IO_ADDR_W;
531 data_phase_addr |= ZYNQ_NAND_CLEAR_CS;
532 data_phase_addr |= (1 << END_CMD_VALID_SHIFT);
533 chip->IO_ADDR_W = (void __iomem *)data_phase_addr;
535 chip->write_buf(mtd, p, data_width);
541 * nand_write_page_hwecc - Hardware ECC based page write function
542 * @mtd: Pointer to the mtd info structure
543 * @chip: Pointer to the NAND chip info structure
544 * @buf: Pointer to the data buffer
545 * @oob_required: must write chip->oob_poi to OOB
547 * This functions writes data and hardware generated ECC values in to the page.
549 static int zynq_nand_write_page_hwecc(struct mtd_info *mtd,
550 struct nand_chip *chip, const u8 *buf, int oob_required, int page)
552 int i, eccsteps, eccsize = chip->ecc.size;
553 u8 *ecc_calc = chip->buffers->ecccalc;
555 u32 *eccpos = chip->ecc.layout->eccpos;
556 unsigned long data_phase_addr = 0;
557 unsigned long data_width = 4;
560 for (eccsteps = chip->ecc.steps; (eccsteps - 1); eccsteps--) {
561 chip->write_buf(mtd, p, eccsize);
564 chip->write_buf(mtd, p, (eccsize - data_width));
565 p += eccsize - data_width;
567 /* Set ECC Last bit to 1 */
568 data_phase_addr = (unsigned long) chip->IO_ADDR_W;
569 data_phase_addr |= ZYNQ_NAND_ECC_LAST;
570 chip->IO_ADDR_W = (void __iomem *)data_phase_addr;
571 chip->write_buf(mtd, p, data_width);
573 /* Wait for ECC to be calculated and read the error values */
575 chip->ecc.calculate(mtd, p, &ecc_calc[0]);
577 for (i = 0; i < chip->ecc.total; i++)
578 chip->oob_poi[eccpos[i]] = ~(ecc_calc[i]);
580 /* Clear ECC last bit */
581 data_phase_addr = (unsigned long)chip->IO_ADDR_W;
582 data_phase_addr &= ~ZYNQ_NAND_ECC_LAST;
583 chip->IO_ADDR_W = (void __iomem *)data_phase_addr;
585 /* Write the spare area with ECC bytes */
586 oob_ptr = chip->oob_poi;
587 chip->write_buf(mtd, oob_ptr, (mtd->oobsize - data_width));
589 data_phase_addr = (unsigned long)chip->IO_ADDR_W;
590 data_phase_addr |= ZYNQ_NAND_CLEAR_CS;
591 data_phase_addr |= (1 << END_CMD_VALID_SHIFT);
592 chip->IO_ADDR_W = (void __iomem *)data_phase_addr;
593 oob_ptr += (mtd->oobsize - data_width);
594 chip->write_buf(mtd, oob_ptr, data_width);
600 * zynq_nand_write_page_swecc - [REPLACABLE] software ecc based page
602 * @mtd: mtd info structure
603 * @chip: nand chip info structure
605 * @oob_required: must write chip->oob_poi to OOB
607 static int zynq_nand_write_page_swecc(struct mtd_info *mtd,
608 struct nand_chip *chip, const u8 *buf, int oob_required, int page)
610 int i, eccsize = chip->ecc.size;
611 int eccbytes = chip->ecc.bytes;
612 int eccsteps = chip->ecc.steps;
613 u8 *ecc_calc = chip->buffers->ecccalc;
615 u32 *eccpos = chip->ecc.layout->eccpos;
617 /* Software ecc calculation */
618 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
619 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
621 for (i = 0; i < chip->ecc.total; i++)
622 chip->oob_poi[eccpos[i]] = ecc_calc[i];
624 return chip->ecc.write_page_raw(mtd, chip, buf, 1, page);
628 * nand_read_page_hwecc - Hardware ECC based page read function
629 * @mtd: Pointer to the mtd info structure
630 * @chip: Pointer to the NAND chip info structure
631 * @buf: Pointer to the buffer to store read data
632 * @oob_required: must write chip->oob_poi to OOB
633 * @page: page number to read
635 * This functions reads data and checks the data integrity by comparing hardware
636 * generated ECC values and read ECC values from spare area.
638 * returns: 0 always and updates ECC operation status in to MTD structure
640 static int zynq_nand_read_page_hwecc(struct mtd_info *mtd,
641 struct nand_chip *chip, u8 *buf, int oob_required, int page)
643 int i, stat, eccsteps, eccsize = chip->ecc.size;
644 int eccbytes = chip->ecc.bytes;
646 u8 *ecc_calc = chip->buffers->ecccalc;
647 u8 *ecc_code = chip->buffers->ecccode;
648 u32 *eccpos = chip->ecc.layout->eccpos;
649 unsigned long data_phase_addr = 0;
650 unsigned long data_width = 4;
653 for (eccsteps = chip->ecc.steps; (eccsteps - 1); eccsteps--) {
654 chip->read_buf(mtd, p, eccsize);
657 chip->read_buf(mtd, p, (eccsize - data_width));
658 p += eccsize - data_width;
660 /* Set ECC Last bit to 1 */
661 data_phase_addr = (unsigned long)chip->IO_ADDR_R;
662 data_phase_addr |= ZYNQ_NAND_ECC_LAST;
663 chip->IO_ADDR_R = (void __iomem *)data_phase_addr;
664 chip->read_buf(mtd, p, data_width);
666 /* Read the calculated ECC value */
668 chip->ecc.calculate(mtd, p, &ecc_calc[0]);
670 /* Clear ECC last bit */
671 data_phase_addr = (unsigned long)chip->IO_ADDR_R;
672 data_phase_addr &= ~ZYNQ_NAND_ECC_LAST;
673 chip->IO_ADDR_R = (void __iomem *)data_phase_addr;
675 /* Read the stored ECC value */
676 oob_ptr = chip->oob_poi;
677 chip->read_buf(mtd, oob_ptr, (mtd->oobsize - data_width));
679 /* de-assert chip select */
680 data_phase_addr = (unsigned long)chip->IO_ADDR_R;
681 data_phase_addr |= ZYNQ_NAND_CLEAR_CS;
682 chip->IO_ADDR_R = (void __iomem *)data_phase_addr;
684 oob_ptr += (mtd->oobsize - data_width);
685 chip->read_buf(mtd, oob_ptr, data_width);
687 for (i = 0; i < chip->ecc.total; i++)
688 ecc_code[i] = ~(chip->oob_poi[eccpos[i]]);
690 eccsteps = chip->ecc.steps;
693 /* Check ECC error for all blocks and correct if it is correctable */
694 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
695 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
697 mtd->ecc_stats.failed++;
699 mtd->ecc_stats.corrected += stat;
705 * zynq_nand_read_page_swecc - [REPLACABLE] software ecc based page
707 * @mtd: mtd info structure
708 * @chip: nand chip info structure
709 * @buf: buffer to store read data
710 * @page: page number to read
712 static int zynq_nand_read_page_swecc(struct mtd_info *mtd,
713 struct nand_chip *chip, u8 *buf, int oob_required, int page)
715 int i, eccsize = chip->ecc.size;
716 int eccbytes = chip->ecc.bytes;
717 int eccsteps = chip->ecc.steps;
719 u8 *ecc_calc = chip->buffers->ecccalc;
720 u8 *ecc_code = chip->buffers->ecccode;
721 u32 *eccpos = chip->ecc.layout->eccpos;
723 chip->ecc.read_page_raw(mtd, chip, buf, 1, page);
725 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
726 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
728 for (i = 0; i < chip->ecc.total; i++)
729 ecc_code[i] = chip->oob_poi[eccpos[i]];
731 eccsteps = chip->ecc.steps;
734 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
737 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
739 mtd->ecc_stats.failed++;
741 mtd->ecc_stats.corrected += stat;
747 * zynq_nand_select_chip - Select the flash device
748 * @mtd: Pointer to the mtd_info structure
749 * @chip: Chip number to be selected
751 * This function is empty as the NAND controller handles chip select line
752 * internally based on the chip address passed in command and data phase.
754 static void zynq_nand_select_chip(struct mtd_info *mtd, int chip)
756 /* Not support multiple chips yet */
760 * zynq_nand_cmd_function - Send command to NAND device
761 * @mtd: Pointer to the mtd_info structure
762 * @command: The command to be sent to the flash device
763 * @column: The column address for this command, -1 if none
764 * @page_addr: The page address for this command, -1 if none
766 static void zynq_nand_cmd_function(struct mtd_info *mtd, unsigned int command,
767 int column, int page_addr)
769 struct nand_chip *chip = mtd->priv;
770 const struct zynq_nand_command_format *curr_cmd = NULL;
771 struct zynq_nand_info *xnand = (struct zynq_nand_info *)chip->priv;
773 unsigned long cmd_data = 0;
774 unsigned long cmd_phase_addr = 0;
775 unsigned long data_phase_addr = 0;
777 u8 end_cmd_valid = 0;
780 if (xnand->end_cmd_pending) {
781 /* Check for end command if this command request is same as the
782 * pending command then return
784 if (xnand->end_cmd == command) {
786 xnand->end_cmd_pending = 0;
791 /* Emulate NAND_CMD_READOOB for large page device */
792 if ((mtd->writesize > ZYNQ_NAND_ECC_SIZE) &&
793 (command == NAND_CMD_READOOB)) {
794 column += mtd->writesize;
795 command = NAND_CMD_READ0;
798 /* Get the command format */
799 for (index = 0; index < ARRAY_SIZE(zynq_nand_commands); index++)
800 if (command == zynq_nand_commands[index].start_cmd)
803 if (index == ARRAY_SIZE(zynq_nand_commands)) {
804 printf("%s: Unsupported start cmd %02x\n", __func__, command);
807 curr_cmd = &zynq_nand_commands[index];
809 /* Clear interrupt */
810 writel(ZYNQ_MEMC_CLRCR_INT_CLR1, &zynq_nand_smc_base->cfr);
812 /* Get the command phase address */
813 if (curr_cmd->end_cmd_valid == ZYNQ_NAND_CMD_PHASE)
816 if (curr_cmd->end_cmd == NAND_CMD_NONE)
819 end_cmd = curr_cmd->end_cmd;
821 cmd_phase_addr = (unsigned long)xnand->nand_base |
822 (curr_cmd->addr_cycles << ADDR_CYCLES_SHIFT) |
823 (end_cmd_valid << END_CMD_VALID_SHIFT) |
825 (end_cmd << END_CMD_SHIFT) |
826 (curr_cmd->start_cmd << START_CMD_SHIFT);
828 cmd_addr = (void __iomem *)cmd_phase_addr;
830 /* Get the data phase address */
833 data_phase_addr = (unsigned long)xnand->nand_base |
834 (0x0 << CLEAR_CS_SHIFT) |
835 (end_cmd_valid << END_CMD_VALID_SHIFT) |
837 (end_cmd << END_CMD_SHIFT) |
838 (0x0 << ECC_LAST_SHIFT);
840 chip->IO_ADDR_R = (void __iomem *)data_phase_addr;
841 chip->IO_ADDR_W = chip->IO_ADDR_R;
843 /* Command phase AXI Read & Write */
844 if (column != -1 && page_addr != -1) {
845 /* Adjust columns for 16 bit bus width */
846 if (chip->options & NAND_BUSWIDTH_16)
849 if (mtd->writesize > ZYNQ_NAND_ECC_SIZE) {
850 cmd_data |= page_addr << 16;
851 /* Another address cycle for devices > 128MiB */
852 if (chip->chipsize > (128 << 20)) {
853 writel(cmd_data, cmd_addr);
854 cmd_data = (page_addr >> 16);
857 cmd_data |= page_addr << 8;
859 } else if (page_addr != -1) { /* Erase */
860 cmd_data = page_addr;
861 } else if (column != -1) { /* Change read/write column, read id etc */
862 /* Adjust columns for 16 bit bus width */
863 if ((chip->options & NAND_BUSWIDTH_16) &&
864 ((command == NAND_CMD_READ0) ||
865 (command == NAND_CMD_SEQIN) ||
866 (command == NAND_CMD_RNDOUT) ||
867 (command == NAND_CMD_RNDIN)))
872 writel(cmd_data, cmd_addr);
874 if (curr_cmd->end_cmd_valid) {
875 xnand->end_cmd = curr_cmd->end_cmd;
876 xnand->end_cmd_pending = 1;
881 if ((command == NAND_CMD_READ0) ||
882 (command == NAND_CMD_RESET) ||
883 (command == NAND_CMD_PARAM) ||
884 (command == NAND_CMD_GET_FEATURES))
885 /* wait until command is processed */
886 nand_wait_ready(mtd);
890 * zynq_nand_read_buf - read chip data into buffer
891 * @mtd: MTD device structure
892 * @buf: buffer to store date
893 * @len: number of bytes to read
895 static void zynq_nand_read_buf(struct mtd_info *mtd, u8 *buf, int len)
897 struct nand_chip *chip = mtd->priv;
899 /* Make sure that buf is 32 bit aligned */
900 if (((unsigned long)buf & 0x3) != 0) {
901 if (((unsigned long)buf & 0x1) != 0) {
903 *buf = readb(chip->IO_ADDR_R);
909 if (((unsigned long)buf & 0x3) != 0) {
911 *(u16 *)buf = readw(chip->IO_ADDR_R);
918 /* copy aligned data */
920 *(u32 *)buf = readl(chip->IO_ADDR_R);
925 /* mop up any remaining bytes */
928 *(u16 *)buf = readw(chip->IO_ADDR_R);
933 *buf = readb(chip->IO_ADDR_R);
938 * zynq_nand_write_buf - write buffer to chip
939 * @mtd: MTD device structure
941 * @len: number of bytes to write
943 static void zynq_nand_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
945 struct nand_chip *chip = mtd->priv;
946 const u32 *nand = chip->IO_ADDR_W;
948 /* Make sure that buf is 32 bit aligned */
949 if (((unsigned long)buf & 0x3) != 0) {
950 if (((unsigned long)buf & 0x1) != 0) {
958 if (((unsigned long)buf & 0x3) != 0) {
960 writew(*(u16 *)buf, nand);
967 /* copy aligned data */
969 writel(*(u32 *)buf, nand);
974 /* mop up any remaining bytes */
977 writew(*(u16 *)buf, nand);
988 * zynq_nand_device_ready - Check device ready/busy line
989 * @mtd: Pointer to the mtd_info structure
991 * returns: 0 on busy or 1 on ready state
993 static int zynq_nand_device_ready(struct mtd_info *mtd)
997 csr_val = readl(&zynq_nand_smc_base->csr);
998 /* Check the raw_int_status1 bit */
999 if (csr_val & ZYNQ_MEMC_SR_RAW_INT_ST1) {
1000 /* Clear the interrupt condition */
1001 writel(ZYNQ_MEMC_SR_INT_ST1, &zynq_nand_smc_base->cfr);
1008 static int zynq_nand_init(struct nand_chip *nand_chip, int devnum)
1010 struct zynq_nand_info *xnand;
1011 struct mtd_info *mtd;
1012 unsigned long ecc_page_size;
1013 u8 maf_id, dev_id, i;
1015 u8 set_feature[4] = {ONDIE_ECC_FEATURE_ENABLE, 0x00, 0x00, 0x00};
1016 unsigned long ecc_cfg;
1017 int ondie_ecc_enabled = 0;
1020 xnand = calloc(1, sizeof(struct zynq_nand_info));
1022 printf("%s: failed to allocate\n", __func__);
1026 xnand->nand_base = (void __iomem *)ZYNQ_NAND_BASEADDR;
1027 mtd = nand_to_mtd(nand_chip);
1029 nand_chip->priv = xnand;
1030 mtd->priv = nand_chip;
1032 /* Set address of NAND IO lines */
1033 nand_chip->IO_ADDR_R = xnand->nand_base;
1034 nand_chip->IO_ADDR_W = xnand->nand_base;
1036 /* Set the driver entry points for MTD */
1037 nand_chip->cmdfunc = zynq_nand_cmd_function;
1038 nand_chip->dev_ready = zynq_nand_device_ready;
1039 nand_chip->select_chip = zynq_nand_select_chip;
1041 /* If we don't set this delay driver sets 20us by default */
1042 nand_chip->chip_delay = 30;
1044 /* Buffer read/write routines */
1045 nand_chip->read_buf = zynq_nand_read_buf;
1046 nand_chip->write_buf = zynq_nand_write_buf;
1048 nand_chip->bbt_options = NAND_BBT_USE_FLASH;
1050 /* Initialize the NAND flash interface on NAND controller */
1051 if (zynq_nand_init_nand_flash(nand_chip->options) < 0) {
1052 printf("%s: nand flash init failed\n", __func__);
1056 /* first scan to find the device and get the page size */
1057 if (nand_scan_ident(mtd, 1, NULL)) {
1058 printf("%s: nand_scan_ident failed\n", __func__);
1061 /* Send the command for reading device ID */
1062 nand_chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1063 nand_chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
1065 /* Read manufacturer and device IDs */
1066 maf_id = nand_chip->read_byte(mtd);
1067 dev_id = nand_chip->read_byte(mtd);
1069 if ((maf_id == 0x2c) && ((dev_id == 0xf1) ||
1070 (dev_id == 0xa1) || (dev_id == 0xb1) ||
1071 (dev_id == 0xaa) || (dev_id == 0xba) ||
1072 (dev_id == 0xda) || (dev_id == 0xca) ||
1073 (dev_id == 0xac) || (dev_id == 0xbc) ||
1074 (dev_id == 0xdc) || (dev_id == 0xcc) ||
1075 (dev_id == 0xa3) || (dev_id == 0xb3) ||
1076 (dev_id == 0xd3) || (dev_id == 0xc3))) {
1077 nand_chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES,
1078 ONDIE_ECC_FEATURE_ADDR, -1);
1079 for (i = 0; i < 4; i++)
1080 writeb(set_feature[i], nand_chip->IO_ADDR_W);
1082 /* Wait for 1us after writing data with SET_FEATURES command */
1085 nand_chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES,
1086 ONDIE_ECC_FEATURE_ADDR, -1);
1087 nand_chip->read_buf(mtd, get_feature, 4);
1089 if (get_feature[0] & ONDIE_ECC_FEATURE_ENABLE) {
1090 debug("%s: OnDie ECC flash\n", __func__);
1091 ondie_ecc_enabled = 1;
1093 printf("%s: Unable to detect OnDie ECC\n", __func__);
1097 if (ondie_ecc_enabled) {
1098 /* Bypass the controller ECC block */
1099 ecc_cfg = readl(&zynq_nand_smc_base->emcr);
1100 ecc_cfg &= ~ZYNQ_MEMC_NAND_ECC_MODE_MASK;
1101 writel(ecc_cfg, &zynq_nand_smc_base->emcr);
1103 /* The software ECC routines won't work
1104 * with the SMC controller
1106 nand_chip->ecc.mode = NAND_ECC_HW;
1107 nand_chip->ecc.strength = 1;
1108 nand_chip->ecc.read_page = zynq_nand_read_page_raw_nooob;
1109 nand_chip->ecc.read_subpage = zynq_nand_read_subpage_raw;
1110 nand_chip->ecc.write_page = zynq_nand_write_page_raw;
1111 nand_chip->ecc.read_page_raw = zynq_nand_read_page_raw;
1112 nand_chip->ecc.write_page_raw = zynq_nand_write_page_raw;
1113 nand_chip->ecc.read_oob = zynq_nand_read_oob;
1114 nand_chip->ecc.write_oob = zynq_nand_write_oob;
1115 nand_chip->ecc.size = mtd->writesize;
1116 nand_chip->ecc.bytes = 0;
1118 /* NAND with on-die ECC supports subpage reads */
1119 nand_chip->options |= NAND_SUBPAGE_READ;
1121 /* On-Die ECC spare bytes offset 8 is used for ECC codes */
1122 if (ondie_ecc_enabled) {
1123 nand_chip->ecc.layout = &ondie_nand_oob_64;
1124 /* Use the BBT pattern descriptors */
1125 nand_chip->bbt_td = &bbt_main_descr;
1126 nand_chip->bbt_md = &bbt_mirror_descr;
1129 /* Hardware ECC generates 3 bytes ECC code for each 512 bytes */
1130 nand_chip->ecc.mode = NAND_ECC_HW;
1131 nand_chip->ecc.strength = 1;
1132 nand_chip->ecc.size = ZYNQ_NAND_ECC_SIZE;
1133 nand_chip->ecc.bytes = 3;
1134 nand_chip->ecc.calculate = zynq_nand_calculate_hwecc;
1135 nand_chip->ecc.correct = zynq_nand_correct_data;
1136 nand_chip->ecc.hwctl = NULL;
1137 nand_chip->ecc.read_page = zynq_nand_read_page_hwecc;
1138 nand_chip->ecc.write_page = zynq_nand_write_page_hwecc;
1139 nand_chip->ecc.read_page_raw = zynq_nand_read_page_raw;
1140 nand_chip->ecc.write_page_raw = zynq_nand_write_page_raw;
1141 nand_chip->ecc.read_oob = zynq_nand_read_oob;
1142 nand_chip->ecc.write_oob = zynq_nand_write_oob;
1144 switch (mtd->writesize) {
1146 ecc_page_size = 0x1;
1147 /* Set the ECC memory config register */
1148 writel((ZYNQ_NAND_ECC_CONFIG | ecc_page_size),
1149 &zynq_nand_smc_base->emcr);
1152 ecc_page_size = 0x2;
1153 /* Set the ECC memory config register */
1154 writel((ZYNQ_NAND_ECC_CONFIG | ecc_page_size),
1155 &zynq_nand_smc_base->emcr);
1158 ecc_page_size = 0x3;
1159 /* Set the ECC memory config register */
1160 writel((ZYNQ_NAND_ECC_CONFIG | ecc_page_size),
1161 &zynq_nand_smc_base->emcr);
1164 nand_chip->ecc.mode = NAND_ECC_SOFT;
1165 nand_chip->ecc.calculate = nand_calculate_ecc;
1166 nand_chip->ecc.correct = nand_correct_data;
1167 nand_chip->ecc.read_page = zynq_nand_read_page_swecc;
1168 nand_chip->ecc.write_page = zynq_nand_write_page_swecc;
1169 nand_chip->ecc.size = 256;
1173 if (mtd->oobsize == 16)
1174 nand_chip->ecc.layout = &nand_oob_16;
1175 else if (mtd->oobsize == 64)
1176 nand_chip->ecc.layout = &nand_oob_64;
1178 printf("%s: No oob layout found\n", __func__);
1181 /* Second phase scan */
1182 if (nand_scan_tail(mtd)) {
1183 printf("%s: nand_scan_tail failed\n", __func__);
1186 if (nand_register(devnum, mtd))
1194 static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
1196 void board_nand_init(void)
1198 struct nand_chip *nand = &nand_chip[0];
1200 if (zynq_nand_init(nand, 0))
1201 puts("ZYNQ NAND init failed\n");