2 * (C) Copyright 2016 Xilinx, Inc.
4 * Xilinx Zynq NAND Flash Controller Driver
5 * This driver is based on plat_nand.c and mxc_nand.c drivers
7 * SPDX-License-Identifier: GPL-2.0+
13 #include <linux/errno.h>
15 #include <linux/mtd/mtd.h>
16 #include <linux/mtd/rawnand.h>
17 #include <linux/mtd/partitions.h>
18 #include <linux/mtd/nand_ecc.h>
19 #include <asm/arch/hardware.h>
21 /* The NAND flash driver defines */
22 #define ZYNQ_NAND_CMD_PHASE 1
23 #define ZYNQ_NAND_DATA_PHASE 2
24 #define ZYNQ_NAND_ECC_SIZE 512
25 #define ZYNQ_NAND_SET_OPMODE_8BIT (0 << 0)
26 #define ZYNQ_NAND_SET_OPMODE_16BIT (1 << 0)
27 #define ZYNQ_NAND_ECC_STATUS (1 << 6)
28 #define ZYNQ_MEMC_CLRCR_INT_CLR1 (1 << 4)
29 #define ZYNQ_MEMC_SR_RAW_INT_ST1 (1 << 6)
30 #define ZYNQ_MEMC_SR_INT_ST1 (1 << 4)
31 #define ZYNQ_MEMC_NAND_ECC_MODE_MASK 0xC
33 /* Flash memory controller operating parameters */
34 #define ZYNQ_NAND_CLR_CONFIG ((0x1 << 1) | /* Disable interrupt */ \
35 (0x1 << 4) | /* Clear interrupt */ \
36 (0x1 << 6)) /* Disable ECC interrupt */
38 #ifndef CONFIG_NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS
40 /* Assuming 50MHz clock (20ns cycle time) and 3V operation */
41 #define ZYNQ_NAND_SET_CYCLES ((0x2 << 20) | /* t_rr from nand_cycles */ \
42 (0x2 << 17) | /* t_ar from nand_cycles */ \
43 (0x1 << 14) | /* t_clr from nand_cycles */ \
44 (0x3 << 11) | /* t_wp from nand_cycles */ \
45 (0x2 << 8) | /* t_rea from nand_cycles */ \
46 (0x5 << 4) | /* t_wc from nand_cycles */ \
47 (0x5 << 0)) /* t_rc from nand_cycles */
51 #define ZYNQ_NAND_DIRECT_CMD ((0x4 << 23) | /* Chip 0 from interface 1 */ \
52 (0x2 << 21)) /* UpdateRegs operation */
54 #define ZYNQ_NAND_ECC_CONFIG ((0x1 << 2) | /* ECC available on APB */ \
55 (0x1 << 4) | /* ECC read at end of page */ \
56 (0x0 << 5)) /* No Jumping */
58 #define ZYNQ_NAND_ECC_CMD1 ((0x80) | /* Write command */ \
59 (0x00 << 8) | /* Read command */ \
60 (0x30 << 16) | /* Read End command */ \
61 (0x1 << 24)) /* Read End command calid */
63 #define ZYNQ_NAND_ECC_CMD2 ((0x85) | /* Write col change cmd */ \
64 (0x05 << 8) | /* Read col change cmd */ \
65 (0xE0 << 16) | /* Read col change end cmd */ \
66 (0x1 << 24)) /* Read col change
68 /* AXI Address definitions */
69 #define START_CMD_SHIFT 3
70 #define END_CMD_SHIFT 11
71 #define END_CMD_VALID_SHIFT 20
72 #define ADDR_CYCLES_SHIFT 21
73 #define CLEAR_CS_SHIFT 21
74 #define ECC_LAST_SHIFT 10
75 #define COMMAND_PHASE (0 << 19)
76 #define DATA_PHASE (1 << 19)
77 #define ONDIE_ECC_FEATURE_ADDR 0x90
78 #define ONDIE_ECC_FEATURE_ENABLE 0x08
80 #define ZYNQ_NAND_ECC_LAST (1 << ECC_LAST_SHIFT) /* Set ECC_Last */
81 #define ZYNQ_NAND_CLEAR_CS (1 << CLEAR_CS_SHIFT) /* Clear chip select */
83 /* ECC block registers bit position and bit mask */
84 #define ZYNQ_NAND_ECC_BUSY (1 << 6) /* ECC block is busy */
85 #define ZYNQ_NAND_ECC_MASK 0x00FFFFFF /* ECC value mask */
87 #ifndef NAND_CMD_LOCK_TIGHT
88 #define NAND_CMD_LOCK_TIGHT 0x2c
91 #ifndef NAND_CMD_LOCK_STATUS
92 #define NAND_CMD_LOCK_STATUS 0x7a
95 /* SMC register set */
96 struct zynq_nand_smc_regs {
105 u32 emcr; /* 0x404 */
106 u32 emcmd1r; /* 0x408 */
107 u32 emcmd2r; /* 0x40C */
109 u32 eval0r; /* 0x418 */
111 #define zynq_nand_smc_base ((struct zynq_nand_smc_regs __iomem *)\
115 * struct zynq_nand_info - Defines the NAND flash driver instance
116 * @parts: Pointer to the mtd_partition structure
117 * @nand_base: Virtual address of the NAND flash device
118 * @end_cmd_pending: End command is pending
119 * @end_cmd: End command
121 struct zynq_nand_info {
122 void __iomem *nand_base;
128 * struct zynq_nand_command_format - Defines NAND flash command format
129 * @start_cmd: First cycle command (Start command)
130 * @end_cmd: Second cycle command (Last command)
131 * @addr_cycles: Number of address cycles required to send the address
132 * @end_cmd_valid: The second cycle command is valid for cmd or data phase
134 struct zynq_nand_command_format {
141 /* The NAND flash operations command format */
142 static const struct zynq_nand_command_format zynq_nand_commands[] = {
143 {NAND_CMD_READ0, NAND_CMD_READSTART, 5, ZYNQ_NAND_CMD_PHASE},
144 {NAND_CMD_RNDOUT, NAND_CMD_RNDOUTSTART, 2, ZYNQ_NAND_CMD_PHASE},
145 {NAND_CMD_READID, NAND_CMD_NONE, 1, 0},
146 {NAND_CMD_STATUS, NAND_CMD_NONE, 0, 0},
147 {NAND_CMD_SEQIN, NAND_CMD_PAGEPROG, 5, ZYNQ_NAND_DATA_PHASE},
148 {NAND_CMD_RNDIN, NAND_CMD_NONE, 2, 0},
149 {NAND_CMD_ERASE1, NAND_CMD_ERASE2, 3, ZYNQ_NAND_CMD_PHASE},
150 {NAND_CMD_RESET, NAND_CMD_NONE, 0, 0},
151 {NAND_CMD_PARAM, NAND_CMD_NONE, 1, 0},
152 {NAND_CMD_GET_FEATURES, NAND_CMD_NONE, 1, 0},
153 {NAND_CMD_SET_FEATURES, NAND_CMD_NONE, 1, 0},
154 {NAND_CMD_LOCK, NAND_CMD_NONE, 0, 0},
155 {NAND_CMD_LOCK_TIGHT, NAND_CMD_NONE, 0, 0},
156 {NAND_CMD_UNLOCK1, NAND_CMD_NONE, 3, 0},
157 {NAND_CMD_UNLOCK2, NAND_CMD_NONE, 3, 0},
158 {NAND_CMD_LOCK_STATUS, NAND_CMD_NONE, 3, 0},
159 {NAND_CMD_NONE, NAND_CMD_NONE, 0, 0},
160 /* Add all the flash commands supported by the flash device */
163 /* Define default oob placement schemes for large and small page devices */
164 static struct nand_ecclayout nand_oob_16 = {
168 { .offset = 8, .length = 8 }
172 static struct nand_ecclayout nand_oob_64 = {
175 52, 53, 54, 55, 56, 57,
176 58, 59, 60, 61, 62, 63},
178 { .offset = 2, .length = 50 }
182 static struct nand_ecclayout ondie_nand_oob_64 = {
186 8, 9, 10, 11, 12, 13, 14, 15,
187 24, 25, 26, 27, 28, 29, 30, 31,
188 40, 41, 42, 43, 44, 45, 46, 47,
189 56, 57, 58, 59, 60, 61, 62, 63
193 { .offset = 4, .length = 4 },
194 { .offset = 20, .length = 4 },
195 { .offset = 36, .length = 4 },
196 { .offset = 52, .length = 4 }
200 /* bbt decriptors for chips with on-die ECC and
201 chips with 64-byte OOB */
202 static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
203 static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
205 static struct nand_bbt_descr bbt_main_descr = {
206 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
207 NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
212 .pattern = bbt_pattern
215 static struct nand_bbt_descr bbt_mirror_descr = {
216 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
217 NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
222 .pattern = mirror_pattern
226 * zynq_nand_waitfor_ecc_completion - Wait for ECC completion
228 * returns: status for command completion, -1 for Timeout
230 static int zynq_nand_waitfor_ecc_completion(void)
232 unsigned long timeout;
237 status = readl(&zynq_nand_smc_base->esr);
238 while (status & ZYNQ_NAND_ECC_BUSY) {
239 status = readl(&zynq_nand_smc_base->esr);
250 * zynq_nand_init_nand_flash - Initialize NAND controller
251 * @option: Device property flags
253 * This function initializes the NAND flash interface on the NAND controller.
255 * returns: 0 on success or error value on failure
257 static int zynq_nand_init_nand_flash(int option)
261 /* disable interrupts */
262 writel(ZYNQ_NAND_CLR_CONFIG, &zynq_nand_smc_base->cfr);
263 #ifndef CONFIG_NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS
264 /* Initialize the NAND interface by setting cycles and operation mode */
265 writel(ZYNQ_NAND_SET_CYCLES, &zynq_nand_smc_base->scr);
267 if (option & NAND_BUSWIDTH_16)
268 writel(ZYNQ_NAND_SET_OPMODE_16BIT, &zynq_nand_smc_base->sor);
270 writel(ZYNQ_NAND_SET_OPMODE_8BIT, &zynq_nand_smc_base->sor);
272 writel(ZYNQ_NAND_DIRECT_CMD, &zynq_nand_smc_base->dcr);
274 /* Wait till the ECC operation is complete */
275 status = zynq_nand_waitfor_ecc_completion();
277 printf("%s: Timeout\n", __func__);
281 /* Set the command1 and command2 register */
282 writel(ZYNQ_NAND_ECC_CMD1, &zynq_nand_smc_base->emcmd1r);
283 writel(ZYNQ_NAND_ECC_CMD2, &zynq_nand_smc_base->emcmd2r);
289 * zynq_nand_calculate_hwecc - Calculate Hardware ECC
290 * @mtd: Pointer to the mtd_info structure
291 * @data: Pointer to the page data
292 * @ecc_code: Pointer to the ECC buffer where ECC data needs to be stored
294 * This function retrieves the Hardware ECC data from the controller and returns
295 * ECC data back to the MTD subsystem.
297 * returns: 0 on success or error value on failure
299 static int zynq_nand_calculate_hwecc(struct mtd_info *mtd, const u8 *data,
303 u8 ecc_reg, ecc_byte;
306 /* Wait till the ECC operation is complete */
307 ecc_status = zynq_nand_waitfor_ecc_completion();
308 if (ecc_status < 0) {
309 printf("%s: Timeout\n", __func__);
313 for (ecc_reg = 0; ecc_reg < 4; ecc_reg++) {
314 /* Read ECC value for each block */
315 ecc_value = readl(&zynq_nand_smc_base->eval0r + ecc_reg);
317 /* Get the ecc status from ecc read value */
318 ecc_status = (ecc_value >> 24) & 0xFF;
320 /* ECC value valid */
321 if (ecc_status & ZYNQ_NAND_ECC_STATUS) {
322 for (ecc_byte = 0; ecc_byte < 3; ecc_byte++) {
323 /* Copy ECC bytes to MTD buffer */
324 *ecc_code = ecc_value & 0xFF;
325 ecc_value = ecc_value >> 8;
329 debug("%s: ecc status failed\n", __func__);
337 * onehot - onehot function
338 * @value: value to check for onehot
340 * This function checks whether a value is onehot or not.
341 * onehot is if and only if one bit is set.
343 * FIXME: Try to move this in common.h
345 static bool onehot(unsigned short value)
349 onehot = value && !(value & (value - 1));
354 * zynq_nand_correct_data - ECC correction function
355 * @mtd: Pointer to the mtd_info structure
356 * @buf: Pointer to the page data
357 * @read_ecc: Pointer to the ECC value read from spare data area
358 * @calc_ecc: Pointer to the calculated ECC value
360 * This function corrects the ECC single bit errors & detects 2-bit errors.
362 * returns: 0 if no ECC errors found
363 * 1 if single bit error found and corrected.
364 * -1 if multiple ECC errors found.
366 static int zynq_nand_correct_data(struct mtd_info *mtd, unsigned char *buf,
367 unsigned char *read_ecc, unsigned char *calc_ecc)
369 unsigned char bit_addr;
370 unsigned int byte_addr;
371 unsigned short ecc_odd, ecc_even;
372 unsigned short read_ecc_lower, read_ecc_upper;
373 unsigned short calc_ecc_lower, calc_ecc_upper;
375 read_ecc_lower = (read_ecc[0] | (read_ecc[1] << 8)) & 0xfff;
376 read_ecc_upper = ((read_ecc[1] >> 4) | (read_ecc[2] << 4)) & 0xfff;
378 calc_ecc_lower = (calc_ecc[0] | (calc_ecc[1] << 8)) & 0xfff;
379 calc_ecc_upper = ((calc_ecc[1] >> 4) | (calc_ecc[2] << 4)) & 0xfff;
381 ecc_odd = read_ecc_lower ^ calc_ecc_lower;
382 ecc_even = read_ecc_upper ^ calc_ecc_upper;
384 if ((ecc_odd == 0) && (ecc_even == 0))
385 return 0; /* no error */
387 if (ecc_odd == (~ecc_even & 0xfff)) {
388 /* bits [11:3] of error code is byte offset */
389 byte_addr = (ecc_odd >> 3) & 0x1ff;
390 /* bits [2:0] of error code is bit offset */
391 bit_addr = ecc_odd & 0x7;
392 /* Toggling error bit */
393 buf[byte_addr] ^= (1 << bit_addr);
397 if (onehot(ecc_odd | ecc_even))
398 return 1; /* one error in parity */
400 return -1; /* Uncorrectable error */
404 * zynq_nand_read_oob - [REPLACABLE] the most common OOB data read function
405 * @mtd: mtd info structure
406 * @chip: nand chip info structure
407 * @page: page number to read
408 * @sndcmd: flag whether to issue read command or not
410 static int zynq_nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
413 unsigned long data_phase_addr = 0;
417 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
420 chip->read_buf(mtd, p, (mtd->oobsize - data_width));
421 p += mtd->oobsize - data_width;
423 data_phase_addr = (unsigned long)chip->IO_ADDR_R;
424 data_phase_addr |= ZYNQ_NAND_CLEAR_CS;
425 chip->IO_ADDR_R = (void __iomem *)data_phase_addr;
426 chip->read_buf(mtd, p, data_width);
432 * zynq_nand_write_oob - [REPLACABLE] the most common OOB data write function
433 * @mtd: mtd info structure
434 * @chip: nand chip info structure
435 * @page: page number to write
437 static int zynq_nand_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
440 int status = 0, data_width = 4;
441 const u8 *buf = chip->oob_poi;
442 unsigned long data_phase_addr = 0;
444 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
446 chip->write_buf(mtd, buf, (mtd->oobsize - data_width));
447 buf += mtd->oobsize - data_width;
449 data_phase_addr = (unsigned long)chip->IO_ADDR_W;
450 data_phase_addr |= ZYNQ_NAND_CLEAR_CS;
451 data_phase_addr |= (1 << END_CMD_VALID_SHIFT);
452 chip->IO_ADDR_W = (void __iomem *)data_phase_addr;
453 chip->write_buf(mtd, buf, data_width);
455 /* Send command to program the OOB data */
456 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
457 status = chip->waitfunc(mtd, chip);
459 return status & NAND_STATUS_FAIL ? -EIO : 0;
463 * zynq_nand_read_page_raw - [Intern] read raw page data without ecc
464 * @mtd: mtd info structure
465 * @chip: nand chip info structure
466 * @buf: buffer to store read data
467 * @oob_required: must write chip->oob_poi to OOB
468 * @page: page number to read
470 static int zynq_nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
471 u8 *buf, int oob_required, int page)
473 unsigned long data_width = 4;
474 unsigned long data_phase_addr = 0;
477 chip->read_buf(mtd, buf, mtd->writesize);
480 chip->read_buf(mtd, p, (mtd->oobsize - data_width));
481 p += (mtd->oobsize - data_width);
483 data_phase_addr = (unsigned long)chip->IO_ADDR_R;
484 data_phase_addr |= ZYNQ_NAND_CLEAR_CS;
485 chip->IO_ADDR_R = (void __iomem *)data_phase_addr;
487 chip->read_buf(mtd, p, data_width);
491 static int zynq_nand_read_page_raw_nooob(struct mtd_info *mtd,
492 struct nand_chip *chip, u8 *buf, int oob_required, int page)
494 chip->read_buf(mtd, buf, mtd->writesize);
498 static int zynq_nand_read_subpage_raw(struct mtd_info *mtd,
499 struct nand_chip *chip, u32 data_offs,
500 u32 readlen, u8 *buf, int page)
502 if (data_offs != 0) {
503 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_offs, -1);
506 chip->read_buf(mtd, buf, readlen);
512 * zynq_nand_write_page_raw - [Intern] raw page write function
513 * @mtd: mtd info structure
514 * @chip: nand chip info structure
516 * @oob_required: must write chip->oob_poi to OOB
518 static int zynq_nand_write_page_raw(struct mtd_info *mtd,
519 struct nand_chip *chip, const u8 *buf, int oob_required, int page)
521 unsigned long data_width = 4;
522 unsigned long data_phase_addr = 0;
525 chip->write_buf(mtd, buf, mtd->writesize);
528 chip->write_buf(mtd, p, (mtd->oobsize - data_width));
529 p += (mtd->oobsize - data_width);
531 data_phase_addr = (unsigned long)chip->IO_ADDR_W;
532 data_phase_addr |= ZYNQ_NAND_CLEAR_CS;
533 data_phase_addr |= (1 << END_CMD_VALID_SHIFT);
534 chip->IO_ADDR_W = (void __iomem *)data_phase_addr;
536 chip->write_buf(mtd, p, data_width);
542 * nand_write_page_hwecc - Hardware ECC based page write function
543 * @mtd: Pointer to the mtd info structure
544 * @chip: Pointer to the NAND chip info structure
545 * @buf: Pointer to the data buffer
546 * @oob_required: must write chip->oob_poi to OOB
548 * This functions writes data and hardware generated ECC values in to the page.
550 static int zynq_nand_write_page_hwecc(struct mtd_info *mtd,
551 struct nand_chip *chip, const u8 *buf, int oob_required, int page)
553 int i, eccsteps, eccsize = chip->ecc.size;
554 u8 *ecc_calc = chip->buffers->ecccalc;
556 u32 *eccpos = chip->ecc.layout->eccpos;
557 unsigned long data_phase_addr = 0;
558 unsigned long data_width = 4;
561 for (eccsteps = chip->ecc.steps; (eccsteps - 1); eccsteps--) {
562 chip->write_buf(mtd, p, eccsize);
565 chip->write_buf(mtd, p, (eccsize - data_width));
566 p += eccsize - data_width;
568 /* Set ECC Last bit to 1 */
569 data_phase_addr = (unsigned long) chip->IO_ADDR_W;
570 data_phase_addr |= ZYNQ_NAND_ECC_LAST;
571 chip->IO_ADDR_W = (void __iomem *)data_phase_addr;
572 chip->write_buf(mtd, p, data_width);
574 /* Wait for ECC to be calculated and read the error values */
576 chip->ecc.calculate(mtd, p, &ecc_calc[0]);
578 for (i = 0; i < chip->ecc.total; i++)
579 chip->oob_poi[eccpos[i]] = ~(ecc_calc[i]);
581 /* Clear ECC last bit */
582 data_phase_addr = (unsigned long)chip->IO_ADDR_W;
583 data_phase_addr &= ~ZYNQ_NAND_ECC_LAST;
584 chip->IO_ADDR_W = (void __iomem *)data_phase_addr;
586 /* Write the spare area with ECC bytes */
587 oob_ptr = chip->oob_poi;
588 chip->write_buf(mtd, oob_ptr, (mtd->oobsize - data_width));
590 data_phase_addr = (unsigned long)chip->IO_ADDR_W;
591 data_phase_addr |= ZYNQ_NAND_CLEAR_CS;
592 data_phase_addr |= (1 << END_CMD_VALID_SHIFT);
593 chip->IO_ADDR_W = (void __iomem *)data_phase_addr;
594 oob_ptr += (mtd->oobsize - data_width);
595 chip->write_buf(mtd, oob_ptr, data_width);
601 * zynq_nand_write_page_swecc - [REPLACABLE] software ecc based page
603 * @mtd: mtd info structure
604 * @chip: nand chip info structure
606 * @oob_required: must write chip->oob_poi to OOB
608 static int zynq_nand_write_page_swecc(struct mtd_info *mtd,
609 struct nand_chip *chip, const u8 *buf, int oob_required, int page)
611 int i, eccsize = chip->ecc.size;
612 int eccbytes = chip->ecc.bytes;
613 int eccsteps = chip->ecc.steps;
614 u8 *ecc_calc = chip->buffers->ecccalc;
616 u32 *eccpos = chip->ecc.layout->eccpos;
618 /* Software ecc calculation */
619 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
620 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
622 for (i = 0; i < chip->ecc.total; i++)
623 chip->oob_poi[eccpos[i]] = ecc_calc[i];
625 return chip->ecc.write_page_raw(mtd, chip, buf, 1, page);
629 * nand_read_page_hwecc - Hardware ECC based page read function
630 * @mtd: Pointer to the mtd info structure
631 * @chip: Pointer to the NAND chip info structure
632 * @buf: Pointer to the buffer to store read data
633 * @oob_required: must write chip->oob_poi to OOB
634 * @page: page number to read
636 * This functions reads data and checks the data integrity by comparing hardware
637 * generated ECC values and read ECC values from spare area.
639 * returns: 0 always and updates ECC operation status in to MTD structure
641 static int zynq_nand_read_page_hwecc(struct mtd_info *mtd,
642 struct nand_chip *chip, u8 *buf, int oob_required, int page)
644 int i, stat, eccsteps, eccsize = chip->ecc.size;
645 int eccbytes = chip->ecc.bytes;
647 u8 *ecc_calc = chip->buffers->ecccalc;
648 u8 *ecc_code = chip->buffers->ecccode;
649 u32 *eccpos = chip->ecc.layout->eccpos;
650 unsigned long data_phase_addr = 0;
651 unsigned long data_width = 4;
654 for (eccsteps = chip->ecc.steps; (eccsteps - 1); eccsteps--) {
655 chip->read_buf(mtd, p, eccsize);
658 chip->read_buf(mtd, p, (eccsize - data_width));
659 p += eccsize - data_width;
661 /* Set ECC Last bit to 1 */
662 data_phase_addr = (unsigned long)chip->IO_ADDR_R;
663 data_phase_addr |= ZYNQ_NAND_ECC_LAST;
664 chip->IO_ADDR_R = (void __iomem *)data_phase_addr;
665 chip->read_buf(mtd, p, data_width);
667 /* Read the calculated ECC value */
669 chip->ecc.calculate(mtd, p, &ecc_calc[0]);
671 /* Clear ECC last bit */
672 data_phase_addr = (unsigned long)chip->IO_ADDR_R;
673 data_phase_addr &= ~ZYNQ_NAND_ECC_LAST;
674 chip->IO_ADDR_R = (void __iomem *)data_phase_addr;
676 /* Read the stored ECC value */
677 oob_ptr = chip->oob_poi;
678 chip->read_buf(mtd, oob_ptr, (mtd->oobsize - data_width));
680 /* de-assert chip select */
681 data_phase_addr = (unsigned long)chip->IO_ADDR_R;
682 data_phase_addr |= ZYNQ_NAND_CLEAR_CS;
683 chip->IO_ADDR_R = (void __iomem *)data_phase_addr;
685 oob_ptr += (mtd->oobsize - data_width);
686 chip->read_buf(mtd, oob_ptr, data_width);
688 for (i = 0; i < chip->ecc.total; i++)
689 ecc_code[i] = ~(chip->oob_poi[eccpos[i]]);
691 eccsteps = chip->ecc.steps;
694 /* Check ECC error for all blocks and correct if it is correctable */
695 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
696 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
698 mtd->ecc_stats.failed++;
700 mtd->ecc_stats.corrected += stat;
706 * zynq_nand_read_page_swecc - [REPLACABLE] software ecc based page
708 * @mtd: mtd info structure
709 * @chip: nand chip info structure
710 * @buf: buffer to store read data
711 * @page: page number to read
713 static int zynq_nand_read_page_swecc(struct mtd_info *mtd,
714 struct nand_chip *chip, u8 *buf, int oob_required, int page)
716 int i, eccsize = chip->ecc.size;
717 int eccbytes = chip->ecc.bytes;
718 int eccsteps = chip->ecc.steps;
720 u8 *ecc_calc = chip->buffers->ecccalc;
721 u8 *ecc_code = chip->buffers->ecccode;
722 u32 *eccpos = chip->ecc.layout->eccpos;
724 chip->ecc.read_page_raw(mtd, chip, buf, 1, page);
726 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
727 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
729 for (i = 0; i < chip->ecc.total; i++)
730 ecc_code[i] = chip->oob_poi[eccpos[i]];
732 eccsteps = chip->ecc.steps;
735 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
738 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
740 mtd->ecc_stats.failed++;
742 mtd->ecc_stats.corrected += stat;
748 * zynq_nand_select_chip - Select the flash device
749 * @mtd: Pointer to the mtd_info structure
750 * @chip: Chip number to be selected
752 * This function is empty as the NAND controller handles chip select line
753 * internally based on the chip address passed in command and data phase.
755 static void zynq_nand_select_chip(struct mtd_info *mtd, int chip)
757 /* Not support multiple chips yet */
761 * zynq_nand_cmd_function - Send command to NAND device
762 * @mtd: Pointer to the mtd_info structure
763 * @command: The command to be sent to the flash device
764 * @column: The column address for this command, -1 if none
765 * @page_addr: The page address for this command, -1 if none
767 static void zynq_nand_cmd_function(struct mtd_info *mtd, unsigned int command,
768 int column, int page_addr)
770 struct nand_chip *chip = mtd->priv;
771 const struct zynq_nand_command_format *curr_cmd = NULL;
772 struct zynq_nand_info *xnand = (struct zynq_nand_info *)chip->priv;
774 unsigned long cmd_data = 0;
775 unsigned long cmd_phase_addr = 0;
776 unsigned long data_phase_addr = 0;
778 u8 end_cmd_valid = 0;
781 if (xnand->end_cmd_pending) {
782 /* Check for end command if this command request is same as the
783 * pending command then return
785 if (xnand->end_cmd == command) {
787 xnand->end_cmd_pending = 0;
792 /* Emulate NAND_CMD_READOOB for large page device */
793 if ((mtd->writesize > ZYNQ_NAND_ECC_SIZE) &&
794 (command == NAND_CMD_READOOB)) {
795 column += mtd->writesize;
796 command = NAND_CMD_READ0;
799 /* Get the command format */
800 for (index = 0; index < ARRAY_SIZE(zynq_nand_commands); index++)
801 if (command == zynq_nand_commands[index].start_cmd)
804 if (index == ARRAY_SIZE(zynq_nand_commands)) {
805 printf("%s: Unsupported start cmd %02x\n", __func__, command);
808 curr_cmd = &zynq_nand_commands[index];
810 /* Clear interrupt */
811 writel(ZYNQ_MEMC_CLRCR_INT_CLR1, &zynq_nand_smc_base->cfr);
813 /* Get the command phase address */
814 if (curr_cmd->end_cmd_valid == ZYNQ_NAND_CMD_PHASE)
817 if (curr_cmd->end_cmd == NAND_CMD_NONE)
820 end_cmd = curr_cmd->end_cmd;
822 cmd_phase_addr = (unsigned long)xnand->nand_base |
823 (curr_cmd->addr_cycles << ADDR_CYCLES_SHIFT) |
824 (end_cmd_valid << END_CMD_VALID_SHIFT) |
826 (end_cmd << END_CMD_SHIFT) |
827 (curr_cmd->start_cmd << START_CMD_SHIFT);
829 cmd_addr = (void __iomem *)cmd_phase_addr;
831 /* Get the data phase address */
834 data_phase_addr = (unsigned long)xnand->nand_base |
835 (0x0 << CLEAR_CS_SHIFT) |
836 (end_cmd_valid << END_CMD_VALID_SHIFT) |
838 (end_cmd << END_CMD_SHIFT) |
839 (0x0 << ECC_LAST_SHIFT);
841 chip->IO_ADDR_R = (void __iomem *)data_phase_addr;
842 chip->IO_ADDR_W = chip->IO_ADDR_R;
844 /* Command phase AXI Read & Write */
845 if (column != -1 && page_addr != -1) {
846 /* Adjust columns for 16 bit bus width */
847 if (chip->options & NAND_BUSWIDTH_16)
850 if (mtd->writesize > ZYNQ_NAND_ECC_SIZE) {
851 cmd_data |= page_addr << 16;
852 /* Another address cycle for devices > 128MiB */
853 if (chip->chipsize > (128 << 20)) {
854 writel(cmd_data, cmd_addr);
855 cmd_data = (page_addr >> 16);
858 cmd_data |= page_addr << 8;
860 } else if (page_addr != -1) { /* Erase */
861 cmd_data = page_addr;
862 } else if (column != -1) { /* Change read/write column, read id etc */
863 /* Adjust columns for 16 bit bus width */
864 if ((chip->options & NAND_BUSWIDTH_16) &&
865 ((command == NAND_CMD_READ0) ||
866 (command == NAND_CMD_SEQIN) ||
867 (command == NAND_CMD_RNDOUT) ||
868 (command == NAND_CMD_RNDIN)))
873 writel(cmd_data, cmd_addr);
875 if (curr_cmd->end_cmd_valid) {
876 xnand->end_cmd = curr_cmd->end_cmd;
877 xnand->end_cmd_pending = 1;
882 if ((command == NAND_CMD_READ0) ||
883 (command == NAND_CMD_RESET) ||
884 (command == NAND_CMD_PARAM) ||
885 (command == NAND_CMD_GET_FEATURES))
886 /* wait until command is processed */
887 nand_wait_ready(mtd);
891 * zynq_nand_read_buf - read chip data into buffer
892 * @mtd: MTD device structure
893 * @buf: buffer to store date
894 * @len: number of bytes to read
896 static void zynq_nand_read_buf(struct mtd_info *mtd, u8 *buf, int len)
898 struct nand_chip *chip = mtd->priv;
900 /* Make sure that buf is 32 bit aligned */
901 if (((unsigned long)buf & 0x3) != 0) {
902 if (((unsigned long)buf & 0x1) != 0) {
904 *buf = readb(chip->IO_ADDR_R);
910 if (((unsigned long)buf & 0x3) != 0) {
912 *(u16 *)buf = readw(chip->IO_ADDR_R);
919 /* copy aligned data */
921 *(u32 *)buf = readl(chip->IO_ADDR_R);
926 /* mop up any remaining bytes */
929 *(u16 *)buf = readw(chip->IO_ADDR_R);
934 *buf = readb(chip->IO_ADDR_R);
939 * zynq_nand_write_buf - write buffer to chip
940 * @mtd: MTD device structure
942 * @len: number of bytes to write
944 static void zynq_nand_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
946 struct nand_chip *chip = mtd->priv;
947 const u32 *nand = chip->IO_ADDR_W;
949 /* Make sure that buf is 32 bit aligned */
950 if (((unsigned long)buf & 0x3) != 0) {
951 if (((unsigned long)buf & 0x1) != 0) {
959 if (((unsigned long)buf & 0x3) != 0) {
961 writew(*(u16 *)buf, nand);
968 /* copy aligned data */
970 writel(*(u32 *)buf, nand);
975 /* mop up any remaining bytes */
978 writew(*(u16 *)buf, nand);
989 * zynq_nand_device_ready - Check device ready/busy line
990 * @mtd: Pointer to the mtd_info structure
992 * returns: 0 on busy or 1 on ready state
994 static int zynq_nand_device_ready(struct mtd_info *mtd)
998 csr_val = readl(&zynq_nand_smc_base->csr);
999 /* Check the raw_int_status1 bit */
1000 if (csr_val & ZYNQ_MEMC_SR_RAW_INT_ST1) {
1001 /* Clear the interrupt condition */
1002 writel(ZYNQ_MEMC_SR_INT_ST1, &zynq_nand_smc_base->cfr);
1009 static int zynq_nand_init(struct nand_chip *nand_chip, int devnum)
1011 struct zynq_nand_info *xnand;
1012 struct mtd_info *mtd;
1013 unsigned long ecc_page_size;
1014 u8 maf_id, dev_id, i;
1016 u8 set_feature[4] = {ONDIE_ECC_FEATURE_ENABLE, 0x00, 0x00, 0x00};
1017 unsigned long ecc_cfg;
1018 int ondie_ecc_enabled = 0;
1021 xnand = calloc(1, sizeof(struct zynq_nand_info));
1023 printf("%s: failed to allocate\n", __func__);
1027 xnand->nand_base = (void __iomem *)ZYNQ_NAND_BASEADDR;
1028 mtd = nand_to_mtd(nand_chip);
1030 nand_chip->priv = xnand;
1031 mtd->priv = nand_chip;
1033 /* Set address of NAND IO lines */
1034 nand_chip->IO_ADDR_R = xnand->nand_base;
1035 nand_chip->IO_ADDR_W = xnand->nand_base;
1037 /* Set the driver entry points for MTD */
1038 nand_chip->cmdfunc = zynq_nand_cmd_function;
1039 nand_chip->dev_ready = zynq_nand_device_ready;
1040 nand_chip->select_chip = zynq_nand_select_chip;
1042 /* If we don't set this delay driver sets 20us by default */
1043 nand_chip->chip_delay = 30;
1045 /* Buffer read/write routines */
1046 nand_chip->read_buf = zynq_nand_read_buf;
1047 nand_chip->write_buf = zynq_nand_write_buf;
1049 nand_chip->bbt_options = NAND_BBT_USE_FLASH;
1051 /* Initialize the NAND flash interface on NAND controller */
1052 if (zynq_nand_init_nand_flash(nand_chip->options) < 0) {
1053 printf("%s: nand flash init failed\n", __func__);
1057 /* first scan to find the device and get the page size */
1058 if (nand_scan_ident(mtd, 1, NULL)) {
1059 printf("%s: nand_scan_ident failed\n", __func__);
1062 /* Send the command for reading device ID */
1063 nand_chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1064 nand_chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
1066 /* Read manufacturer and device IDs */
1067 maf_id = nand_chip->read_byte(mtd);
1068 dev_id = nand_chip->read_byte(mtd);
1070 if ((maf_id == 0x2c) && ((dev_id == 0xf1) ||
1071 (dev_id == 0xa1) || (dev_id == 0xb1) ||
1072 (dev_id == 0xaa) || (dev_id == 0xba) ||
1073 (dev_id == 0xda) || (dev_id == 0xca) ||
1074 (dev_id == 0xac) || (dev_id == 0xbc) ||
1075 (dev_id == 0xdc) || (dev_id == 0xcc) ||
1076 (dev_id == 0xa3) || (dev_id == 0xb3) ||
1077 (dev_id == 0xd3) || (dev_id == 0xc3))) {
1078 nand_chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES,
1079 ONDIE_ECC_FEATURE_ADDR, -1);
1080 for (i = 0; i < 4; i++)
1081 writeb(set_feature[i], nand_chip->IO_ADDR_W);
1083 /* Wait for 1us after writing data with SET_FEATURES command */
1086 nand_chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES,
1087 ONDIE_ECC_FEATURE_ADDR, -1);
1088 nand_chip->read_buf(mtd, get_feature, 4);
1090 if (get_feature[0] & ONDIE_ECC_FEATURE_ENABLE) {
1091 debug("%s: OnDie ECC flash\n", __func__);
1092 ondie_ecc_enabled = 1;
1094 printf("%s: Unable to detect OnDie ECC\n", __func__);
1098 if (ondie_ecc_enabled) {
1099 /* Bypass the controller ECC block */
1100 ecc_cfg = readl(&zynq_nand_smc_base->emcr);
1101 ecc_cfg &= ~ZYNQ_MEMC_NAND_ECC_MODE_MASK;
1102 writel(ecc_cfg, &zynq_nand_smc_base->emcr);
1104 /* The software ECC routines won't work
1105 * with the SMC controller
1107 nand_chip->ecc.mode = NAND_ECC_HW;
1108 nand_chip->ecc.strength = 1;
1109 nand_chip->ecc.read_page = zynq_nand_read_page_raw_nooob;
1110 nand_chip->ecc.read_subpage = zynq_nand_read_subpage_raw;
1111 nand_chip->ecc.write_page = zynq_nand_write_page_raw;
1112 nand_chip->ecc.read_page_raw = zynq_nand_read_page_raw;
1113 nand_chip->ecc.write_page_raw = zynq_nand_write_page_raw;
1114 nand_chip->ecc.read_oob = zynq_nand_read_oob;
1115 nand_chip->ecc.write_oob = zynq_nand_write_oob;
1116 nand_chip->ecc.size = mtd->writesize;
1117 nand_chip->ecc.bytes = 0;
1119 /* NAND with on-die ECC supports subpage reads */
1120 nand_chip->options |= NAND_SUBPAGE_READ;
1122 /* On-Die ECC spare bytes offset 8 is used for ECC codes */
1123 if (ondie_ecc_enabled) {
1124 nand_chip->ecc.layout = &ondie_nand_oob_64;
1125 /* Use the BBT pattern descriptors */
1126 nand_chip->bbt_td = &bbt_main_descr;
1127 nand_chip->bbt_md = &bbt_mirror_descr;
1130 /* Hardware ECC generates 3 bytes ECC code for each 512 bytes */
1131 nand_chip->ecc.mode = NAND_ECC_HW;
1132 nand_chip->ecc.strength = 1;
1133 nand_chip->ecc.size = ZYNQ_NAND_ECC_SIZE;
1134 nand_chip->ecc.bytes = 3;
1135 nand_chip->ecc.calculate = zynq_nand_calculate_hwecc;
1136 nand_chip->ecc.correct = zynq_nand_correct_data;
1137 nand_chip->ecc.hwctl = NULL;
1138 nand_chip->ecc.read_page = zynq_nand_read_page_hwecc;
1139 nand_chip->ecc.write_page = zynq_nand_write_page_hwecc;
1140 nand_chip->ecc.read_page_raw = zynq_nand_read_page_raw;
1141 nand_chip->ecc.write_page_raw = zynq_nand_write_page_raw;
1142 nand_chip->ecc.read_oob = zynq_nand_read_oob;
1143 nand_chip->ecc.write_oob = zynq_nand_write_oob;
1145 switch (mtd->writesize) {
1147 ecc_page_size = 0x1;
1148 /* Set the ECC memory config register */
1149 writel((ZYNQ_NAND_ECC_CONFIG | ecc_page_size),
1150 &zynq_nand_smc_base->emcr);
1153 ecc_page_size = 0x2;
1154 /* Set the ECC memory config register */
1155 writel((ZYNQ_NAND_ECC_CONFIG | ecc_page_size),
1156 &zynq_nand_smc_base->emcr);
1159 ecc_page_size = 0x3;
1160 /* Set the ECC memory config register */
1161 writel((ZYNQ_NAND_ECC_CONFIG | ecc_page_size),
1162 &zynq_nand_smc_base->emcr);
1165 nand_chip->ecc.mode = NAND_ECC_SOFT;
1166 nand_chip->ecc.calculate = nand_calculate_ecc;
1167 nand_chip->ecc.correct = nand_correct_data;
1168 nand_chip->ecc.read_page = zynq_nand_read_page_swecc;
1169 nand_chip->ecc.write_page = zynq_nand_write_page_swecc;
1170 nand_chip->ecc.size = 256;
1174 if (mtd->oobsize == 16)
1175 nand_chip->ecc.layout = &nand_oob_16;
1176 else if (mtd->oobsize == 64)
1177 nand_chip->ecc.layout = &nand_oob_64;
1179 printf("%s: No oob layout found\n", __func__);
1182 /* Second phase scan */
1183 if (nand_scan_tail(mtd)) {
1184 printf("%s: nand_scan_tail failed\n", __func__);
1187 if (nand_register(devnum, mtd))
1195 static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
1197 void board_nand_init(void)
1199 struct nand_chip *nand = &nand_chip[0];
1201 if (zynq_nand_init(nand, 0))
1202 puts("ZYNQ NAND init failed\n");