2 * Copyright 2009-2014 Freescale Semiconductor, Inc. and others
4 * Description: MPC5125, VF610, MCF54418 and Kinetis K70 Nand driver.
5 * Ported to U-Boot by Stefan Agner
6 * Based on RFC driver posted on Kernel Mailing list by Bill Pringlemeir
7 * Jason ported to M54418TWR and MVFA5.
8 * Authors: Stefan Agner <stefan.agner@toradex.com>
9 * Bill Pringlemeir <bpringlemeir@nbsps.com>
10 * Shaohui Xie <b21989@freescale.com>
11 * Jason Jin <Jason.jin@freescale.com>
13 * Based on original driver mpc5121_nfc.c.
15 * This is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
21 * - Untested on MPC5125 and M54418.
24 * - Only 2K page w. 64+OOB and hardware ECC.
30 #include <linux/mtd/mtd.h>
31 #include <linux/mtd/nand.h>
32 #include <linux/mtd/partitions.h>
38 /* Register Offsets */
39 #define NFC_FLASH_CMD1 0x3F00
40 #define NFC_FLASH_CMD2 0x3F04
41 #define NFC_COL_ADDR 0x3F08
42 #define NFC_ROW_ADDR 0x3F0c
43 #define NFC_ROW_ADDR_INC 0x3F14
44 #define NFC_FLASH_STATUS1 0x3F18
45 #define NFC_FLASH_STATUS2 0x3F1c
46 #define NFC_CACHE_SWAP 0x3F28
47 #define NFC_SECTOR_SIZE 0x3F2c
48 #define NFC_FLASH_CONFIG 0x3F30
49 #define NFC_IRQ_STATUS 0x3F38
51 /* Addresses for NFC MAIN RAM BUFFER areas */
52 #define NFC_MAIN_AREA(n) ((n) * 0x1000)
54 #define PAGE_2K 0x0800
58 * NFC_CMD2[CODE] values. See section:
59 * - 31.4.7 Flash Command Code Description, Vybrid manual
60 * - 23.8.6 Flash Command Sequencer, MPC5125 manual
62 * Briefly these are bitmasks of controller cycles.
64 #define READ_PAGE_CMD_CODE 0x7EE0
65 #define PROGRAM_PAGE_CMD_CODE 0x7FC0
66 #define ERASE_CMD_CODE 0x4EC0
67 #define READ_ID_CMD_CODE 0x4804
68 #define RESET_CMD_CODE 0x4040
69 #define STATUS_READ_CMD_CODE 0x4068
71 /* NFC ECC mode define */
75 /*** Register Mask and bit definitions */
77 /* NFC_FLASH_CMD1 Field */
78 #define CMD_BYTE2_MASK 0xFF000000
79 #define CMD_BYTE2_SHIFT 24
81 /* NFC_FLASH_CM2 Field */
82 #define CMD_BYTE1_MASK 0xFF000000
83 #define CMD_BYTE1_SHIFT 24
84 #define CMD_CODE_MASK 0x00FFFF00
85 #define CMD_CODE_SHIFT 8
86 #define BUFNO_MASK 0x00000006
88 #define START_BIT (1<<0)
90 /* NFC_COL_ADDR Field */
91 #define COL_ADDR_MASK 0x0000FFFF
92 #define COL_ADDR_SHIFT 0
94 /* NFC_ROW_ADDR Field */
95 #define ROW_ADDR_MASK 0x00FFFFFF
96 #define ROW_ADDR_SHIFT 0
97 #define ROW_ADDR_CHIP_SEL_RB_MASK 0xF0000000
98 #define ROW_ADDR_CHIP_SEL_RB_SHIFT 28
99 #define ROW_ADDR_CHIP_SEL_MASK 0x0F000000
100 #define ROW_ADDR_CHIP_SEL_SHIFT 24
102 /* NFC_FLASH_STATUS2 Field */
103 #define STATUS_BYTE1_MASK 0x000000FF
105 /* NFC_FLASH_CONFIG Field */
106 #define CONFIG_ECC_SRAM_ADDR_MASK 0x7FC00000
107 #define CONFIG_ECC_SRAM_ADDR_SHIFT 22
108 #define CONFIG_ECC_SRAM_REQ_BIT (1<<21)
109 #define CONFIG_DMA_REQ_BIT (1<<20)
110 #define CONFIG_ECC_MODE_MASK 0x000E0000
111 #define CONFIG_ECC_MODE_SHIFT 17
112 #define CONFIG_FAST_FLASH_BIT (1<<16)
113 #define CONFIG_16BIT (1<<7)
114 #define CONFIG_BOOT_MODE_BIT (1<<6)
115 #define CONFIG_ADDR_AUTO_INCR_BIT (1<<5)
116 #define CONFIG_BUFNO_AUTO_INCR_BIT (1<<4)
117 #define CONFIG_PAGE_CNT_MASK 0xF
118 #define CONFIG_PAGE_CNT_SHIFT 0
120 /* NFC_IRQ_STATUS Field */
121 #define IDLE_IRQ_BIT (1<<29)
122 #define IDLE_EN_BIT (1<<20)
123 #define CMD_DONE_CLEAR_BIT (1<<18)
124 #define IDLE_CLEAR_BIT (1<<17)
126 #define NFC_TIMEOUT (1000)
128 /* ECC status placed at end of buffers. */
129 #define ECC_SRAM_ADDR ((PAGE_2K+256-8) >> 3)
130 #define ECC_STATUS_MASK 0x80
131 #define ECC_ERR_COUNT 0x3F
134 * ECC status is stored at NFC_CFG[ECCADD] +4 for little-endian
135 * and +7 for big-endian SOC.
144 struct mtd_info *mtd;
145 struct nand_chip chip;
148 /* Status and ID are in alternate locations. */
151 #define ALT_BUF_STAT 2
155 #define mtd_to_nfc(_mtd) \
156 (struct vf610_nfc *)((struct nand_chip *)_mtd->priv)->priv
158 static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
159 static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
161 static struct nand_bbt_descr bbt_main_descr = {
162 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
163 NAND_BBT_2BIT | NAND_BBT_VERSION,
168 .pattern = bbt_pattern,
171 static struct nand_bbt_descr bbt_mirror_descr = {
172 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
173 NAND_BBT_2BIT | NAND_BBT_VERSION,
178 .pattern = mirror_pattern,
181 static struct nand_ecclayout vf610_nfc_ecc45 = {
183 .eccpos = {19, 20, 21, 22, 23,
184 24, 25, 26, 27, 28, 29, 30, 31,
185 32, 33, 34, 35, 36, 37, 38, 39,
186 40, 41, 42, 43, 44, 45, 46, 47,
187 48, 49, 50, 51, 52, 53, 54, 55,
188 56, 57, 58, 59, 60, 61, 62, 63},
194 static inline u32 vf610_nfc_read(struct mtd_info *mtd, uint reg)
196 struct vf610_nfc *nfc = mtd_to_nfc(mtd);
198 return readl(nfc->regs + reg);
201 static inline void vf610_nfc_write(struct mtd_info *mtd, uint reg, u32 val)
203 struct vf610_nfc *nfc = mtd_to_nfc(mtd);
205 writel(val, nfc->regs + reg);
208 static inline void vf610_nfc_set(struct mtd_info *mtd, uint reg, u32 bits)
210 vf610_nfc_write(mtd, reg, vf610_nfc_read(mtd, reg) | bits);
213 static inline void vf610_nfc_clear(struct mtd_info *mtd, uint reg, u32 bits)
215 vf610_nfc_write(mtd, reg, vf610_nfc_read(mtd, reg) & ~bits);
218 static inline void vf610_nfc_set_field(struct mtd_info *mtd, u32 reg,
219 u32 mask, u32 shift, u32 val)
221 vf610_nfc_write(mtd, reg,
222 (vf610_nfc_read(mtd, reg) & (~mask)) | val << shift);
225 static inline void vf610_nfc_memcpy(void *dst, const void *src, size_t n)
228 * Use this accessor for the interal SRAM buffers. On ARM we can
229 * treat the SRAM buffer as if its memory, hence use memcpy
234 /* Clear flags for upcoming command */
235 static inline void vf610_nfc_clear_status(void __iomem *regbase)
237 void __iomem *reg = regbase + NFC_IRQ_STATUS;
238 u32 tmp = __raw_readl(reg);
239 tmp |= CMD_DONE_CLEAR_BIT | IDLE_CLEAR_BIT;
240 __raw_writel(tmp, reg);
243 /* Wait for complete operation */
244 static inline void vf610_nfc_done(struct mtd_info *mtd)
246 struct vf610_nfc *nfc = mtd_to_nfc(mtd);
250 * Barrier is needed after this write. This write need
251 * to be done before reading the next register the first
253 * vf610_nfc_set implicates such a barrier by using writel
254 * to write to the register.
256 vf610_nfc_set(mtd, NFC_FLASH_CMD2, START_BIT);
258 start = get_timer(0);
260 while (!(vf610_nfc_read(mtd, NFC_IRQ_STATUS) & IDLE_IRQ_BIT)) {
261 if (get_timer(start) > NFC_TIMEOUT) {
262 printf("Timeout while waiting for !BUSY.\n");
266 vf610_nfc_clear_status(nfc->regs);
269 static u8 vf610_nfc_get_id(struct mtd_info *mtd, int col)
274 flash_id = vf610_nfc_read(mtd, NFC_FLASH_STATUS1);
275 return (flash_id >> (3-col)*8) & 0xff;
277 flash_id = vf610_nfc_read(mtd, NFC_FLASH_STATUS2);
278 return flash_id >> 24;
282 static u8 vf610_nfc_get_status(struct mtd_info *mtd)
284 return vf610_nfc_read(mtd, NFC_FLASH_STATUS2) & STATUS_BYTE1_MASK;
288 static void vf610_nfc_send_command(void __iomem *regbase, u32 cmd_byte1,
291 void __iomem *reg = regbase + NFC_FLASH_CMD2;
293 vf610_nfc_clear_status(regbase);
295 tmp = __raw_readl(reg);
296 tmp &= ~(CMD_BYTE1_MASK | CMD_CODE_MASK | BUFNO_MASK);
297 tmp |= cmd_byte1 << CMD_BYTE1_SHIFT;
298 tmp |= cmd_code << CMD_CODE_SHIFT;
299 __raw_writel(tmp, reg);
303 static void vf610_nfc_send_commands(void __iomem *regbase, u32 cmd_byte1,
304 u32 cmd_byte2, u32 cmd_code)
306 void __iomem *reg = regbase + NFC_FLASH_CMD1;
308 vf610_nfc_send_command(regbase, cmd_byte1, cmd_code);
310 tmp = __raw_readl(reg);
311 tmp &= ~CMD_BYTE2_MASK;
312 tmp |= cmd_byte2 << CMD_BYTE2_SHIFT;
313 __raw_writel(tmp, reg);
316 static void vf610_nfc_addr_cycle(struct mtd_info *mtd, int column, int page)
319 struct vf610_nfc *nfc = mtd_to_nfc(mtd);
320 if (nfc->chip.options & NAND_BUSWIDTH_16)
322 vf610_nfc_set_field(mtd, NFC_COL_ADDR, COL_ADDR_MASK,
323 COL_ADDR_SHIFT, column);
326 vf610_nfc_set_field(mtd, NFC_ROW_ADDR, ROW_ADDR_MASK,
327 ROW_ADDR_SHIFT, page);
330 static inline void vf610_nfc_ecc_mode(struct mtd_info *mtd, int ecc_mode)
332 vf610_nfc_set_field(mtd, NFC_FLASH_CONFIG,
333 CONFIG_ECC_MODE_MASK,
334 CONFIG_ECC_MODE_SHIFT, ecc_mode);
337 static inline void vf610_nfc_transfer_size(void __iomem *regbase, int size)
339 __raw_writel(size, regbase + NFC_SECTOR_SIZE);
342 /* Send command to NAND chip */
343 static void vf610_nfc_command(struct mtd_info *mtd, unsigned command,
344 int column, int page)
346 struct vf610_nfc *nfc = mtd_to_nfc(mtd);
347 int page_sz = nfc->chip.options & NAND_BUSWIDTH_16 ? 1 : 0;
349 nfc->column = max(column, 0);
354 /* Use valid column/page from preread... */
355 vf610_nfc_addr_cycle(mtd, column, page);
357 * SEQIN => data => PAGEPROG sequence is done by the controller
358 * hence we do not need to issue the command here...
361 case NAND_CMD_PAGEPROG:
362 page_sz += mtd->writesize + mtd->oobsize;
363 vf610_nfc_transfer_size(nfc->regs, page_sz);
364 vf610_nfc_send_commands(nfc->regs, NAND_CMD_SEQIN,
365 command, PROGRAM_PAGE_CMD_CODE);
366 vf610_nfc_ecc_mode(mtd, ECC_45_BYTE);
370 vf610_nfc_transfer_size(nfc->regs, 0);
371 vf610_nfc_send_command(nfc->regs, command, RESET_CMD_CODE);
374 case NAND_CMD_READOOB:
375 page_sz += mtd->oobsize;
376 column = mtd->writesize;
377 vf610_nfc_transfer_size(nfc->regs, page_sz);
378 vf610_nfc_send_commands(nfc->regs, NAND_CMD_READ0,
379 NAND_CMD_READSTART, READ_PAGE_CMD_CODE);
380 vf610_nfc_addr_cycle(mtd, column, page);
381 vf610_nfc_ecc_mode(mtd, ECC_BYPASS);
385 page_sz += mtd->writesize + mtd->oobsize;
387 vf610_nfc_transfer_size(nfc->regs, page_sz);
388 vf610_nfc_send_commands(nfc->regs, NAND_CMD_READ0,
389 NAND_CMD_READSTART, READ_PAGE_CMD_CODE);
390 vf610_nfc_addr_cycle(mtd, column, page);
391 vf610_nfc_ecc_mode(mtd, ECC_45_BYTE);
394 case NAND_CMD_ERASE1:
395 vf610_nfc_transfer_size(nfc->regs, 0);
396 vf610_nfc_send_commands(nfc->regs, command,
397 NAND_CMD_ERASE2, ERASE_CMD_CODE);
398 vf610_nfc_addr_cycle(mtd, column, page);
401 case NAND_CMD_READID:
402 nfc->alt_buf = ALT_BUF_ID;
403 vf610_nfc_transfer_size(nfc->regs, 0);
404 vf610_nfc_send_command(nfc->regs, command, READ_ID_CMD_CODE);
407 case NAND_CMD_STATUS:
408 nfc->alt_buf = ALT_BUF_STAT;
409 vf610_nfc_transfer_size(nfc->regs, 0);
410 vf610_nfc_send_command(nfc->regs, command,
411 STATUS_READ_CMD_CODE);
420 /* Read data from NFC buffers */
421 static void vf610_nfc_read_buf(struct mtd_info *mtd, u_char *buf, int len)
423 struct vf610_nfc *nfc = mtd_to_nfc(mtd);
424 uint c = nfc->column;
426 switch (nfc->alt_buf) {
428 *buf = vf610_nfc_get_id(mtd, c);
431 *buf = vf610_nfc_get_status(mtd);
434 vf610_nfc_memcpy(buf, nfc->regs + NFC_MAIN_AREA(0) + c, len);
441 /* Write data to NFC buffers */
442 static void vf610_nfc_write_buf(struct mtd_info *mtd, const u_char *buf,
445 struct vf610_nfc *nfc = mtd_to_nfc(mtd);
446 uint c = nfc->column;
449 l = min((uint)len, mtd->writesize + mtd->oobsize - c);
451 vf610_nfc_memcpy(nfc->regs + NFC_MAIN_AREA(0) + c, buf, l);
454 /* Read byte from NFC buffers */
455 static u8 vf610_nfc_read_byte(struct mtd_info *mtd)
458 vf610_nfc_read_buf(mtd, &tmp, sizeof(tmp));
462 /* Read word from NFC buffers */
463 static u16 vf610_nfc_read_word(struct mtd_info *mtd)
466 vf610_nfc_read_buf(mtd, (u_char *)&tmp, sizeof(tmp));
470 /* If not provided, upper layers apply a fixed delay. */
471 static int vf610_nfc_dev_ready(struct mtd_info *mtd)
473 /* NFC handles R/B internally; always ready. */
478 * This function supports Vybrid only (MPC5125 would have full RB and four CS)
480 static void vf610_nfc_select_chip(struct mtd_info *mtd, int chip)
483 u32 tmp = vf610_nfc_read(mtd, NFC_ROW_ADDR);
484 tmp &= ~(ROW_ADDR_CHIP_SEL_RB_MASK | ROW_ADDR_CHIP_SEL_MASK);
485 tmp |= 1 << ROW_ADDR_CHIP_SEL_RB_SHIFT;
488 tmp |= 1 << ROW_ADDR_CHIP_SEL_SHIFT;
490 tmp |= 2 << ROW_ADDR_CHIP_SEL_SHIFT;
492 vf610_nfc_write(mtd, NFC_ROW_ADDR, tmp);
496 /* Count the number of 0's in buff upto max_bits */
497 static inline int count_written_bits(uint8_t *buff, int size, int max_bits)
499 uint32_t *buff32 = (uint32_t *)buff;
500 int k, written_bits = 0;
502 for (k = 0; k < (size / 4); k++) {
503 written_bits += hweight32(~buff32[k]);
504 if (written_bits > max_bits)
511 static inline int vf610_nfc_correct_data(struct mtd_info *mtd, u_char *dat)
513 struct vf610_nfc *nfc = mtd_to_nfc(mtd);
518 ecc_status = __raw_readb(nfc->regs + ECC_SRAM_ADDR * 8 + ECC_OFFSET);
519 ecc_count = ecc_status & ECC_ERR_COUNT;
520 if (!(ecc_status & ECC_STATUS_MASK))
523 /* If 'ecc_count' zero or less then buffer is all 0xff or erased. */
524 flip = count_written_bits(dat, nfc->chip.ecc.size, ecc_count);
527 if (flip > ecc_count && flip > (nfc->chip.ecc.strength / 2))
531 memset(dat, 0xff, nfc->chip.ecc.size);
536 static int vf610_nfc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
537 uint8_t *buf, int oob_required, int page)
539 int eccsize = chip->ecc.size;
544 vf610_nfc_read_buf(mtd, p, eccsize);
547 vf610_nfc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
549 stat = vf610_nfc_correct_data(mtd, p);
552 mtd->ecc_stats.failed++;
554 mtd->ecc_stats.corrected += stat;
560 * ECC will be calculated automatically
562 static int vf610_nfc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
563 const uint8_t *buf, int oob_required)
565 vf610_nfc_write_buf(mtd, buf, mtd->writesize);
567 vf610_nfc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
572 struct vf610_nfc_config {
578 static int vf610_nfc_nand_init(int devnum, void __iomem *addr)
580 struct mtd_info *mtd = &nand_info[devnum];
581 struct nand_chip *chip;
582 struct vf610_nfc *nfc;
584 struct vf610_nfc_config cfg = {
586 #ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT
594 nfc = malloc(sizeof(*nfc));
596 printf(KERN_ERR "%s: Memory exhausted!\n", __func__);
606 if (cfg.width == 16) {
607 chip->options |= NAND_BUSWIDTH_16;
608 vf610_nfc_set(mtd, NFC_FLASH_CONFIG, CONFIG_16BIT);
610 chip->options &= ~NAND_BUSWIDTH_16;
611 vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_16BIT);
614 /* Disable subpage writes as we do not provide ecc->hwctl */
615 chip->options |= NAND_NO_SUBPAGE_WRITE;
617 chip->dev_ready = vf610_nfc_dev_ready;
618 chip->cmdfunc = vf610_nfc_command;
619 chip->read_byte = vf610_nfc_read_byte;
620 chip->read_word = vf610_nfc_read_word;
621 chip->read_buf = vf610_nfc_read_buf;
622 chip->write_buf = vf610_nfc_write_buf;
623 chip->select_chip = vf610_nfc_select_chip;
625 /* Bad block options. */
627 chip->bbt_options = NAND_BBT_USE_FLASH | NAND_BBT_CREATE;
629 chip->bbt_td = &bbt_main_descr;
630 chip->bbt_md = &bbt_mirror_descr;
632 /* Set configuration register. */
633 vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_ADDR_AUTO_INCR_BIT);
634 vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_BUFNO_AUTO_INCR_BIT);
635 vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_BOOT_MODE_BIT);
636 vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_DMA_REQ_BIT);
637 vf610_nfc_set(mtd, NFC_FLASH_CONFIG, CONFIG_FAST_FLASH_BIT);
639 /* Enable Idle IRQ */
640 vf610_nfc_set(mtd, NFC_IRQ_STATUS, IDLE_EN_BIT);
643 vf610_nfc_set_field(mtd, NFC_FLASH_CONFIG, CONFIG_PAGE_CNT_MASK,
644 CONFIG_PAGE_CNT_SHIFT, 1);
646 /* Set ECC_STATUS offset */
647 vf610_nfc_set_field(mtd, NFC_FLASH_CONFIG,
648 CONFIG_ECC_SRAM_ADDR_MASK,
649 CONFIG_ECC_SRAM_ADDR_SHIFT, ECC_SRAM_ADDR);
651 /* first scan to find the device and get the page size */
652 if (nand_scan_ident(mtd, CONFIG_SYS_MAX_NAND_DEVICE, NULL)) {
657 chip->ecc.mode = NAND_ECC_SOFT; /* default */
659 /* Single buffer only, max 256 OOB minus ECC status */
660 if (mtd->writesize + mtd->oobsize > PAGE_2K + 256 - 8) {
661 dev_err(nfc->dev, "Unsupported flash size\n");
666 if (cfg.hardware_ecc) {
667 if (mtd->writesize != PAGE_2K && mtd->oobsize < 64) {
668 dev_err(nfc->dev, "Unsupported flash with hwecc\n");
673 chip->ecc.layout = &vf610_nfc_ecc45;
675 /* propagate ecc.layout to mtd_info */
676 mtd->ecclayout = chip->ecc.layout;
677 chip->ecc.read_page = vf610_nfc_read_page;
678 chip->ecc.write_page = vf610_nfc_write_page;
679 chip->ecc.mode = NAND_ECC_HW;
681 chip->ecc.bytes = 45;
682 chip->ecc.size = PAGE_2K;
683 chip->ecc.strength = 24;
685 /* Enable ECC_STATUS */
686 vf610_nfc_set(mtd, NFC_FLASH_CONFIG, CONFIG_ECC_SRAM_REQ_BIT);
689 /* second phase scan */
690 err = nand_scan_tail(mtd);
694 err = nand_register(devnum);
704 void board_nand_init(void)
706 int err = vf610_nfc_nand_init(0, (void __iomem *)CONFIG_SYS_NAND_BASE);
708 printf("VF610 NAND init failed (err %d)\n", err);