2 * Copyright 2009-2014 Freescale Semiconductor, Inc. and others
4 * Description: MPC5125, VF610, MCF54418 and Kinetis K70 Nand driver.
5 * Ported to U-Boot by Stefan Agner
6 * Based on RFC driver posted on Kernel Mailing list by Bill Pringlemeir
7 * Jason ported to M54418TWR and MVFA5.
8 * Authors: Stefan Agner <stefan.agner@toradex.com>
9 * Bill Pringlemeir <bpringlemeir@nbsps.com>
10 * Shaohui Xie <b21989@freescale.com>
11 * Jason Jin <Jason.jin@freescale.com>
13 * Based on original driver mpc5121_nfc.c.
15 * This is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
21 * - Untested on MPC5125 and M54418.
24 * - Only 2K page w. 64+OOB and hardware ECC.
30 #include <linux/mtd/mtd.h>
31 #include <linux/mtd/nand.h>
32 #include <linux/mtd/partitions.h>
38 /* Register Offsets */
39 #define NFC_FLASH_CMD1 0x3F00
40 #define NFC_FLASH_CMD2 0x3F04
41 #define NFC_COL_ADDR 0x3F08
42 #define NFC_ROW_ADDR 0x3F0c
43 #define NFC_ROW_ADDR_INC 0x3F14
44 #define NFC_FLASH_STATUS1 0x3F18
45 #define NFC_FLASH_STATUS2 0x3F1c
46 #define NFC_CACHE_SWAP 0x3F28
47 #define NFC_SECTOR_SIZE 0x3F2c
48 #define NFC_FLASH_CONFIG 0x3F30
49 #define NFC_IRQ_STATUS 0x3F38
51 /* Addresses for NFC MAIN RAM BUFFER areas */
52 #define NFC_MAIN_AREA(n) ((n) * 0x1000)
54 #define PAGE_2K 0x0800
58 * NFC_CMD2[CODE] values. See section:
59 * - 31.4.7 Flash Command Code Description, Vybrid manual
60 * - 23.8.6 Flash Command Sequencer, MPC5125 manual
62 * Briefly these are bitmasks of controller cycles.
64 #define READ_PAGE_CMD_CODE 0x7EE0
65 #define PROGRAM_PAGE_CMD_CODE 0x7FC0
66 #define ERASE_CMD_CODE 0x4EC0
67 #define READ_ID_CMD_CODE 0x4804
68 #define RESET_CMD_CODE 0x4040
69 #define STATUS_READ_CMD_CODE 0x4068
71 /* NFC ECC mode define */
76 /*** Register Mask and bit definitions */
78 /* NFC_FLASH_CMD1 Field */
79 #define CMD_BYTE2_MASK 0xFF000000
80 #define CMD_BYTE2_SHIFT 24
82 /* NFC_FLASH_CM2 Field */
83 #define CMD_BYTE1_MASK 0xFF000000
84 #define CMD_BYTE1_SHIFT 24
85 #define CMD_CODE_MASK 0x00FFFF00
86 #define CMD_CODE_SHIFT 8
87 #define BUFNO_MASK 0x00000006
89 #define START_BIT (1<<0)
91 /* NFC_COL_ADDR Field */
92 #define COL_ADDR_MASK 0x0000FFFF
93 #define COL_ADDR_SHIFT 0
95 /* NFC_ROW_ADDR Field */
96 #define ROW_ADDR_MASK 0x00FFFFFF
97 #define ROW_ADDR_SHIFT 0
98 #define ROW_ADDR_CHIP_SEL_RB_MASK 0xF0000000
99 #define ROW_ADDR_CHIP_SEL_RB_SHIFT 28
100 #define ROW_ADDR_CHIP_SEL_MASK 0x0F000000
101 #define ROW_ADDR_CHIP_SEL_SHIFT 24
103 /* NFC_FLASH_STATUS2 Field */
104 #define STATUS_BYTE1_MASK 0x000000FF
106 /* NFC_FLASH_CONFIG Field */
107 #define CONFIG_ECC_SRAM_ADDR_MASK 0x7FC00000
108 #define CONFIG_ECC_SRAM_ADDR_SHIFT 22
109 #define CONFIG_ECC_SRAM_REQ_BIT (1<<21)
110 #define CONFIG_DMA_REQ_BIT (1<<20)
111 #define CONFIG_ECC_MODE_MASK 0x000E0000
112 #define CONFIG_ECC_MODE_SHIFT 17
113 #define CONFIG_FAST_FLASH_BIT (1<<16)
114 #define CONFIG_16BIT (1<<7)
115 #define CONFIG_BOOT_MODE_BIT (1<<6)
116 #define CONFIG_ADDR_AUTO_INCR_BIT (1<<5)
117 #define CONFIG_BUFNO_AUTO_INCR_BIT (1<<4)
118 #define CONFIG_PAGE_CNT_MASK 0xF
119 #define CONFIG_PAGE_CNT_SHIFT 0
121 /* NFC_IRQ_STATUS Field */
122 #define IDLE_IRQ_BIT (1<<29)
123 #define IDLE_EN_BIT (1<<20)
124 #define CMD_DONE_CLEAR_BIT (1<<18)
125 #define IDLE_CLEAR_BIT (1<<17)
127 #define NFC_TIMEOUT (1000)
129 /* ECC status placed at end of buffers. */
130 #define ECC_SRAM_ADDR ((PAGE_2K+256-8) >> 3)
131 #define ECC_STATUS_MASK 0x80
132 #define ECC_ERR_COUNT 0x3F
135 * ECC status is stored at NFC_CFG[ECCADD] +4 for little-endian
136 * and +7 for big-endian SOC.
145 struct mtd_info *mtd;
146 struct nand_chip chip;
149 /* Status and ID are in alternate locations. */
152 #define ALT_BUF_STAT 2
156 #define mtd_to_nfc(_mtd) \
157 (struct vf610_nfc *)((struct nand_chip *)_mtd->priv)->priv
159 #if defined(CONFIG_SYS_NAND_VF610_NFC_45_ECC_BYTES)
160 #define ECC_HW_MODE ECC_45_BYTE
162 static struct nand_ecclayout vf610_nfc_ecc = {
164 .eccpos = {19, 20, 21, 22, 23,
165 24, 25, 26, 27, 28, 29, 30, 31,
166 32, 33, 34, 35, 36, 37, 38, 39,
167 40, 41, 42, 43, 44, 45, 46, 47,
168 48, 49, 50, 51, 52, 53, 54, 55,
169 56, 57, 58, 59, 60, 61, 62, 63},
174 #elif defined(CONFIG_SYS_NAND_VF610_NFC_60_ECC_BYTES)
175 #define ECC_HW_MODE ECC_60_BYTE
177 static struct nand_ecclayout vf610_nfc_ecc = {
179 .eccpos = { 4, 5, 6, 7, 8, 9, 10, 11,
180 12, 13, 14, 15, 16, 17, 18, 19,
181 20, 21, 22, 23, 24, 25, 26, 27,
182 28, 29, 30, 31, 32, 33, 34, 35,
183 36, 37, 38, 39, 40, 41, 42, 43,
184 44, 45, 46, 47, 48, 49, 50, 51,
185 52, 53, 54, 55, 56, 57, 58, 59,
193 static inline u32 vf610_nfc_read(struct mtd_info *mtd, uint reg)
195 struct vf610_nfc *nfc = mtd_to_nfc(mtd);
197 return readl(nfc->regs + reg);
200 static inline void vf610_nfc_write(struct mtd_info *mtd, uint reg, u32 val)
202 struct vf610_nfc *nfc = mtd_to_nfc(mtd);
204 writel(val, nfc->regs + reg);
207 static inline void vf610_nfc_set(struct mtd_info *mtd, uint reg, u32 bits)
209 vf610_nfc_write(mtd, reg, vf610_nfc_read(mtd, reg) | bits);
212 static inline void vf610_nfc_clear(struct mtd_info *mtd, uint reg, u32 bits)
214 vf610_nfc_write(mtd, reg, vf610_nfc_read(mtd, reg) & ~bits);
217 static inline void vf610_nfc_set_field(struct mtd_info *mtd, u32 reg,
218 u32 mask, u32 shift, u32 val)
220 vf610_nfc_write(mtd, reg,
221 (vf610_nfc_read(mtd, reg) & (~mask)) | val << shift);
224 static inline void vf610_nfc_memcpy(void *dst, const void *src, size_t n)
227 * Use this accessor for the interal SRAM buffers. On ARM we can
228 * treat the SRAM buffer as if its memory, hence use memcpy
233 /* Clear flags for upcoming command */
234 static inline void vf610_nfc_clear_status(void __iomem *regbase)
236 void __iomem *reg = regbase + NFC_IRQ_STATUS;
237 u32 tmp = __raw_readl(reg);
238 tmp |= CMD_DONE_CLEAR_BIT | IDLE_CLEAR_BIT;
239 __raw_writel(tmp, reg);
242 /* Wait for complete operation */
243 static inline void vf610_nfc_done(struct mtd_info *mtd)
245 struct vf610_nfc *nfc = mtd_to_nfc(mtd);
249 * Barrier is needed after this write. This write need
250 * to be done before reading the next register the first
252 * vf610_nfc_set implicates such a barrier by using writel
253 * to write to the register.
255 vf610_nfc_set(mtd, NFC_FLASH_CMD2, START_BIT);
257 start = get_timer(0);
259 while (!(vf610_nfc_read(mtd, NFC_IRQ_STATUS) & IDLE_IRQ_BIT)) {
260 if (get_timer(start) > NFC_TIMEOUT) {
261 printf("Timeout while waiting for !BUSY.\n");
265 vf610_nfc_clear_status(nfc->regs);
268 static u8 vf610_nfc_get_id(struct mtd_info *mtd, int col)
273 flash_id = vf610_nfc_read(mtd, NFC_FLASH_STATUS1);
274 return (flash_id >> (3-col)*8) & 0xff;
276 flash_id = vf610_nfc_read(mtd, NFC_FLASH_STATUS2);
277 return flash_id >> 24;
281 static u8 vf610_nfc_get_status(struct mtd_info *mtd)
283 return vf610_nfc_read(mtd, NFC_FLASH_STATUS2) & STATUS_BYTE1_MASK;
287 static void vf610_nfc_send_command(void __iomem *regbase, u32 cmd_byte1,
290 void __iomem *reg = regbase + NFC_FLASH_CMD2;
292 vf610_nfc_clear_status(regbase);
294 tmp = __raw_readl(reg);
295 tmp &= ~(CMD_BYTE1_MASK | CMD_CODE_MASK | BUFNO_MASK);
296 tmp |= cmd_byte1 << CMD_BYTE1_SHIFT;
297 tmp |= cmd_code << CMD_CODE_SHIFT;
298 __raw_writel(tmp, reg);
302 static void vf610_nfc_send_commands(void __iomem *regbase, u32 cmd_byte1,
303 u32 cmd_byte2, u32 cmd_code)
305 void __iomem *reg = regbase + NFC_FLASH_CMD1;
307 vf610_nfc_send_command(regbase, cmd_byte1, cmd_code);
309 tmp = __raw_readl(reg);
310 tmp &= ~CMD_BYTE2_MASK;
311 tmp |= cmd_byte2 << CMD_BYTE2_SHIFT;
312 __raw_writel(tmp, reg);
315 static void vf610_nfc_addr_cycle(struct mtd_info *mtd, int column, int page)
318 struct vf610_nfc *nfc = mtd_to_nfc(mtd);
319 if (nfc->chip.options & NAND_BUSWIDTH_16)
321 vf610_nfc_set_field(mtd, NFC_COL_ADDR, COL_ADDR_MASK,
322 COL_ADDR_SHIFT, column);
325 vf610_nfc_set_field(mtd, NFC_ROW_ADDR, ROW_ADDR_MASK,
326 ROW_ADDR_SHIFT, page);
329 static inline void vf610_nfc_ecc_mode(struct mtd_info *mtd, int ecc_mode)
331 vf610_nfc_set_field(mtd, NFC_FLASH_CONFIG,
332 CONFIG_ECC_MODE_MASK,
333 CONFIG_ECC_MODE_SHIFT, ecc_mode);
336 static inline void vf610_nfc_transfer_size(void __iomem *regbase, int size)
338 __raw_writel(size, regbase + NFC_SECTOR_SIZE);
341 /* Send command to NAND chip */
342 static void vf610_nfc_command(struct mtd_info *mtd, unsigned command,
343 int column, int page)
345 struct vf610_nfc *nfc = mtd_to_nfc(mtd);
346 int page_sz = nfc->chip.options & NAND_BUSWIDTH_16 ? 1 : 0;
348 nfc->column = max(column, 0);
353 /* Use valid column/page from preread... */
354 vf610_nfc_addr_cycle(mtd, column, page);
356 * SEQIN => data => PAGEPROG sequence is done by the controller
357 * hence we do not need to issue the command here...
360 case NAND_CMD_PAGEPROG:
361 page_sz += mtd->writesize + mtd->oobsize;
362 vf610_nfc_transfer_size(nfc->regs, page_sz);
363 vf610_nfc_send_commands(nfc->regs, NAND_CMD_SEQIN,
364 command, PROGRAM_PAGE_CMD_CODE);
365 vf610_nfc_ecc_mode(mtd, ECC_HW_MODE);
369 vf610_nfc_transfer_size(nfc->regs, 0);
370 vf610_nfc_send_command(nfc->regs, command, RESET_CMD_CODE);
373 case NAND_CMD_READOOB:
374 page_sz += mtd->oobsize;
375 column = mtd->writesize;
376 vf610_nfc_transfer_size(nfc->regs, page_sz);
377 vf610_nfc_send_commands(nfc->regs, NAND_CMD_READ0,
378 NAND_CMD_READSTART, READ_PAGE_CMD_CODE);
379 vf610_nfc_addr_cycle(mtd, column, page);
380 vf610_nfc_ecc_mode(mtd, ECC_BYPASS);
384 page_sz += mtd->writesize + mtd->oobsize;
386 vf610_nfc_transfer_size(nfc->regs, page_sz);
387 vf610_nfc_send_commands(nfc->regs, NAND_CMD_READ0,
388 NAND_CMD_READSTART, READ_PAGE_CMD_CODE);
389 vf610_nfc_addr_cycle(mtd, column, page);
390 vf610_nfc_ecc_mode(mtd, ECC_HW_MODE);
393 case NAND_CMD_ERASE1:
394 vf610_nfc_transfer_size(nfc->regs, 0);
395 vf610_nfc_send_commands(nfc->regs, command,
396 NAND_CMD_ERASE2, ERASE_CMD_CODE);
397 vf610_nfc_addr_cycle(mtd, column, page);
400 case NAND_CMD_READID:
401 nfc->alt_buf = ALT_BUF_ID;
402 vf610_nfc_transfer_size(nfc->regs, 0);
403 vf610_nfc_send_command(nfc->regs, command, READ_ID_CMD_CODE);
406 case NAND_CMD_STATUS:
407 nfc->alt_buf = ALT_BUF_STAT;
408 vf610_nfc_transfer_size(nfc->regs, 0);
409 vf610_nfc_send_command(nfc->regs, command,
410 STATUS_READ_CMD_CODE);
419 /* Read data from NFC buffers */
420 static void vf610_nfc_read_buf(struct mtd_info *mtd, u_char *buf, int len)
422 struct vf610_nfc *nfc = mtd_to_nfc(mtd);
423 uint c = nfc->column;
425 switch (nfc->alt_buf) {
427 *buf = vf610_nfc_get_id(mtd, c);
430 *buf = vf610_nfc_get_status(mtd);
433 vf610_nfc_memcpy(buf, nfc->regs + NFC_MAIN_AREA(0) + c, len);
440 /* Write data to NFC buffers */
441 static void vf610_nfc_write_buf(struct mtd_info *mtd, const u_char *buf,
444 struct vf610_nfc *nfc = mtd_to_nfc(mtd);
445 uint c = nfc->column;
448 l = min((uint)len, mtd->writesize + mtd->oobsize - c);
450 vf610_nfc_memcpy(nfc->regs + NFC_MAIN_AREA(0) + c, buf, l);
453 /* Read byte from NFC buffers */
454 static u8 vf610_nfc_read_byte(struct mtd_info *mtd)
457 vf610_nfc_read_buf(mtd, &tmp, sizeof(tmp));
461 /* Read word from NFC buffers */
462 static u16 vf610_nfc_read_word(struct mtd_info *mtd)
465 vf610_nfc_read_buf(mtd, (u_char *)&tmp, sizeof(tmp));
469 /* If not provided, upper layers apply a fixed delay. */
470 static int vf610_nfc_dev_ready(struct mtd_info *mtd)
472 /* NFC handles R/B internally; always ready. */
477 * This function supports Vybrid only (MPC5125 would have full RB and four CS)
479 static void vf610_nfc_select_chip(struct mtd_info *mtd, int chip)
482 u32 tmp = vf610_nfc_read(mtd, NFC_ROW_ADDR);
483 tmp &= ~(ROW_ADDR_CHIP_SEL_RB_MASK | ROW_ADDR_CHIP_SEL_MASK);
484 tmp |= 1 << ROW_ADDR_CHIP_SEL_RB_SHIFT;
487 tmp |= 1 << ROW_ADDR_CHIP_SEL_SHIFT;
489 tmp |= 2 << ROW_ADDR_CHIP_SEL_SHIFT;
491 vf610_nfc_write(mtd, NFC_ROW_ADDR, tmp);
495 /* Count the number of 0's in buff upto max_bits */
496 static inline int count_written_bits(uint8_t *buff, int size, int max_bits)
498 uint32_t *buff32 = (uint32_t *)buff;
499 int k, written_bits = 0;
501 for (k = 0; k < (size / 4); k++) {
502 written_bits += hweight32(~buff32[k]);
503 if (written_bits > max_bits)
510 static inline int vf610_nfc_correct_data(struct mtd_info *mtd, u_char *dat)
512 struct vf610_nfc *nfc = mtd_to_nfc(mtd);
517 ecc_status = __raw_readb(nfc->regs + ECC_SRAM_ADDR * 8 + ECC_OFFSET);
518 ecc_count = ecc_status & ECC_ERR_COUNT;
519 if (!(ecc_status & ECC_STATUS_MASK))
522 /* If 'ecc_count' zero or less then buffer is all 0xff or erased. */
523 flip = count_written_bits(dat, nfc->chip.ecc.size, ecc_count);
526 if (flip > ecc_count && flip > (nfc->chip.ecc.strength / 2))
530 memset(dat, 0xff, nfc->chip.ecc.size);
535 static int vf610_nfc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
536 uint8_t *buf, int oob_required, int page)
538 int eccsize = chip->ecc.size;
543 vf610_nfc_read_buf(mtd, p, eccsize);
546 vf610_nfc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
548 stat = vf610_nfc_correct_data(mtd, p);
551 mtd->ecc_stats.failed++;
553 mtd->ecc_stats.corrected += stat;
559 * ECC will be calculated automatically
561 static int vf610_nfc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
562 const uint8_t *buf, int oob_required)
564 vf610_nfc_write_buf(mtd, buf, mtd->writesize);
566 vf610_nfc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
571 struct vf610_nfc_config {
577 static int vf610_nfc_nand_init(int devnum, void __iomem *addr)
579 struct mtd_info *mtd = &nand_info[devnum];
580 struct nand_chip *chip;
581 struct vf610_nfc *nfc;
583 struct vf610_nfc_config cfg = {
585 #ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT
593 nfc = malloc(sizeof(*nfc));
595 printf(KERN_ERR "%s: Memory exhausted!\n", __func__);
605 if (cfg.width == 16) {
606 chip->options |= NAND_BUSWIDTH_16;
607 vf610_nfc_set(mtd, NFC_FLASH_CONFIG, CONFIG_16BIT);
609 chip->options &= ~NAND_BUSWIDTH_16;
610 vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_16BIT);
613 /* Disable subpage writes as we do not provide ecc->hwctl */
614 chip->options |= NAND_NO_SUBPAGE_WRITE;
616 chip->dev_ready = vf610_nfc_dev_ready;
617 chip->cmdfunc = vf610_nfc_command;
618 chip->read_byte = vf610_nfc_read_byte;
619 chip->read_word = vf610_nfc_read_word;
620 chip->read_buf = vf610_nfc_read_buf;
621 chip->write_buf = vf610_nfc_write_buf;
622 chip->select_chip = vf610_nfc_select_chip;
624 /* Bad block options. */
626 chip->bbt_options = NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB |
629 /* Set configuration register. */
630 vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_ADDR_AUTO_INCR_BIT);
631 vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_BUFNO_AUTO_INCR_BIT);
632 vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_BOOT_MODE_BIT);
633 vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_DMA_REQ_BIT);
634 vf610_nfc_set(mtd, NFC_FLASH_CONFIG, CONFIG_FAST_FLASH_BIT);
636 /* Enable Idle IRQ */
637 vf610_nfc_set(mtd, NFC_IRQ_STATUS, IDLE_EN_BIT);
640 vf610_nfc_set_field(mtd, NFC_FLASH_CONFIG, CONFIG_PAGE_CNT_MASK,
641 CONFIG_PAGE_CNT_SHIFT, 1);
643 /* Set ECC_STATUS offset */
644 vf610_nfc_set_field(mtd, NFC_FLASH_CONFIG,
645 CONFIG_ECC_SRAM_ADDR_MASK,
646 CONFIG_ECC_SRAM_ADDR_SHIFT, ECC_SRAM_ADDR);
648 /* first scan to find the device and get the page size */
649 if (nand_scan_ident(mtd, CONFIG_SYS_MAX_NAND_DEVICE, NULL)) {
654 chip->ecc.mode = NAND_ECC_SOFT; /* default */
656 /* Single buffer only, max 256 OOB minus ECC status */
657 if (mtd->writesize + mtd->oobsize > PAGE_2K + 256 - 8) {
658 dev_err(nfc->dev, "Unsupported flash size\n");
663 if (cfg.hardware_ecc) {
664 if (mtd->writesize != PAGE_2K && mtd->oobsize < 64) {
665 dev_err(nfc->dev, "Unsupported flash with hwecc\n");
670 /* Current HW ECC layouts only use 64 bytes of OOB */
671 if (mtd->oobsize > 64)
674 /* propagate ecc.layout to mtd_info */
675 mtd->ecclayout = chip->ecc.layout;
676 chip->ecc.read_page = vf610_nfc_read_page;
677 chip->ecc.write_page = vf610_nfc_write_page;
678 chip->ecc.mode = NAND_ECC_HW;
680 chip->ecc.size = PAGE_2K;
681 chip->ecc.layout = &vf610_nfc_ecc;
682 #if defined(CONFIG_SYS_NAND_VF610_NFC_45_ECC_BYTES)
683 chip->ecc.strength = 24;
684 chip->ecc.bytes = 45;
685 #elif defined(CONFIG_SYS_NAND_VF610_NFC_60_ECC_BYTES)
686 chip->ecc.strength = 32;
687 chip->ecc.bytes = 60;
690 /* Enable ECC_STATUS */
691 vf610_nfc_set(mtd, NFC_FLASH_CONFIG, CONFIG_ECC_SRAM_REQ_BIT);
694 /* second phase scan */
695 err = nand_scan_tail(mtd);
699 err = nand_register(devnum);
709 void board_nand_init(void)
711 int err = vf610_nfc_nand_init(0, (void __iomem *)CONFIG_SYS_NAND_BASE);
713 printf("VF610 NAND init failed (err %d)\n", err);