2 * Copyright 2009-2015 Freescale Semiconductor, Inc. and others
4 * Description: MPC5125, VF610, MCF54418 and Kinetis K70 Nand driver.
5 * Ported to U-Boot by Stefan Agner
6 * Based on RFC driver posted on Kernel Mailing list by Bill Pringlemeir
7 * Jason ported to M54418TWR and MVFA5.
8 * Authors: Stefan Agner <stefan.agner@toradex.com>
9 * Bill Pringlemeir <bpringlemeir@nbsps.com>
10 * Shaohui Xie <b21989@freescale.com>
11 * Jason Jin <Jason.jin@freescale.com>
13 * Based on original driver mpc5121_nfc.c.
15 * This is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
21 * - Untested on MPC5125 and M54418.
22 * - DMA and pipelining not used.
24 * - HW ECC: Only 2K page with 64+ OOB.
25 * - HW ECC: Only 24 and 32-bit error correction implemented.
31 #include <linux/mtd/mtd.h>
32 #include <linux/mtd/nand.h>
33 #include <linux/mtd/partitions.h>
39 /* Register Offsets */
40 #define NFC_FLASH_CMD1 0x3F00
41 #define NFC_FLASH_CMD2 0x3F04
42 #define NFC_COL_ADDR 0x3F08
43 #define NFC_ROW_ADDR 0x3F0c
44 #define NFC_ROW_ADDR_INC 0x3F14
45 #define NFC_FLASH_STATUS1 0x3F18
46 #define NFC_FLASH_STATUS2 0x3F1c
47 #define NFC_CACHE_SWAP 0x3F28
48 #define NFC_SECTOR_SIZE 0x3F2c
49 #define NFC_FLASH_CONFIG 0x3F30
50 #define NFC_IRQ_STATUS 0x3F38
52 /* Addresses for NFC MAIN RAM BUFFER areas */
53 #define NFC_MAIN_AREA(n) ((n) * 0x1000)
55 #define PAGE_2K 0x0800
57 #define OOB_MAX 0x0100
60 * NFC_CMD2[CODE] values. See section:
61 * - 31.4.7 Flash Command Code Description, Vybrid manual
62 * - 23.8.6 Flash Command Sequencer, MPC5125 manual
64 * Briefly these are bitmasks of controller cycles.
66 #define READ_PAGE_CMD_CODE 0x7EE0
67 #define READ_ONFI_PARAM_CMD_CODE 0x4860
68 #define PROGRAM_PAGE_CMD_CODE 0x7FC0
69 #define ERASE_CMD_CODE 0x4EC0
70 #define READ_ID_CMD_CODE 0x4804
71 #define RESET_CMD_CODE 0x4040
72 #define STATUS_READ_CMD_CODE 0x4068
74 /* NFC ECC mode define */
79 /*** Register Mask and bit definitions */
81 /* NFC_FLASH_CMD1 Field */
82 #define CMD_BYTE2_MASK 0xFF000000
83 #define CMD_BYTE2_SHIFT 24
85 /* NFC_FLASH_CM2 Field */
86 #define CMD_BYTE1_MASK 0xFF000000
87 #define CMD_BYTE1_SHIFT 24
88 #define CMD_CODE_MASK 0x00FFFF00
89 #define CMD_CODE_SHIFT 8
90 #define BUFNO_MASK 0x00000006
92 #define START_BIT (1<<0)
94 /* NFC_COL_ADDR Field */
95 #define COL_ADDR_MASK 0x0000FFFF
96 #define COL_ADDR_SHIFT 0
98 /* NFC_ROW_ADDR Field */
99 #define ROW_ADDR_MASK 0x00FFFFFF
100 #define ROW_ADDR_SHIFT 0
101 #define ROW_ADDR_CHIP_SEL_RB_MASK 0xF0000000
102 #define ROW_ADDR_CHIP_SEL_RB_SHIFT 28
103 #define ROW_ADDR_CHIP_SEL_MASK 0x0F000000
104 #define ROW_ADDR_CHIP_SEL_SHIFT 24
106 /* NFC_FLASH_STATUS2 Field */
107 #define STATUS_BYTE1_MASK 0x000000FF
109 /* NFC_FLASH_CONFIG Field */
110 #define CONFIG_ECC_SRAM_ADDR_MASK 0x7FC00000
111 #define CONFIG_ECC_SRAM_ADDR_SHIFT 22
112 #define CONFIG_ECC_SRAM_REQ_BIT (1<<21)
113 #define CONFIG_DMA_REQ_BIT (1<<20)
114 #define CONFIG_ECC_MODE_MASK 0x000E0000
115 #define CONFIG_ECC_MODE_SHIFT 17
116 #define CONFIG_FAST_FLASH_BIT (1<<16)
117 #define CONFIG_16BIT (1<<7)
118 #define CONFIG_BOOT_MODE_BIT (1<<6)
119 #define CONFIG_ADDR_AUTO_INCR_BIT (1<<5)
120 #define CONFIG_BUFNO_AUTO_INCR_BIT (1<<4)
121 #define CONFIG_PAGE_CNT_MASK 0xF
122 #define CONFIG_PAGE_CNT_SHIFT 0
124 /* NFC_IRQ_STATUS Field */
125 #define IDLE_IRQ_BIT (1<<29)
126 #define IDLE_EN_BIT (1<<20)
127 #define CMD_DONE_CLEAR_BIT (1<<18)
128 #define IDLE_CLEAR_BIT (1<<17)
130 #define NFC_TIMEOUT (1000)
133 * ECC status - seems to consume 8 bytes (double word). The documented
134 * status byte is located in the lowest byte of the second word (which is
135 * the 4th or 7th byte depending on endianness).
136 * Calculate an offset to store the ECC status at the end of the buffer.
138 #define ECC_SRAM_ADDR (PAGE_2K + OOB_MAX - 8)
140 #define ECC_STATUS 0x4
141 #define ECC_STATUS_MASK 0x80
142 #define ECC_STATUS_ERR_COUNT 0x3F
144 enum vf610_nfc_alt_buf {
152 struct mtd_info *mtd;
153 struct nand_chip chip;
157 /* Status and ID are in alternate locations. */
158 enum vf610_nfc_alt_buf alt_buf;
161 #define mtd_to_nfc(_mtd) \
162 (struct vf610_nfc *)((struct nand_chip *)_mtd->priv)->priv
164 #if defined(CONFIG_SYS_NAND_VF610_NFC_45_ECC_BYTES)
165 #define ECC_HW_MODE ECC_45_BYTE
167 static struct nand_ecclayout vf610_nfc_ecc = {
169 .eccpos = {19, 20, 21, 22, 23,
170 24, 25, 26, 27, 28, 29, 30, 31,
171 32, 33, 34, 35, 36, 37, 38, 39,
172 40, 41, 42, 43, 44, 45, 46, 47,
173 48, 49, 50, 51, 52, 53, 54, 55,
174 56, 57, 58, 59, 60, 61, 62, 63},
179 #elif defined(CONFIG_SYS_NAND_VF610_NFC_60_ECC_BYTES)
180 #define ECC_HW_MODE ECC_60_BYTE
182 static struct nand_ecclayout vf610_nfc_ecc = {
184 .eccpos = { 4, 5, 6, 7, 8, 9, 10, 11,
185 12, 13, 14, 15, 16, 17, 18, 19,
186 20, 21, 22, 23, 24, 25, 26, 27,
187 28, 29, 30, 31, 32, 33, 34, 35,
188 36, 37, 38, 39, 40, 41, 42, 43,
189 44, 45, 46, 47, 48, 49, 50, 51,
190 52, 53, 54, 55, 56, 57, 58, 59,
198 static inline u32 vf610_nfc_read(struct mtd_info *mtd, uint reg)
200 struct vf610_nfc *nfc = mtd_to_nfc(mtd);
202 return readl(nfc->regs + reg);
205 static inline void vf610_nfc_write(struct mtd_info *mtd, uint reg, u32 val)
207 struct vf610_nfc *nfc = mtd_to_nfc(mtd);
209 writel(val, nfc->regs + reg);
212 static inline void vf610_nfc_set(struct mtd_info *mtd, uint reg, u32 bits)
214 vf610_nfc_write(mtd, reg, vf610_nfc_read(mtd, reg) | bits);
217 static inline void vf610_nfc_clear(struct mtd_info *mtd, uint reg, u32 bits)
219 vf610_nfc_write(mtd, reg, vf610_nfc_read(mtd, reg) & ~bits);
222 static inline void vf610_nfc_set_field(struct mtd_info *mtd, u32 reg,
223 u32 mask, u32 shift, u32 val)
225 vf610_nfc_write(mtd, reg,
226 (vf610_nfc_read(mtd, reg) & (~mask)) | val << shift);
229 static inline void vf610_nfc_memcpy(void *dst, const void *src, size_t n)
232 * Use this accessor for the internal SRAM buffers. On the ARM
233 * Freescale Vybrid SoC it's known that the driver can treat
234 * the SRAM buffer as if it's memory. Other platform might need
235 * to treat the buffers differently.
237 * For the time being, use memcpy
242 /* Clear flags for upcoming command */
243 static inline void vf610_nfc_clear_status(void __iomem *regbase)
245 void __iomem *reg = regbase + NFC_IRQ_STATUS;
246 u32 tmp = __raw_readl(reg);
247 tmp |= CMD_DONE_CLEAR_BIT | IDLE_CLEAR_BIT;
248 __raw_writel(tmp, reg);
251 /* Wait for complete operation */
252 static void vf610_nfc_done(struct mtd_info *mtd)
254 struct vf610_nfc *nfc = mtd_to_nfc(mtd);
258 * Barrier is needed after this write. This write need
259 * to be done before reading the next register the first
261 * vf610_nfc_set implicates such a barrier by using writel
262 * to write to the register.
264 vf610_nfc_set(mtd, NFC_FLASH_CMD2, START_BIT);
266 start = get_timer(0);
268 while (!(vf610_nfc_read(mtd, NFC_IRQ_STATUS) & IDLE_IRQ_BIT)) {
269 if (get_timer(start) > NFC_TIMEOUT) {
270 printf("Timeout while waiting for IDLE.\n");
274 vf610_nfc_clear_status(nfc->regs);
277 static u8 vf610_nfc_get_id(struct mtd_info *mtd, int col)
282 flash_id = vf610_nfc_read(mtd, NFC_FLASH_STATUS1);
283 flash_id >>= (3 - col) * 8;
285 flash_id = vf610_nfc_read(mtd, NFC_FLASH_STATUS2);
289 return flash_id & 0xff;
292 static u8 vf610_nfc_get_status(struct mtd_info *mtd)
294 return vf610_nfc_read(mtd, NFC_FLASH_STATUS2) & STATUS_BYTE1_MASK;
298 static void vf610_nfc_send_command(void __iomem *regbase, u32 cmd_byte1,
301 void __iomem *reg = regbase + NFC_FLASH_CMD2;
303 vf610_nfc_clear_status(regbase);
305 tmp = __raw_readl(reg);
306 tmp &= ~(CMD_BYTE1_MASK | CMD_CODE_MASK | BUFNO_MASK);
307 tmp |= cmd_byte1 << CMD_BYTE1_SHIFT;
308 tmp |= cmd_code << CMD_CODE_SHIFT;
309 __raw_writel(tmp, reg);
313 static void vf610_nfc_send_commands(void __iomem *regbase, u32 cmd_byte1,
314 u32 cmd_byte2, u32 cmd_code)
316 void __iomem *reg = regbase + NFC_FLASH_CMD1;
318 vf610_nfc_send_command(regbase, cmd_byte1, cmd_code);
320 tmp = __raw_readl(reg);
321 tmp &= ~CMD_BYTE2_MASK;
322 tmp |= cmd_byte2 << CMD_BYTE2_SHIFT;
323 __raw_writel(tmp, reg);
326 static void vf610_nfc_addr_cycle(struct mtd_info *mtd, int column, int page)
329 struct vf610_nfc *nfc = mtd_to_nfc(mtd);
330 if (nfc->chip.options & NAND_BUSWIDTH_16)
332 vf610_nfc_set_field(mtd, NFC_COL_ADDR, COL_ADDR_MASK,
333 COL_ADDR_SHIFT, column);
336 vf610_nfc_set_field(mtd, NFC_ROW_ADDR, ROW_ADDR_MASK,
337 ROW_ADDR_SHIFT, page);
340 static inline void vf610_nfc_ecc_mode(struct mtd_info *mtd, int ecc_mode)
342 vf610_nfc_set_field(mtd, NFC_FLASH_CONFIG,
343 CONFIG_ECC_MODE_MASK,
344 CONFIG_ECC_MODE_SHIFT, ecc_mode);
347 static inline void vf610_nfc_transfer_size(void __iomem *regbase, int size)
349 __raw_writel(size, regbase + NFC_SECTOR_SIZE);
352 /* Send command to NAND chip */
353 static void vf610_nfc_command(struct mtd_info *mtd, unsigned command,
354 int column, int page)
356 struct vf610_nfc *nfc = mtd_to_nfc(mtd);
357 int trfr_sz = nfc->chip.options & NAND_BUSWIDTH_16 ? 1 : 0;
359 nfc->buf_offset = max(column, 0);
360 nfc->alt_buf = ALT_BUF_DATA;
364 /* Use valid column/page from preread... */
365 vf610_nfc_addr_cycle(mtd, column, page);
369 * SEQIN => data => PAGEPROG sequence is done by the controller
370 * hence we do not need to issue the command here...
373 case NAND_CMD_PAGEPROG:
374 trfr_sz += nfc->write_sz;
375 vf610_nfc_ecc_mode(mtd, ECC_HW_MODE);
376 vf610_nfc_transfer_size(nfc->regs, trfr_sz);
377 vf610_nfc_send_commands(nfc->regs, NAND_CMD_SEQIN,
378 command, PROGRAM_PAGE_CMD_CODE);
382 vf610_nfc_transfer_size(nfc->regs, 0);
383 vf610_nfc_send_command(nfc->regs, command, RESET_CMD_CODE);
386 case NAND_CMD_READOOB:
387 trfr_sz += mtd->oobsize;
388 column = mtd->writesize;
389 vf610_nfc_transfer_size(nfc->regs, trfr_sz);
390 vf610_nfc_send_commands(nfc->regs, NAND_CMD_READ0,
391 NAND_CMD_READSTART, READ_PAGE_CMD_CODE);
392 vf610_nfc_addr_cycle(mtd, column, page);
393 vf610_nfc_ecc_mode(mtd, ECC_BYPASS);
397 trfr_sz += mtd->writesize + mtd->oobsize;
398 vf610_nfc_transfer_size(nfc->regs, trfr_sz);
399 vf610_nfc_ecc_mode(mtd, ECC_HW_MODE);
400 vf610_nfc_send_commands(nfc->regs, NAND_CMD_READ0,
401 NAND_CMD_READSTART, READ_PAGE_CMD_CODE);
402 vf610_nfc_addr_cycle(mtd, column, page);
406 nfc->alt_buf = ALT_BUF_ONFI;
407 trfr_sz = 3 * sizeof(struct nand_onfi_params);
408 vf610_nfc_transfer_size(nfc->regs, trfr_sz);
409 vf610_nfc_send_command(nfc->regs, NAND_CMD_PARAM,
410 READ_ONFI_PARAM_CMD_CODE);
411 vf610_nfc_set_field(mtd, NFC_ROW_ADDR, ROW_ADDR_MASK,
412 ROW_ADDR_SHIFT, column);
413 vf610_nfc_ecc_mode(mtd, ECC_BYPASS);
416 case NAND_CMD_ERASE1:
417 vf610_nfc_transfer_size(nfc->regs, 0);
418 vf610_nfc_send_commands(nfc->regs, command,
419 NAND_CMD_ERASE2, ERASE_CMD_CODE);
420 vf610_nfc_addr_cycle(mtd, column, page);
423 case NAND_CMD_READID:
424 nfc->alt_buf = ALT_BUF_ID;
426 vf610_nfc_transfer_size(nfc->regs, 0);
427 vf610_nfc_send_command(nfc->regs, command, READ_ID_CMD_CODE);
428 vf610_nfc_set_field(mtd, NFC_ROW_ADDR, ROW_ADDR_MASK,
429 ROW_ADDR_SHIFT, column);
432 case NAND_CMD_STATUS:
433 nfc->alt_buf = ALT_BUF_STAT;
434 vf610_nfc_transfer_size(nfc->regs, 0);
435 vf610_nfc_send_command(nfc->regs, command, STATUS_READ_CMD_CODE);
446 /* Read data from NFC buffers */
447 static void vf610_nfc_read_buf(struct mtd_info *mtd, u_char *buf, int len)
449 struct vf610_nfc *nfc = mtd_to_nfc(mtd);
450 uint c = nfc->buf_offset;
452 /* Alternate buffers are only supported through read_byte */
456 vf610_nfc_memcpy(buf, nfc->regs + NFC_MAIN_AREA(0) + c, len);
458 nfc->buf_offset += len;
461 /* Write data to NFC buffers */
462 static void vf610_nfc_write_buf(struct mtd_info *mtd, const uint8_t *buf,
465 struct vf610_nfc *nfc = mtd_to_nfc(mtd);
466 uint c = nfc->buf_offset;
469 l = min_t(uint, len, mtd->writesize + mtd->oobsize - c);
470 vf610_nfc_memcpy(nfc->regs + NFC_MAIN_AREA(0) + c, buf, l);
473 nfc->buf_offset += l;
476 /* Read byte from NFC buffers */
477 static uint8_t vf610_nfc_read_byte(struct mtd_info *mtd)
479 struct vf610_nfc *nfc = mtd_to_nfc(mtd);
481 uint c = nfc->buf_offset;
483 switch (nfc->alt_buf) {
485 tmp = vf610_nfc_get_id(mtd, c);
488 tmp = vf610_nfc_get_status(mtd);
490 #ifdef __LITTLE_ENDIAN
492 /* Reverse byte since the controller uses big endianness */
493 c = nfc->buf_offset ^ 0x3;
497 tmp = *((u8 *)(nfc->regs + NFC_MAIN_AREA(0) + c));
504 /* Read word from NFC buffers */
505 static u16 vf610_nfc_read_word(struct mtd_info *mtd)
509 vf610_nfc_read_buf(mtd, (u_char *)&tmp, sizeof(tmp));
513 /* If not provided, upper layers apply a fixed delay. */
514 static int vf610_nfc_dev_ready(struct mtd_info *mtd)
516 /* NFC handles R/B internally; always ready. */
521 * This function supports Vybrid only (MPC5125 would have full RB and four CS)
523 static void vf610_nfc_select_chip(struct mtd_info *mtd, int chip)
526 u32 tmp = vf610_nfc_read(mtd, NFC_ROW_ADDR);
527 tmp &= ~(ROW_ADDR_CHIP_SEL_RB_MASK | ROW_ADDR_CHIP_SEL_MASK);
530 tmp |= 1 << ROW_ADDR_CHIP_SEL_RB_SHIFT;
531 tmp |= (1 << chip) << ROW_ADDR_CHIP_SEL_SHIFT;
534 vf610_nfc_write(mtd, NFC_ROW_ADDR, tmp);
538 /* Count the number of 0's in buff upto max_bits */
539 static inline int count_written_bits(uint8_t *buff, int size, int max_bits)
541 uint32_t *buff32 = (uint32_t *)buff;
542 int k, written_bits = 0;
544 for (k = 0; k < (size / 4); k++) {
545 written_bits += hweight32(~buff32[k]);
546 if (written_bits > max_bits)
553 static inline int vf610_nfc_correct_data(struct mtd_info *mtd, uint8_t *dat,
554 uint8_t *oob, int page)
556 struct vf610_nfc *nfc = mtd_to_nfc(mtd);
557 u32 ecc_status_off = NFC_MAIN_AREA(0) + ECC_SRAM_ADDR + ECC_STATUS;
561 int flips_threshold = nfc->chip.ecc.strength / 2;
563 ecc_status = vf610_nfc_read(mtd, ecc_status_off) & 0xff;
564 ecc_count = ecc_status & ECC_STATUS_ERR_COUNT;
566 if (!(ecc_status & ECC_STATUS_MASK))
569 /* Read OOB without ECC unit enabled */
570 vf610_nfc_command(mtd, NAND_CMD_READOOB, 0, page);
571 vf610_nfc_read_buf(mtd, oob, mtd->oobsize);
574 * On an erased page, bit count (including OOB) should be zero or
575 * at least less then half of the ECC strength.
577 flips = count_written_bits(dat, nfc->chip.ecc.size, flips_threshold);
578 flips += count_written_bits(oob, mtd->oobsize, flips_threshold);
580 if (unlikely(flips > flips_threshold))
584 memset(dat, 0xff, nfc->chip.ecc.size);
585 memset(oob, 0xff, mtd->oobsize);
589 static int vf610_nfc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
590 uint8_t *buf, int oob_required, int page)
592 int eccsize = chip->ecc.size;
595 vf610_nfc_read_buf(mtd, buf, eccsize);
597 vf610_nfc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
599 stat = vf610_nfc_correct_data(mtd, buf, chip->oob_poi, page);
602 mtd->ecc_stats.failed++;
605 mtd->ecc_stats.corrected += stat;
611 * ECC will be calculated automatically
613 static int vf610_nfc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
614 const uint8_t *buf, int oob_required)
616 struct vf610_nfc *nfc = mtd_to_nfc(mtd);
618 vf610_nfc_write_buf(mtd, buf, mtd->writesize);
620 vf610_nfc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
622 /* Always write whole page including OOB due to HW ECC */
623 nfc->write_sz = mtd->writesize + mtd->oobsize;
628 struct vf610_nfc_config {
634 static int vf610_nfc_nand_init(int devnum, void __iomem *addr)
636 struct mtd_info *mtd = &nand_info[devnum];
637 struct nand_chip *chip;
638 struct vf610_nfc *nfc;
640 struct vf610_nfc_config cfg = {
642 #ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT
650 nfc = malloc(sizeof(*nfc));
652 printf(KERN_ERR "%s: Memory exhausted!\n", __func__);
663 chip->options |= NAND_BUSWIDTH_16;
665 chip->dev_ready = vf610_nfc_dev_ready;
666 chip->cmdfunc = vf610_nfc_command;
667 chip->read_byte = vf610_nfc_read_byte;
668 chip->read_word = vf610_nfc_read_word;
669 chip->read_buf = vf610_nfc_read_buf;
670 chip->write_buf = vf610_nfc_write_buf;
671 chip->select_chip = vf610_nfc_select_chip;
673 chip->options |= NAND_NO_SUBPAGE_WRITE;
675 chip->ecc.size = PAGE_2K;
677 /* Set configuration register. */
678 vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_16BIT);
679 vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_ADDR_AUTO_INCR_BIT);
680 vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_BUFNO_AUTO_INCR_BIT);
681 vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_BOOT_MODE_BIT);
682 vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_DMA_REQ_BIT);
683 vf610_nfc_set(mtd, NFC_FLASH_CONFIG, CONFIG_FAST_FLASH_BIT);
685 /* Disable virtual pages, only one elementary transfer unit */
686 vf610_nfc_set_field(mtd, NFC_FLASH_CONFIG, CONFIG_PAGE_CNT_MASK,
687 CONFIG_PAGE_CNT_SHIFT, 1);
689 /* first scan to find the device and get the page size */
690 if (nand_scan_ident(mtd, CONFIG_SYS_MAX_NAND_DEVICE, NULL)) {
696 vf610_nfc_set(mtd, NFC_FLASH_CONFIG, CONFIG_16BIT);
698 /* Bad block options. */
700 chip->bbt_options = NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB |
703 /* Single buffer only, max 256 OOB minus ECC status */
704 if (mtd->writesize + mtd->oobsize > PAGE_2K + OOB_MAX - 8) {
705 dev_err(nfc->dev, "Unsupported flash page size\n");
710 if (cfg.hardware_ecc) {
711 if (mtd->writesize != PAGE_2K && mtd->oobsize < 64) {
712 dev_err(nfc->dev, "Unsupported flash with hwecc\n");
717 if (chip->ecc.size != mtd->writesize) {
718 dev_err(nfc->dev, "ecc size: %d\n", chip->ecc.size);
719 dev_err(nfc->dev, "Step size needs to be page size\n");
724 /* Current HW ECC layouts only use 64 bytes of OOB */
725 if (mtd->oobsize > 64)
728 /* propagate ecc.layout to mtd_info */
729 mtd->ecclayout = chip->ecc.layout;
730 chip->ecc.read_page = vf610_nfc_read_page;
731 chip->ecc.write_page = vf610_nfc_write_page;
732 chip->ecc.mode = NAND_ECC_HW;
734 chip->ecc.size = PAGE_2K;
735 chip->ecc.layout = &vf610_nfc_ecc;
736 #if defined(CONFIG_SYS_NAND_VF610_NFC_45_ECC_BYTES)
737 chip->ecc.strength = 24;
738 chip->ecc.bytes = 45;
739 #elif defined(CONFIG_SYS_NAND_VF610_NFC_60_ECC_BYTES)
740 chip->ecc.strength = 32;
741 chip->ecc.bytes = 60;
744 /* Set ECC_STATUS offset */
745 vf610_nfc_set_field(mtd, NFC_FLASH_CONFIG,
746 CONFIG_ECC_SRAM_ADDR_MASK,
747 CONFIG_ECC_SRAM_ADDR_SHIFT,
750 /* Enable ECC status in SRAM */
751 vf610_nfc_set(mtd, NFC_FLASH_CONFIG, CONFIG_ECC_SRAM_REQ_BIT);
754 /* second phase scan */
755 err = nand_scan_tail(mtd);
759 err = nand_register(devnum);
769 void board_nand_init(void)
771 int err = vf610_nfc_nand_init(0, (void __iomem *)CONFIG_SYS_NAND_BASE);
773 printf("VF610 NAND init failed (err %d)\n", err);