2 * Copyright (c) 2011 The Chromium OS Authors.
3 * (C) Copyright 2011 NVIDIA Corporation <www.nvidia.com>
4 * (C) Copyright 2006 Detlev Zundel, dzu@denx.de
5 * (C) Copyright 2006 DENX Software Engineering
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #include <asm/arch/clk_rst.h>
30 #include <asm/arch/clock.h>
31 #include <asm/arch/funcmux.h>
32 #include <asm/arch/gpio.h>
33 #include <asm/errno.h>
34 #include <asm-generic/gpio.h>
36 #include "tegra_nand.h"
38 DECLARE_GLOBAL_DATA_PTR;
40 #define NAND_CMD_TIMEOUT_MS 10
42 #define SKIPPED_SPARE_BYTES 4
44 /* ECC bytes to be generated for tag data */
45 #define TAG_ECC_BYTES 4
47 /* 64 byte oob block info for large page (== 2KB) device
49 * OOB flash layout for Tegra with Reed-Solomon 4 symbol correct ECC:
55 * Yaffs2 will use 16 tag bytes.
57 static struct nand_ecclayout eccoob = {
60 4, 5, 6, 7, 8, 9, 10, 11, 12,
61 13, 14, 15, 16, 17, 18, 19, 20, 21,
62 22, 23, 24, 25, 26, 27, 28, 29, 30,
63 31, 32, 33, 34, 35, 36, 37, 38, 39,
76 ECC_TAG_ERROR = 1 << 0,
77 ECC_DATA_ERROR = 1 << 1
80 /* Timing parameters */
82 FDT_NAND_MAX_TRP_TREA,
84 FDT_NAND_MAX_TCR_TAR_TRR,
86 FDT_NAND_MAX_TCS_TCH_TALS_TALH,
95 /* Information about an attached NAND chip */
97 struct nand_ctlr *reg;
98 int enabled; /* 1 to enable, 0 to disable */
99 struct fdt_gpio_state wp_gpio; /* write-protect GPIO */
100 s32 width; /* bit width, normally 8 */
101 u32 timing[FDT_NAND_TIMING_COUNT];
105 struct nand_ctlr *reg;
108 * When running in PIO mode to get READ ID bytes from register
109 * RESP_0, we need this variable as an index to know which byte in
110 * register RESP_0 should be read.
111 * Because common code in nand_base.c invokes read_byte function two
112 * times for NAND_CMD_READID.
113 * And our controller returns 4 bytes at once in register RESP_0.
116 struct fdt_nand config;
119 static struct nand_drv nand_ctrl;
120 static struct mtd_info *our_mtd;
121 static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
123 #ifdef CONFIG_SYS_DCACHE_OFF
124 static inline void dma_prepare(void *start, unsigned long length,
130 * Prepare for a DMA transaction
132 * For a write we flush out our data. For a read we invalidate, since we
133 * need to do this before we read from the buffer after the DMA has
134 * completed, so may as well do it now.
136 * @param start Start address for DMA buffer (should be cache-aligned)
137 * @param length Length of DMA buffer in bytes
138 * @param is_writing 0 if reading, non-zero if writing
140 static void dma_prepare(void *start, unsigned long length, int is_writing)
142 unsigned long addr = (unsigned long)start;
144 length = ALIGN(length, ARCH_DMA_MINALIGN);
146 flush_dcache_range(addr, addr + length);
148 invalidate_dcache_range(addr, addr + length);
153 * Wait for command completion
155 * @param reg nand_ctlr structure
157 * 1 - Command completed
160 static int nand_waitfor_cmd_completion(struct nand_ctlr *reg)
166 for (i = 0; i < NAND_CMD_TIMEOUT_MS * 1000; i++) {
167 if ((readl(®->command) & CMD_GO) ||
168 !(readl(®->status) & STATUS_RBSY0) ||
169 !(readl(®->isr) & ISR_IS_CMD_DONE)) {
173 reg_val = readl(®->dma_mst_ctrl);
175 * If DMA_MST_CTRL_EN_A_ENABLE or DMA_MST_CTRL_EN_B_ENABLE
176 * is set, that means DMA engine is running.
178 * Then we have to wait until DMA_MST_CTRL_IS_DMA_DONE
179 * is cleared, indicating DMA transfer completion.
181 running = reg_val & (DMA_MST_CTRL_EN_A_ENABLE |
182 DMA_MST_CTRL_EN_B_ENABLE);
183 if (!running || (reg_val & DMA_MST_CTRL_IS_DMA_DONE))
191 * Read one byte from the chip
193 * @param mtd MTD device structure
196 * Read function for 8bit bus-width
198 static uint8_t read_byte(struct mtd_info *mtd)
200 struct nand_chip *chip = mtd->priv;
202 struct nand_drv *info;
204 info = (struct nand_drv *)chip->priv;
206 /* In PIO mode, only 4 bytes can be transferred with single CMD_GO. */
207 if (info->pio_byte_index > 3) {
208 info->pio_byte_index = 0;
209 writel(CMD_GO | CMD_PIO
211 &info->reg->command);
212 if (!nand_waitfor_cmd_completion(info->reg))
213 printf("Command timeout\n");
216 dword_read = readl(&info->reg->resp);
217 dword_read = dword_read >> (8 * info->pio_byte_index);
218 info->pio_byte_index++;
219 return (uint8_t)dword_read;
223 * Check NAND status to see if it is ready or not
225 * @param mtd MTD device structure
230 static int nand_dev_ready(struct mtd_info *mtd)
232 struct nand_chip *chip = mtd->priv;
234 struct nand_drv *info;
236 info = (struct nand_drv *)chip->priv;
238 reg_val = readl(&info->reg->status);
239 if (reg_val & STATUS_RBSY0)
245 /* Dummy implementation: we don't support multiple chips */
246 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
259 * Clear all interrupt status bits
261 * @param reg nand_ctlr structure
263 static void nand_clear_interrupt_status(struct nand_ctlr *reg)
267 /* Clear interrupt status */
268 reg_val = readl(®->isr);
269 writel(reg_val, ®->isr);
273 * Send command to NAND device
275 * @param mtd MTD device structure
276 * @param command the command to be sent
277 * @param column the column address for this command, -1 if none
278 * @param page_addr the page address for this command, -1 if none
280 static void nand_command(struct mtd_info *mtd, unsigned int command,
281 int column, int page_addr)
283 struct nand_chip *chip = mtd->priv;
284 struct nand_drv *info;
286 info = (struct nand_drv *)chip->priv;
289 * Write out the command to the device.
291 * Only command NAND_CMD_RESET or NAND_CMD_READID will come
292 * here before mtd->writesize is initialized.
295 /* Emulate NAND_CMD_READOOB */
296 if (command == NAND_CMD_READOOB) {
297 assert(mtd->writesize != 0);
298 column += mtd->writesize;
299 command = NAND_CMD_READ0;
302 /* Adjust columns for 16 bit bus-width */
303 if (column != -1 && (chip->options & NAND_BUSWIDTH_16))
306 nand_clear_interrupt_status(info->reg);
308 /* Stop DMA engine, clear DMA completion status */
309 writel(DMA_MST_CTRL_EN_A_DISABLE
310 | DMA_MST_CTRL_EN_B_DISABLE
311 | DMA_MST_CTRL_IS_DMA_DONE,
312 &info->reg->dma_mst_ctrl);
315 * Program and erase have their own busy handlers
316 * status and sequential in needs no delay
319 case NAND_CMD_READID:
320 writel(NAND_CMD_READID, &info->reg->cmd_reg1);
321 writel(CMD_GO | CMD_CLE | CMD_ALE | CMD_PIO
323 ((4 - 1) << CMD_TRANS_SIZE_SHIFT)
325 &info->reg->command);
326 info->pio_byte_index = 0;
329 writel(NAND_CMD_READ0, &info->reg->cmd_reg1);
330 writel(NAND_CMD_READSTART, &info->reg->cmd_reg2);
331 writel((page_addr << 16) | (column & 0xFFFF),
332 &info->reg->addr_reg1);
333 writel(page_addr >> 16, &info->reg->addr_reg2);
336 writel(NAND_CMD_SEQIN, &info->reg->cmd_reg1);
337 writel(NAND_CMD_PAGEPROG, &info->reg->cmd_reg2);
338 writel((page_addr << 16) | (column & 0xFFFF),
339 &info->reg->addr_reg1);
340 writel(page_addr >> 16,
341 &info->reg->addr_reg2);
343 case NAND_CMD_PAGEPROG:
345 case NAND_CMD_ERASE1:
346 writel(NAND_CMD_ERASE1, &info->reg->cmd_reg1);
347 writel(NAND_CMD_ERASE2, &info->reg->cmd_reg2);
348 writel(page_addr, &info->reg->addr_reg1);
349 writel(CMD_GO | CMD_CLE | CMD_ALE |
350 CMD_SEC_CMD | CMD_CE0 | CMD_ALE_BYTES3,
351 &info->reg->command);
353 case NAND_CMD_ERASE2:
355 case NAND_CMD_STATUS:
356 writel(NAND_CMD_STATUS, &info->reg->cmd_reg1);
357 writel(CMD_GO | CMD_CLE | CMD_PIO | CMD_RX
358 | ((1 - 0) << CMD_TRANS_SIZE_SHIFT)
360 &info->reg->command);
361 info->pio_byte_index = 0;
364 writel(NAND_CMD_RESET, &info->reg->cmd_reg1);
365 writel(CMD_GO | CMD_CLE | CMD_CE0,
366 &info->reg->command);
368 case NAND_CMD_RNDOUT:
370 printf("%s: Unsupported command %d\n", __func__, command);
373 if (!nand_waitfor_cmd_completion(info->reg))
374 printf("Command 0x%02X timeout\n", command);
378 * Check whether the pointed buffer are all 0xff (blank).
380 * @param buf data buffer for blank check
381 * @param len length of the buffer in byte
386 static int blank_check(u8 *buf, int len)
390 for (i = 0; i < len; i++)
397 * After a DMA transfer for read, we call this function to see whether there
398 * is any uncorrectable error on the pointed data buffer or oob buffer.
400 * @param reg nand_ctlr structure
401 * @param databuf data buffer
402 * @param a_len data buffer length
403 * @param oobbuf oob buffer
404 * @param b_len oob buffer length
406 * ECC_OK - no ECC error or correctable ECC error
407 * ECC_TAG_ERROR - uncorrectable tag ECC error
408 * ECC_DATA_ERROR - uncorrectable data ECC error
409 * ECC_DATA_ERROR + ECC_TAG_ERROR - uncorrectable data+tag ECC error
411 static int check_ecc_error(struct nand_ctlr *reg, u8 *databuf,
412 int a_len, u8 *oobbuf, int b_len)
414 int return_val = ECC_OK;
417 if (!(readl(®->isr) & ISR_IS_ECC_ERR))
421 * Area A is used for the data block (databuf). Area B is used for
422 * the spare block (oobbuf)
424 reg_val = readl(®->dec_status);
425 if ((reg_val & DEC_STATUS_A_ECC_FAIL) && databuf) {
426 reg_val = readl(®->bch_dec_status_buf);
428 * If uncorrectable error occurs on data area, then see whether
429 * they are all FF. If all are FF, it's a blank page.
432 if ((reg_val & BCH_DEC_STATUS_FAIL_SEC_FLAG_MASK) &&
433 !blank_check(databuf, a_len))
434 return_val |= ECC_DATA_ERROR;
437 if ((reg_val & DEC_STATUS_B_ECC_FAIL) && oobbuf) {
438 reg_val = readl(®->bch_dec_status_buf);
440 * If uncorrectable error occurs on tag area, then see whether
441 * they are all FF. If all are FF, it's a blank page.
444 if ((reg_val & BCH_DEC_STATUS_FAIL_TAG_MASK) &&
445 !blank_check(oobbuf, b_len))
446 return_val |= ECC_TAG_ERROR;
453 * Set GO bit to send command to device
455 * @param reg nand_ctlr structure
457 static void start_command(struct nand_ctlr *reg)
461 reg_val = readl(®->command);
463 writel(reg_val, ®->command);
467 * Clear command GO bit, DMA GO bit, and DMA completion status
469 * @param reg nand_ctlr structure
471 static void stop_command(struct nand_ctlr *reg)
474 writel(0, ®->command);
476 /* Stop DMA engine and clear DMA completion status */
477 writel(DMA_MST_CTRL_GO_DISABLE
478 | DMA_MST_CTRL_IS_DMA_DONE,
483 * Set up NAND bus width and page size
485 * @param info nand_info structure
486 * @param *reg_val address of reg_val
487 * @return 0 if ok, -1 on error
489 static int set_bus_width_page_size(struct fdt_nand *config,
492 if (config->width == 8)
493 *reg_val = CFG_BUS_WIDTH_8BIT;
494 else if (config->width == 16)
495 *reg_val = CFG_BUS_WIDTH_16BIT;
497 debug("%s: Unsupported bus width %d\n", __func__,
502 if (our_mtd->writesize == 512)
503 *reg_val |= CFG_PAGE_SIZE_512;
504 else if (our_mtd->writesize == 2048)
505 *reg_val |= CFG_PAGE_SIZE_2048;
506 else if (our_mtd->writesize == 4096)
507 *reg_val |= CFG_PAGE_SIZE_4096;
509 debug("%s: Unsupported page size %d\n", __func__,
518 * Page read/write function
520 * @param mtd mtd info structure
521 * @param chip nand chip info structure
522 * @param buf data buffer
523 * @param page page number
524 * @param with_ecc 1 to enable ECC, 0 to disable ECC
525 * @param is_writing 0 for read, 1 for write
526 * @return 0 when successfully completed
527 * -EIO when command timeout
529 static int nand_rw_page(struct mtd_info *mtd, struct nand_chip *chip,
530 uint8_t *buf, int page, int with_ecc, int is_writing)
534 struct nand_oobfree *free = chip->ecc.layout->oobfree;
535 /* 4*128=512 (byte) is the value that our HW can support. */
536 ALLOC_CACHE_ALIGN_BUFFER(u32, tag_buf, 128);
538 struct nand_drv *info;
539 struct fdt_nand *config;
541 if ((uintptr_t)buf & 0x03) {
542 printf("buf %p has to be 4-byte aligned\n", buf);
546 info = (struct nand_drv *)chip->priv;
547 config = &info->config;
548 if (set_bus_width_page_size(config, ®_val))
551 /* Need to be 4-byte aligned */
552 tag_ptr = (char *)tag_buf;
554 stop_command(info->reg);
556 writel((1 << chip->page_shift) - 1, &info->reg->dma_cfg_a);
557 writel(virt_to_phys(buf), &info->reg->data_block_ptr);
560 writel(virt_to_phys(tag_ptr), &info->reg->tag_ptr);
562 memcpy(tag_ptr, chip->oob_poi + free->offset,
563 chip->ecc.layout->oobavail +
566 writel(virt_to_phys(chip->oob_poi), &info->reg->tag_ptr);
569 /* Set ECC selection, configure ECC settings */
571 tag_size = chip->ecc.layout->oobavail + TAG_ECC_BYTES;
572 reg_val |= (CFG_SKIP_SPARE_SEL_4
573 | CFG_SKIP_SPARE_ENABLE
574 | CFG_HW_ECC_CORRECTION_ENABLE
575 | CFG_ECC_EN_TAG_DISABLE
582 tag_size += SKIPPED_SPARE_BYTES;
583 dma_prepare(tag_ptr, tag_size, is_writing);
585 tag_size = mtd->oobsize;
586 reg_val |= (CFG_SKIP_SPARE_DISABLE
587 | CFG_HW_ECC_CORRECTION_DISABLE
588 | CFG_ECC_EN_TAG_DISABLE
591 dma_prepare(chip->oob_poi, tag_size, is_writing);
593 writel(reg_val, &info->reg->config);
595 dma_prepare(buf, 1 << chip->page_shift, is_writing);
597 writel(BCH_CONFIG_BCH_ECC_DISABLE, &info->reg->bch_config);
599 writel(tag_size - 1, &info->reg->dma_cfg_b);
601 nand_clear_interrupt_status(info->reg);
603 reg_val = CMD_CLE | CMD_ALE
605 | (CMD_ALE_BYTES5 << CMD_ALE_BYTE_SIZE_SHIFT)
608 | (CMD_TRANS_SIZE_PAGE << CMD_TRANS_SIZE_SHIFT)
611 reg_val |= (CMD_AFT_DAT_DISABLE | CMD_RX);
613 reg_val |= (CMD_AFT_DAT_ENABLE | CMD_TX);
614 writel(reg_val, &info->reg->command);
616 /* Setup DMA engine */
617 reg_val = DMA_MST_CTRL_GO_ENABLE
618 | DMA_MST_CTRL_BURST_8WORDS
619 | DMA_MST_CTRL_EN_A_ENABLE
620 | DMA_MST_CTRL_EN_B_ENABLE;
623 reg_val |= DMA_MST_CTRL_DIR_READ;
625 reg_val |= DMA_MST_CTRL_DIR_WRITE;
627 writel(reg_val, &info->reg->dma_mst_ctrl);
629 start_command(info->reg);
631 if (!nand_waitfor_cmd_completion(info->reg)) {
633 printf("Read Page 0x%X timeout ", page);
635 printf("Write Page 0x%X timeout ", page);
639 printf("without ECC");
644 if (with_ecc && !is_writing) {
645 memcpy(chip->oob_poi, tag_ptr,
646 SKIPPED_SPARE_BYTES);
647 memcpy(chip->oob_poi + free->offset,
648 tag_ptr + SKIPPED_SPARE_BYTES,
649 chip->ecc.layout->oobavail);
650 reg_val = (u32)check_ecc_error(info->reg, (u8 *)buf,
651 1 << chip->page_shift,
652 (u8 *)(tag_ptr + SKIPPED_SPARE_BYTES),
653 chip->ecc.layout->oobavail);
654 if (reg_val & ECC_TAG_ERROR)
655 printf("Read Page 0x%X tag ECC error\n", page);
656 if (reg_val & ECC_DATA_ERROR)
657 printf("Read Page 0x%X data ECC error\n",
659 if (reg_val & (ECC_DATA_ERROR | ECC_TAG_ERROR))
666 * Hardware ecc based page read function
668 * @param mtd mtd info structure
669 * @param chip nand chip info structure
670 * @param buf buffer to store read data
671 * @param page page number to read
672 * @return 0 when successfully completed
673 * -EIO when command timeout
675 static int nand_read_page_hwecc(struct mtd_info *mtd,
676 struct nand_chip *chip, uint8_t *buf, int page)
678 return nand_rw_page(mtd, chip, buf, page, 1, 0);
682 * Hardware ecc based page write function
684 * @param mtd mtd info structure
685 * @param chip nand chip info structure
686 * @param buf data buffer
688 static void nand_write_page_hwecc(struct mtd_info *mtd,
689 struct nand_chip *chip, const uint8_t *buf)
692 struct nand_drv *info;
694 info = (struct nand_drv *)chip->priv;
696 page = (readl(&info->reg->addr_reg1) >> 16) |
697 (readl(&info->reg->addr_reg2) << 16);
699 nand_rw_page(mtd, chip, (uint8_t *)buf, page, 1, 1);
704 * Read raw page data without ecc
706 * @param mtd mtd info structure
707 * @param chip nand chip info structure
708 * @param buf buffer to store read data
709 * @param page page number to read
710 * @return 0 when successfully completed
711 * -EINVAL when chip->oob_poi is not double-word aligned
712 * -EIO when command timeout
714 static int nand_read_page_raw(struct mtd_info *mtd,
715 struct nand_chip *chip, uint8_t *buf, int page)
717 return nand_rw_page(mtd, chip, buf, page, 0, 0);
721 * Raw page write function
723 * @param mtd mtd info structure
724 * @param chip nand chip info structure
725 * @param buf data buffer
727 static void nand_write_page_raw(struct mtd_info *mtd,
728 struct nand_chip *chip, const uint8_t *buf)
731 struct nand_drv *info;
733 info = (struct nand_drv *)chip->priv;
734 page = (readl(&info->reg->addr_reg1) >> 16) |
735 (readl(&info->reg->addr_reg2) << 16);
737 nand_rw_page(mtd, chip, (uint8_t *)buf, page, 0, 1);
741 * OOB data read/write function
743 * @param mtd mtd info structure
744 * @param chip nand chip info structure
745 * @param page page number to read
746 * @param with_ecc 1 to enable ECC, 0 to disable ECC
747 * @param is_writing 0 for read, 1 for write
748 * @return 0 when successfully completed
749 * -EINVAL when chip->oob_poi is not double-word aligned
750 * -EIO when command timeout
752 static int nand_rw_oob(struct mtd_info *mtd, struct nand_chip *chip,
753 int page, int with_ecc, int is_writing)
757 struct nand_oobfree *free = chip->ecc.layout->oobfree;
758 struct nand_drv *info;
760 if (((int)chip->oob_poi) & 0x03)
762 info = (struct nand_drv *)chip->priv;
763 if (set_bus_width_page_size(&info->config, ®_val))
766 stop_command(info->reg);
768 writel(virt_to_phys(chip->oob_poi), &info->reg->tag_ptr);
770 /* Set ECC selection */
771 tag_size = mtd->oobsize;
773 reg_val |= CFG_ECC_EN_TAG_ENABLE;
775 reg_val |= (CFG_ECC_EN_TAG_DISABLE);
777 reg_val |= ((tag_size - 1) |
778 CFG_SKIP_SPARE_DISABLE |
779 CFG_HW_ECC_CORRECTION_DISABLE |
781 writel(reg_val, &info->reg->config);
783 dma_prepare(chip->oob_poi, tag_size, is_writing);
785 writel(BCH_CONFIG_BCH_ECC_DISABLE, &info->reg->bch_config);
787 if (is_writing && with_ecc)
788 tag_size -= TAG_ECC_BYTES;
790 writel(tag_size - 1, &info->reg->dma_cfg_b);
792 nand_clear_interrupt_status(info->reg);
794 reg_val = CMD_CLE | CMD_ALE
796 | (CMD_ALE_BYTES5 << CMD_ALE_BYTE_SIZE_SHIFT)
800 reg_val |= (CMD_AFT_DAT_DISABLE | CMD_RX);
802 reg_val |= (CMD_AFT_DAT_ENABLE | CMD_TX);
803 writel(reg_val, &info->reg->command);
805 /* Setup DMA engine */
806 reg_val = DMA_MST_CTRL_GO_ENABLE
807 | DMA_MST_CTRL_BURST_8WORDS
808 | DMA_MST_CTRL_EN_B_ENABLE;
810 reg_val |= DMA_MST_CTRL_DIR_READ;
812 reg_val |= DMA_MST_CTRL_DIR_WRITE;
814 writel(reg_val, &info->reg->dma_mst_ctrl);
816 start_command(info->reg);
818 if (!nand_waitfor_cmd_completion(info->reg)) {
820 printf("Read OOB of Page 0x%X timeout\n", page);
822 printf("Write OOB of Page 0x%X timeout\n", page);
826 if (with_ecc && !is_writing) {
827 reg_val = (u32)check_ecc_error(info->reg, 0, 0,
828 (u8 *)(chip->oob_poi + free->offset),
829 chip->ecc.layout->oobavail);
830 if (reg_val & ECC_TAG_ERROR)
831 printf("Read OOB of Page 0x%X tag ECC error\n", page);
837 * OOB data read function
839 * @param mtd mtd info structure
840 * @param chip nand chip info structure
841 * @param page page number to read
842 * @param sndcmd flag whether to issue read command or not
843 * @return 1 - issue read command next time
846 static int nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
847 int page, int sndcmd)
850 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
853 nand_rw_oob(mtd, chip, page, 0, 0);
858 * OOB data write function
860 * @param mtd mtd info structure
861 * @param chip nand chip info structure
862 * @param page page number to write
863 * @return 0 when successfully completed
864 * -EINVAL when chip->oob_poi is not double-word aligned
865 * -EIO when command timeout
867 static int nand_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
870 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
872 return nand_rw_oob(mtd, chip, page, 0, 1);
876 * Set up NAND memory timings according to the provided parameters
878 * @param timing Timing parameters
879 * @param reg NAND controller register address
881 static void setup_timing(unsigned timing[FDT_NAND_TIMING_COUNT],
882 struct nand_ctlr *reg)
884 u32 reg_val, clk_rate, clk_period, time_val;
886 clk_rate = (u32)clock_get_periph_rate(PERIPH_ID_NDFLASH,
887 CLOCK_ID_PERIPH) / 1000000;
888 clk_period = 1000 / clk_rate;
889 reg_val = ((timing[FDT_NAND_MAX_TRP_TREA] / clk_period) <<
890 TIMING_TRP_RESP_CNT_SHIFT) & TIMING_TRP_RESP_CNT_MASK;
891 reg_val |= ((timing[FDT_NAND_TWB] / clk_period) <<
892 TIMING_TWB_CNT_SHIFT) & TIMING_TWB_CNT_MASK;
893 time_val = timing[FDT_NAND_MAX_TCR_TAR_TRR] / clk_period;
895 reg_val |= ((time_val - 2) << TIMING_TCR_TAR_TRR_CNT_SHIFT) &
896 TIMING_TCR_TAR_TRR_CNT_MASK;
897 reg_val |= ((timing[FDT_NAND_TWHR] / clk_period) <<
898 TIMING_TWHR_CNT_SHIFT) & TIMING_TWHR_CNT_MASK;
899 time_val = timing[FDT_NAND_MAX_TCS_TCH_TALS_TALH] / clk_period;
901 reg_val |= ((time_val - 1) << TIMING_TCS_CNT_SHIFT) &
903 reg_val |= ((timing[FDT_NAND_TWH] / clk_period) <<
904 TIMING_TWH_CNT_SHIFT) & TIMING_TWH_CNT_MASK;
905 reg_val |= ((timing[FDT_NAND_TWP] / clk_period) <<
906 TIMING_TWP_CNT_SHIFT) & TIMING_TWP_CNT_MASK;
907 reg_val |= ((timing[FDT_NAND_TRH] / clk_period) <<
908 TIMING_TRH_CNT_SHIFT) & TIMING_TRH_CNT_MASK;
909 reg_val |= ((timing[FDT_NAND_MAX_TRP_TREA] / clk_period) <<
910 TIMING_TRP_CNT_SHIFT) & TIMING_TRP_CNT_MASK;
911 writel(reg_val, ®->timing);
914 time_val = timing[FDT_NAND_TADL] / clk_period;
916 reg_val = (time_val - 2) & TIMING2_TADL_CNT_MASK;
917 writel(reg_val, ®->timing2);
921 * Decode NAND parameters from the device tree
923 * @param blob Device tree blob
924 * @param node Node containing "nand-flash" compatble node
925 * @return 0 if ok, -ve on error (FDT_ERR_...)
927 static int fdt_decode_nand(const void *blob, int node, struct fdt_nand *config)
931 config->reg = (struct nand_ctlr *)fdtdec_get_addr(blob, node, "reg");
932 config->enabled = fdtdec_get_is_enabled(blob, node);
933 config->width = fdtdec_get_int(blob, node, "nvidia,nand-width", 8);
934 err = fdtdec_decode_gpio(blob, node, "nvidia,wp-gpios",
938 err = fdtdec_get_int_array(blob, node, "nvidia,timing",
939 config->timing, FDT_NAND_TIMING_COUNT);
943 /* Now look up the controller and decode that */
944 node = fdt_next_node(blob, node, NULL);
952 * Board-specific NAND initialization
954 * @param nand nand chip info structure
955 * @return 0, after initialized, -1 on error
957 int tegra_nand_init(struct nand_chip *nand, int devnum)
959 struct nand_drv *info = &nand_ctrl;
960 struct fdt_nand *config = &info->config;
963 node = fdtdec_next_compatible(gd->fdt_blob, 0,
964 COMPAT_NVIDIA_TEGRA20_NAND);
967 if (fdt_decode_nand(gd->fdt_blob, node, config)) {
968 printf("Could not decode nand-flash in device tree\n");
971 if (!config->enabled)
973 info->reg = config->reg;
974 nand->ecc.mode = NAND_ECC_HW;
975 nand->ecc.layout = &eccoob;
977 nand->options = LP_OPTIONS;
978 nand->cmdfunc = nand_command;
979 nand->read_byte = read_byte;
980 nand->ecc.read_page = nand_read_page_hwecc;
981 nand->ecc.write_page = nand_write_page_hwecc;
982 nand->ecc.read_page_raw = nand_read_page_raw;
983 nand->ecc.write_page_raw = nand_write_page_raw;
984 nand->ecc.read_oob = nand_read_oob;
985 nand->ecc.write_oob = nand_write_oob;
986 nand->select_chip = nand_select_chip;
987 nand->dev_ready = nand_dev_ready;
988 nand->priv = &nand_ctrl;
990 /* Adjust controller clock rate */
991 clock_start_periph_pll(PERIPH_ID_NDFLASH, CLOCK_ID_PERIPH, 52000000);
993 /* Adjust timing for NAND device */
994 setup_timing(config->timing, info->reg);
996 funcmux_select(PERIPH_ID_NDFLASH, FUNCMUX_DEFAULT);
997 fdtdec_setup_gpio(&config->wp_gpio);
998 gpio_direction_output(config->wp_gpio.gpio, 1);
1000 our_mtd = &nand_info[devnum];
1001 our_mtd->priv = nand;
1002 ret = nand_scan_ident(our_mtd, CONFIG_SYS_NAND_MAX_CHIPS, NULL);
1006 nand->ecc.size = our_mtd->writesize;
1007 nand->ecc.bytes = our_mtd->oobsize;
1009 ret = nand_scan_tail(our_mtd);
1013 ret = nand_register(devnum);
1020 void board_nand_init(void)
1022 struct nand_chip *nand = &nand_chip[0];
1024 if (tegra_nand_init(nand, 0))
1025 puts("Tegra NAND init failed\n");