2 * Copyright (c) 2011 The Chromium OS Authors.
3 * (C) Copyright 2011 NVIDIA Corporation <www.nvidia.com>
4 * (C) Copyright 2006 Detlev Zundel, dzu@denx.de
5 * (C) Copyright 2006 DENX Software Engineering
7 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/arch/clock.h>
14 #include <asm/arch/funcmux.h>
15 #include <asm/arch-tegra/clk_rst.h>
16 #include <asm/errno.h>
19 #include "tegra_nand.h"
21 DECLARE_GLOBAL_DATA_PTR;
23 #define NAND_CMD_TIMEOUT_MS 10
25 #define SKIPPED_SPARE_BYTES 4
27 /* ECC bytes to be generated for tag data */
28 #define TAG_ECC_BYTES 4
30 /* 64 byte oob block info for large page (== 2KB) device
32 * OOB flash layout for Tegra with Reed-Solomon 4 symbol correct ECC:
38 * Yaffs2 will use 16 tag bytes.
40 static struct nand_ecclayout eccoob = {
43 4, 5, 6, 7, 8, 9, 10, 11, 12,
44 13, 14, 15, 16, 17, 18, 19, 20, 21,
45 22, 23, 24, 25, 26, 27, 28, 29, 30,
46 31, 32, 33, 34, 35, 36, 37, 38, 39,
59 ECC_TAG_ERROR = 1 << 0,
60 ECC_DATA_ERROR = 1 << 1
63 /* Timing parameters */
65 FDT_NAND_MAX_TRP_TREA,
67 FDT_NAND_MAX_TCR_TAR_TRR,
69 FDT_NAND_MAX_TCS_TCH_TALS_TALH,
78 /* Information about an attached NAND chip */
80 struct nand_ctlr *reg;
81 int enabled; /* 1 to enable, 0 to disable */
82 struct fdt_gpio_state wp_gpio; /* write-protect GPIO */
83 s32 width; /* bit width, normally 8 */
84 u32 timing[FDT_NAND_TIMING_COUNT];
88 struct nand_ctlr *reg;
91 * When running in PIO mode to get READ ID bytes from register
92 * RESP_0, we need this variable as an index to know which byte in
93 * register RESP_0 should be read.
94 * Because common code in nand_base.c invokes read_byte function two
95 * times for NAND_CMD_READID.
96 * And our controller returns 4 bytes at once in register RESP_0.
99 struct fdt_nand config;
102 static struct nand_drv nand_ctrl;
103 static struct mtd_info *our_mtd;
104 static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
106 #ifdef CONFIG_SYS_DCACHE_OFF
107 static inline void dma_prepare(void *start, unsigned long length,
113 * Prepare for a DMA transaction
115 * For a write we flush out our data. For a read we invalidate, since we
116 * need to do this before we read from the buffer after the DMA has
117 * completed, so may as well do it now.
119 * @param start Start address for DMA buffer (should be cache-aligned)
120 * @param length Length of DMA buffer in bytes
121 * @param is_writing 0 if reading, non-zero if writing
123 static void dma_prepare(void *start, unsigned long length, int is_writing)
125 unsigned long addr = (unsigned long)start;
127 length = ALIGN(length, ARCH_DMA_MINALIGN);
129 flush_dcache_range(addr, addr + length);
131 invalidate_dcache_range(addr, addr + length);
136 * Wait for command completion
138 * @param reg nand_ctlr structure
140 * 1 - Command completed
143 static int nand_waitfor_cmd_completion(struct nand_ctlr *reg)
149 for (i = 0; i < NAND_CMD_TIMEOUT_MS * 1000; i++) {
150 if ((readl(®->command) & CMD_GO) ||
151 !(readl(®->status) & STATUS_RBSY0) ||
152 !(readl(®->isr) & ISR_IS_CMD_DONE)) {
156 reg_val = readl(®->dma_mst_ctrl);
158 * If DMA_MST_CTRL_EN_A_ENABLE or DMA_MST_CTRL_EN_B_ENABLE
159 * is set, that means DMA engine is running.
161 * Then we have to wait until DMA_MST_CTRL_IS_DMA_DONE
162 * is cleared, indicating DMA transfer completion.
164 running = reg_val & (DMA_MST_CTRL_EN_A_ENABLE |
165 DMA_MST_CTRL_EN_B_ENABLE);
166 if (!running || (reg_val & DMA_MST_CTRL_IS_DMA_DONE))
174 * Read one byte from the chip
176 * @param mtd MTD device structure
179 * Read function for 8bit bus-width
181 static uint8_t read_byte(struct mtd_info *mtd)
183 struct nand_chip *chip = mtd->priv;
185 struct nand_drv *info;
187 info = (struct nand_drv *)chip->priv;
189 /* In PIO mode, only 4 bytes can be transferred with single CMD_GO. */
190 if (info->pio_byte_index > 3) {
191 info->pio_byte_index = 0;
192 writel(CMD_GO | CMD_PIO
194 &info->reg->command);
195 if (!nand_waitfor_cmd_completion(info->reg))
196 printf("Command timeout\n");
199 dword_read = readl(&info->reg->resp);
200 dword_read = dword_read >> (8 * info->pio_byte_index);
201 info->pio_byte_index++;
202 return (uint8_t)dword_read;
206 * Read len bytes from the chip into a buffer
208 * @param mtd MTD device structure
209 * @param buf buffer to store data to
210 * @param len number of bytes to read
212 * Read function for 8bit bus-width
214 static void read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
218 struct nand_chip *chip = mtd->priv;
219 struct nand_drv *info = (struct nand_drv *)chip->priv;
221 for (i = 0; i < len; i += 4) {
222 s = (len - i) > 4 ? 4 : len - i;
223 writel(CMD_PIO | CMD_RX | CMD_A_VALID | CMD_CE0 |
224 ((s - 1) << CMD_TRANS_SIZE_SHIFT) | CMD_GO,
225 &info->reg->command);
226 if (!nand_waitfor_cmd_completion(info->reg))
227 puts("Command timeout during read_buf\n");
228 reg = readl(&info->reg->resp);
229 memcpy(buf + i, ®, s);
234 * Check NAND status to see if it is ready or not
236 * @param mtd MTD device structure
241 static int nand_dev_ready(struct mtd_info *mtd)
243 struct nand_chip *chip = mtd->priv;
245 struct nand_drv *info;
247 info = (struct nand_drv *)chip->priv;
249 reg_val = readl(&info->reg->status);
250 if (reg_val & STATUS_RBSY0)
256 /* Dummy implementation: we don't support multiple chips */
257 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
270 * Clear all interrupt status bits
272 * @param reg nand_ctlr structure
274 static void nand_clear_interrupt_status(struct nand_ctlr *reg)
278 /* Clear interrupt status */
279 reg_val = readl(®->isr);
280 writel(reg_val, ®->isr);
284 * Send command to NAND device
286 * @param mtd MTD device structure
287 * @param command the command to be sent
288 * @param column the column address for this command, -1 if none
289 * @param page_addr the page address for this command, -1 if none
291 static void nand_command(struct mtd_info *mtd, unsigned int command,
292 int column, int page_addr)
294 struct nand_chip *chip = mtd->priv;
295 struct nand_drv *info;
297 info = (struct nand_drv *)chip->priv;
300 * Write out the command to the device.
302 * Only command NAND_CMD_RESET or NAND_CMD_READID will come
303 * here before mtd->writesize is initialized.
306 /* Emulate NAND_CMD_READOOB */
307 if (command == NAND_CMD_READOOB) {
308 assert(mtd->writesize != 0);
309 column += mtd->writesize;
310 command = NAND_CMD_READ0;
313 /* Adjust columns for 16 bit bus-width */
314 if (column != -1 && (chip->options & NAND_BUSWIDTH_16))
317 nand_clear_interrupt_status(info->reg);
319 /* Stop DMA engine, clear DMA completion status */
320 writel(DMA_MST_CTRL_EN_A_DISABLE
321 | DMA_MST_CTRL_EN_B_DISABLE
322 | DMA_MST_CTRL_IS_DMA_DONE,
323 &info->reg->dma_mst_ctrl);
326 * Program and erase have their own busy handlers
327 * status and sequential in needs no delay
330 case NAND_CMD_READID:
331 writel(NAND_CMD_READID, &info->reg->cmd_reg1);
332 writel(column & 0xFF, &info->reg->addr_reg1);
333 writel(CMD_GO | CMD_CLE | CMD_ALE | CMD_PIO
335 ((4 - 1) << CMD_TRANS_SIZE_SHIFT)
337 &info->reg->command);
338 info->pio_byte_index = 0;
341 writel(NAND_CMD_PARAM, &info->reg->cmd_reg1);
342 writel(column & 0xFF, &info->reg->addr_reg1);
343 writel(CMD_GO | CMD_CLE | CMD_ALE | CMD_CE0,
344 &info->reg->command);
347 writel(NAND_CMD_READ0, &info->reg->cmd_reg1);
348 writel(NAND_CMD_READSTART, &info->reg->cmd_reg2);
349 writel((page_addr << 16) | (column & 0xFFFF),
350 &info->reg->addr_reg1);
351 writel(page_addr >> 16, &info->reg->addr_reg2);
354 writel(NAND_CMD_SEQIN, &info->reg->cmd_reg1);
355 writel(NAND_CMD_PAGEPROG, &info->reg->cmd_reg2);
356 writel((page_addr << 16) | (column & 0xFFFF),
357 &info->reg->addr_reg1);
358 writel(page_addr >> 16,
359 &info->reg->addr_reg2);
361 case NAND_CMD_PAGEPROG:
363 case NAND_CMD_ERASE1:
364 writel(NAND_CMD_ERASE1, &info->reg->cmd_reg1);
365 writel(NAND_CMD_ERASE2, &info->reg->cmd_reg2);
366 writel(page_addr, &info->reg->addr_reg1);
367 writel(CMD_GO | CMD_CLE | CMD_ALE |
368 CMD_SEC_CMD | CMD_CE0 | CMD_ALE_BYTES3,
369 &info->reg->command);
371 case NAND_CMD_ERASE2:
373 case NAND_CMD_STATUS:
374 writel(NAND_CMD_STATUS, &info->reg->cmd_reg1);
375 writel(CMD_GO | CMD_CLE | CMD_PIO | CMD_RX
376 | ((1 - 0) << CMD_TRANS_SIZE_SHIFT)
378 &info->reg->command);
379 info->pio_byte_index = 0;
382 writel(NAND_CMD_RESET, &info->reg->cmd_reg1);
383 writel(CMD_GO | CMD_CLE | CMD_CE0,
384 &info->reg->command);
386 case NAND_CMD_RNDOUT:
388 printf("%s: Unsupported command %d\n", __func__, command);
391 if (!nand_waitfor_cmd_completion(info->reg))
392 printf("Command 0x%02X timeout\n", command);
396 * Check whether the pointed buffer are all 0xff (blank).
398 * @param buf data buffer for blank check
399 * @param len length of the buffer in byte
404 static int blank_check(u8 *buf, int len)
408 for (i = 0; i < len; i++)
415 * After a DMA transfer for read, we call this function to see whether there
416 * is any uncorrectable error on the pointed data buffer or oob buffer.
418 * @param reg nand_ctlr structure
419 * @param databuf data buffer
420 * @param a_len data buffer length
421 * @param oobbuf oob buffer
422 * @param b_len oob buffer length
424 * ECC_OK - no ECC error or correctable ECC error
425 * ECC_TAG_ERROR - uncorrectable tag ECC error
426 * ECC_DATA_ERROR - uncorrectable data ECC error
427 * ECC_DATA_ERROR + ECC_TAG_ERROR - uncorrectable data+tag ECC error
429 static int check_ecc_error(struct nand_ctlr *reg, u8 *databuf,
430 int a_len, u8 *oobbuf, int b_len)
432 int return_val = ECC_OK;
435 if (!(readl(®->isr) & ISR_IS_ECC_ERR))
439 * Area A is used for the data block (databuf). Area B is used for
440 * the spare block (oobbuf)
442 reg_val = readl(®->dec_status);
443 if ((reg_val & DEC_STATUS_A_ECC_FAIL) && databuf) {
444 reg_val = readl(®->bch_dec_status_buf);
446 * If uncorrectable error occurs on data area, then see whether
447 * they are all FF. If all are FF, it's a blank page.
450 if ((reg_val & BCH_DEC_STATUS_FAIL_SEC_FLAG_MASK) &&
451 !blank_check(databuf, a_len))
452 return_val |= ECC_DATA_ERROR;
455 if ((reg_val & DEC_STATUS_B_ECC_FAIL) && oobbuf) {
456 reg_val = readl(®->bch_dec_status_buf);
458 * If uncorrectable error occurs on tag area, then see whether
459 * they are all FF. If all are FF, it's a blank page.
462 if ((reg_val & BCH_DEC_STATUS_FAIL_TAG_MASK) &&
463 !blank_check(oobbuf, b_len))
464 return_val |= ECC_TAG_ERROR;
471 * Set GO bit to send command to device
473 * @param reg nand_ctlr structure
475 static void start_command(struct nand_ctlr *reg)
479 reg_val = readl(®->command);
481 writel(reg_val, ®->command);
485 * Clear command GO bit, DMA GO bit, and DMA completion status
487 * @param reg nand_ctlr structure
489 static void stop_command(struct nand_ctlr *reg)
492 writel(0, ®->command);
494 /* Stop DMA engine and clear DMA completion status */
495 writel(DMA_MST_CTRL_GO_DISABLE
496 | DMA_MST_CTRL_IS_DMA_DONE,
501 * Set up NAND bus width and page size
503 * @param info nand_info structure
504 * @param *reg_val address of reg_val
505 * @return 0 if ok, -1 on error
507 static int set_bus_width_page_size(struct fdt_nand *config,
510 if (config->width == 8)
511 *reg_val = CFG_BUS_WIDTH_8BIT;
512 else if (config->width == 16)
513 *reg_val = CFG_BUS_WIDTH_16BIT;
515 debug("%s: Unsupported bus width %d\n", __func__,
520 if (our_mtd->writesize == 512)
521 *reg_val |= CFG_PAGE_SIZE_512;
522 else if (our_mtd->writesize == 2048)
523 *reg_val |= CFG_PAGE_SIZE_2048;
524 else if (our_mtd->writesize == 4096)
525 *reg_val |= CFG_PAGE_SIZE_4096;
527 debug("%s: Unsupported page size %d\n", __func__,
536 * Page read/write function
538 * @param mtd mtd info structure
539 * @param chip nand chip info structure
540 * @param buf data buffer
541 * @param page page number
542 * @param with_ecc 1 to enable ECC, 0 to disable ECC
543 * @param is_writing 0 for read, 1 for write
544 * @return 0 when successfully completed
545 * -EIO when command timeout
547 static int nand_rw_page(struct mtd_info *mtd, struct nand_chip *chip,
548 uint8_t *buf, int page, int with_ecc, int is_writing)
552 struct nand_oobfree *free = chip->ecc.layout->oobfree;
553 /* 4*128=512 (byte) is the value that our HW can support. */
554 ALLOC_CACHE_ALIGN_BUFFER(u32, tag_buf, 128);
556 struct nand_drv *info;
557 struct fdt_nand *config;
559 if ((uintptr_t)buf & 0x03) {
560 printf("buf %p has to be 4-byte aligned\n", buf);
564 info = (struct nand_drv *)chip->priv;
565 config = &info->config;
566 if (set_bus_width_page_size(config, ®_val))
569 /* Need to be 4-byte aligned */
570 tag_ptr = (char *)tag_buf;
572 stop_command(info->reg);
574 writel((1 << chip->page_shift) - 1, &info->reg->dma_cfg_a);
575 writel(virt_to_phys(buf), &info->reg->data_block_ptr);
578 writel(virt_to_phys(tag_ptr), &info->reg->tag_ptr);
580 memcpy(tag_ptr, chip->oob_poi + free->offset,
581 chip->ecc.layout->oobavail +
584 writel(virt_to_phys(chip->oob_poi), &info->reg->tag_ptr);
587 /* Set ECC selection, configure ECC settings */
589 tag_size = chip->ecc.layout->oobavail + TAG_ECC_BYTES;
590 reg_val |= (CFG_SKIP_SPARE_SEL_4
591 | CFG_SKIP_SPARE_ENABLE
592 | CFG_HW_ECC_CORRECTION_ENABLE
593 | CFG_ECC_EN_TAG_DISABLE
600 tag_size += SKIPPED_SPARE_BYTES;
601 dma_prepare(tag_ptr, tag_size, is_writing);
603 tag_size = mtd->oobsize;
604 reg_val |= (CFG_SKIP_SPARE_DISABLE
605 | CFG_HW_ECC_CORRECTION_DISABLE
606 | CFG_ECC_EN_TAG_DISABLE
609 dma_prepare(chip->oob_poi, tag_size, is_writing);
611 writel(reg_val, &info->reg->config);
613 dma_prepare(buf, 1 << chip->page_shift, is_writing);
615 writel(BCH_CONFIG_BCH_ECC_DISABLE, &info->reg->bch_config);
617 writel(tag_size - 1, &info->reg->dma_cfg_b);
619 nand_clear_interrupt_status(info->reg);
621 reg_val = CMD_CLE | CMD_ALE
623 | (CMD_ALE_BYTES5 << CMD_ALE_BYTE_SIZE_SHIFT)
626 | (CMD_TRANS_SIZE_PAGE << CMD_TRANS_SIZE_SHIFT)
629 reg_val |= (CMD_AFT_DAT_DISABLE | CMD_RX);
631 reg_val |= (CMD_AFT_DAT_ENABLE | CMD_TX);
632 writel(reg_val, &info->reg->command);
634 /* Setup DMA engine */
635 reg_val = DMA_MST_CTRL_GO_ENABLE
636 | DMA_MST_CTRL_BURST_8WORDS
637 | DMA_MST_CTRL_EN_A_ENABLE
638 | DMA_MST_CTRL_EN_B_ENABLE;
641 reg_val |= DMA_MST_CTRL_DIR_READ;
643 reg_val |= DMA_MST_CTRL_DIR_WRITE;
645 writel(reg_val, &info->reg->dma_mst_ctrl);
647 start_command(info->reg);
649 if (!nand_waitfor_cmd_completion(info->reg)) {
651 printf("Read Page 0x%X timeout ", page);
653 printf("Write Page 0x%X timeout ", page);
657 printf("without ECC");
662 if (with_ecc && !is_writing) {
663 memcpy(chip->oob_poi, tag_ptr,
664 SKIPPED_SPARE_BYTES);
665 memcpy(chip->oob_poi + free->offset,
666 tag_ptr + SKIPPED_SPARE_BYTES,
667 chip->ecc.layout->oobavail);
668 reg_val = (u32)check_ecc_error(info->reg, (u8 *)buf,
669 1 << chip->page_shift,
670 (u8 *)(tag_ptr + SKIPPED_SPARE_BYTES),
671 chip->ecc.layout->oobavail);
672 if (reg_val & ECC_TAG_ERROR)
673 printf("Read Page 0x%X tag ECC error\n", page);
674 if (reg_val & ECC_DATA_ERROR)
675 printf("Read Page 0x%X data ECC error\n",
677 if (reg_val & (ECC_DATA_ERROR | ECC_TAG_ERROR))
684 * Hardware ecc based page read function
686 * @param mtd mtd info structure
687 * @param chip nand chip info structure
688 * @param buf buffer to store read data
689 * @param page page number to read
690 * @return 0 when successfully completed
691 * -EIO when command timeout
693 static int nand_read_page_hwecc(struct mtd_info *mtd,
694 struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
696 return nand_rw_page(mtd, chip, buf, page, 1, 0);
700 * Hardware ecc based page write function
702 * @param mtd mtd info structure
703 * @param chip nand chip info structure
704 * @param buf data buffer
706 static int nand_write_page_hwecc(struct mtd_info *mtd,
707 struct nand_chip *chip, const uint8_t *buf, int oob_required)
710 struct nand_drv *info;
712 info = (struct nand_drv *)chip->priv;
714 page = (readl(&info->reg->addr_reg1) >> 16) |
715 (readl(&info->reg->addr_reg2) << 16);
717 nand_rw_page(mtd, chip, (uint8_t *)buf, page, 1, 1);
723 * Read raw page data without ecc
725 * @param mtd mtd info structure
726 * @param chip nand chip info structure
727 * @param buf buffer to store read data
728 * @param page page number to read
729 * @return 0 when successfully completed
730 * -EINVAL when chip->oob_poi is not double-word aligned
731 * -EIO when command timeout
733 static int nand_read_page_raw(struct mtd_info *mtd,
734 struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
736 return nand_rw_page(mtd, chip, buf, page, 0, 0);
740 * Raw page write function
742 * @param mtd mtd info structure
743 * @param chip nand chip info structure
744 * @param buf data buffer
746 static int nand_write_page_raw(struct mtd_info *mtd,
747 struct nand_chip *chip, const uint8_t *buf, int oob_required)
750 struct nand_drv *info;
752 info = (struct nand_drv *)chip->priv;
753 page = (readl(&info->reg->addr_reg1) >> 16) |
754 (readl(&info->reg->addr_reg2) << 16);
756 nand_rw_page(mtd, chip, (uint8_t *)buf, page, 0, 1);
761 * OOB data read/write function
763 * @param mtd mtd info structure
764 * @param chip nand chip info structure
765 * @param page page number to read
766 * @param with_ecc 1 to enable ECC, 0 to disable ECC
767 * @param is_writing 0 for read, 1 for write
768 * @return 0 when successfully completed
769 * -EINVAL when chip->oob_poi is not double-word aligned
770 * -EIO when command timeout
772 static int nand_rw_oob(struct mtd_info *mtd, struct nand_chip *chip,
773 int page, int with_ecc, int is_writing)
777 struct nand_oobfree *free = chip->ecc.layout->oobfree;
778 struct nand_drv *info;
780 if (((int)chip->oob_poi) & 0x03)
782 info = (struct nand_drv *)chip->priv;
783 if (set_bus_width_page_size(&info->config, ®_val))
786 stop_command(info->reg);
788 writel(virt_to_phys(chip->oob_poi), &info->reg->tag_ptr);
790 /* Set ECC selection */
791 tag_size = mtd->oobsize;
793 reg_val |= CFG_ECC_EN_TAG_ENABLE;
795 reg_val |= (CFG_ECC_EN_TAG_DISABLE);
797 reg_val |= ((tag_size - 1) |
798 CFG_SKIP_SPARE_DISABLE |
799 CFG_HW_ECC_CORRECTION_DISABLE |
801 writel(reg_val, &info->reg->config);
803 dma_prepare(chip->oob_poi, tag_size, is_writing);
805 writel(BCH_CONFIG_BCH_ECC_DISABLE, &info->reg->bch_config);
807 if (is_writing && with_ecc)
808 tag_size -= TAG_ECC_BYTES;
810 writel(tag_size - 1, &info->reg->dma_cfg_b);
812 nand_clear_interrupt_status(info->reg);
814 reg_val = CMD_CLE | CMD_ALE
816 | (CMD_ALE_BYTES5 << CMD_ALE_BYTE_SIZE_SHIFT)
820 reg_val |= (CMD_AFT_DAT_DISABLE | CMD_RX);
822 reg_val |= (CMD_AFT_DAT_ENABLE | CMD_TX);
823 writel(reg_val, &info->reg->command);
825 /* Setup DMA engine */
826 reg_val = DMA_MST_CTRL_GO_ENABLE
827 | DMA_MST_CTRL_BURST_8WORDS
828 | DMA_MST_CTRL_EN_B_ENABLE;
830 reg_val |= DMA_MST_CTRL_DIR_READ;
832 reg_val |= DMA_MST_CTRL_DIR_WRITE;
834 writel(reg_val, &info->reg->dma_mst_ctrl);
836 start_command(info->reg);
838 if (!nand_waitfor_cmd_completion(info->reg)) {
840 printf("Read OOB of Page 0x%X timeout\n", page);
842 printf("Write OOB of Page 0x%X timeout\n", page);
846 if (with_ecc && !is_writing) {
847 reg_val = (u32)check_ecc_error(info->reg, 0, 0,
848 (u8 *)(chip->oob_poi + free->offset),
849 chip->ecc.layout->oobavail);
850 if (reg_val & ECC_TAG_ERROR)
851 printf("Read OOB of Page 0x%X tag ECC error\n", page);
857 * OOB data read function
859 * @param mtd mtd info structure
860 * @param chip nand chip info structure
861 * @param page page number to read
863 static int nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
866 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
867 nand_rw_oob(mtd, chip, page, 0, 0);
872 * OOB data write function
874 * @param mtd mtd info structure
875 * @param chip nand chip info structure
876 * @param page page number to write
877 * @return 0 when successfully completed
878 * -EINVAL when chip->oob_poi is not double-word aligned
879 * -EIO when command timeout
881 static int nand_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
884 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
886 return nand_rw_oob(mtd, chip, page, 0, 1);
890 * Set up NAND memory timings according to the provided parameters
892 * @param timing Timing parameters
893 * @param reg NAND controller register address
895 static void setup_timing(unsigned timing[FDT_NAND_TIMING_COUNT],
896 struct nand_ctlr *reg)
898 u32 reg_val, clk_rate, clk_period, time_val;
900 clk_rate = (u32)clock_get_periph_rate(PERIPH_ID_NDFLASH,
901 CLOCK_ID_PERIPH) / 1000000;
902 clk_period = 1000 / clk_rate;
903 reg_val = ((timing[FDT_NAND_MAX_TRP_TREA] / clk_period) <<
904 TIMING_TRP_RESP_CNT_SHIFT) & TIMING_TRP_RESP_CNT_MASK;
905 reg_val |= ((timing[FDT_NAND_TWB] / clk_period) <<
906 TIMING_TWB_CNT_SHIFT) & TIMING_TWB_CNT_MASK;
907 time_val = timing[FDT_NAND_MAX_TCR_TAR_TRR] / clk_period;
909 reg_val |= ((time_val - 2) << TIMING_TCR_TAR_TRR_CNT_SHIFT) &
910 TIMING_TCR_TAR_TRR_CNT_MASK;
911 reg_val |= ((timing[FDT_NAND_TWHR] / clk_period) <<
912 TIMING_TWHR_CNT_SHIFT) & TIMING_TWHR_CNT_MASK;
913 time_val = timing[FDT_NAND_MAX_TCS_TCH_TALS_TALH] / clk_period;
915 reg_val |= ((time_val - 1) << TIMING_TCS_CNT_SHIFT) &
917 reg_val |= ((timing[FDT_NAND_TWH] / clk_period) <<
918 TIMING_TWH_CNT_SHIFT) & TIMING_TWH_CNT_MASK;
919 reg_val |= ((timing[FDT_NAND_TWP] / clk_period) <<
920 TIMING_TWP_CNT_SHIFT) & TIMING_TWP_CNT_MASK;
921 reg_val |= ((timing[FDT_NAND_TRH] / clk_period) <<
922 TIMING_TRH_CNT_SHIFT) & TIMING_TRH_CNT_MASK;
923 reg_val |= ((timing[FDT_NAND_MAX_TRP_TREA] / clk_period) <<
924 TIMING_TRP_CNT_SHIFT) & TIMING_TRP_CNT_MASK;
925 writel(reg_val, ®->timing);
928 time_val = timing[FDT_NAND_TADL] / clk_period;
930 reg_val = (time_val - 2) & TIMING2_TADL_CNT_MASK;
931 writel(reg_val, ®->timing2);
935 * Decode NAND parameters from the device tree
937 * @param blob Device tree blob
938 * @param node Node containing "nand-flash" compatble node
939 * @return 0 if ok, -ve on error (FDT_ERR_...)
941 static int fdt_decode_nand(const void *blob, int node, struct fdt_nand *config)
945 config->reg = (struct nand_ctlr *)fdtdec_get_addr(blob, node, "reg");
946 config->enabled = fdtdec_get_is_enabled(blob, node);
947 config->width = fdtdec_get_int(blob, node, "nvidia,nand-width", 8);
948 err = fdtdec_decode_gpio(blob, node, "nvidia,wp-gpios",
952 err = fdtdec_get_int_array(blob, node, "nvidia,timing",
953 config->timing, FDT_NAND_TIMING_COUNT);
957 /* Now look up the controller and decode that */
958 node = fdt_next_node(blob, node, NULL);
966 * Board-specific NAND initialization
968 * @param nand nand chip info structure
969 * @return 0, after initialized, -1 on error
971 int tegra_nand_init(struct nand_chip *nand, int devnum)
973 struct nand_drv *info = &nand_ctrl;
974 struct fdt_nand *config = &info->config;
977 node = fdtdec_next_compatible(gd->fdt_blob, 0,
978 COMPAT_NVIDIA_TEGRA20_NAND);
981 if (fdt_decode_nand(gd->fdt_blob, node, config)) {
982 printf("Could not decode nand-flash in device tree\n");
985 if (!config->enabled)
987 info->reg = config->reg;
988 nand->ecc.mode = NAND_ECC_HW;
989 nand->ecc.layout = &eccoob;
991 nand->options = LP_OPTIONS;
992 nand->cmdfunc = nand_command;
993 nand->read_byte = read_byte;
994 nand->read_buf = read_buf;
995 nand->ecc.read_page = nand_read_page_hwecc;
996 nand->ecc.write_page = nand_write_page_hwecc;
997 nand->ecc.read_page_raw = nand_read_page_raw;
998 nand->ecc.write_page_raw = nand_write_page_raw;
999 nand->ecc.read_oob = nand_read_oob;
1000 nand->ecc.write_oob = nand_write_oob;
1001 nand->ecc.strength = 1;
1002 nand->select_chip = nand_select_chip;
1003 nand->dev_ready = nand_dev_ready;
1004 nand->priv = &nand_ctrl;
1006 /* Adjust controller clock rate */
1007 clock_start_periph_pll(PERIPH_ID_NDFLASH, CLOCK_ID_PERIPH, 52000000);
1009 /* Adjust timing for NAND device */
1010 setup_timing(config->timing, info->reg);
1012 fdtdec_setup_gpio(&config->wp_gpio);
1013 gpio_direction_output(config->wp_gpio.gpio, 1);
1015 our_mtd = &nand_info[devnum];
1016 our_mtd->priv = nand;
1017 ret = nand_scan_ident(our_mtd, CONFIG_SYS_NAND_MAX_CHIPS, NULL);
1021 nand->ecc.size = our_mtd->writesize;
1022 nand->ecc.bytes = our_mtd->oobsize;
1024 ret = nand_scan_tail(our_mtd);
1028 ret = nand_register(devnum);
1035 void board_nand_init(void)
1037 struct nand_chip *nand = &nand_chip[0];
1039 if (tegra_nand_init(nand, 0))
1040 puts("Tegra NAND init failed\n");