drivers/mtd/nand/sunxi_nand_spl.c

   1 /*
   2  * Copyright (c) 2014-2015, Antmicro Ltd <www.antmicro.com>
   3  * Copyright (c) 2015, AW-SOM Technologies <www.aw-som.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <asm/arch/clock.h>
   9 #include <asm/io.h>
  10 #include <common.h>
  11 #include <config.h>
  12 #include <nand.h>
  13
  14 /* registers */
  15 #define NFC_CTL                    0x00000000
  16 #define NFC_ST                     0x00000004
  17 #define NFC_INT                    0x00000008
  18 #define NFC_TIMING_CTL             0x0000000C
  19 #define NFC_TIMING_CFG             0x00000010
  20 #define NFC_ADDR_LOW               0x00000014
  21 #define NFC_ADDR_HIGH              0x00000018
  22 #define NFC_SECTOR_NUM             0x0000001C
  23 #define NFC_CNT                    0x00000020
  24 #define NFC_CMD                    0x00000024
  25 #define NFC_RCMD_SET               0x00000028
  26 #define NFC_WCMD_SET               0x0000002C
  27 #define NFC_IO_DATA                0x00000030
  28 #define NFC_ECC_CTL                0x00000034
  29 #define NFC_ECC_ST                 0x00000038
  30 #define NFC_DEBUG                  0x0000003C
  31 #define NFC_ECC_CNT0               0x00000040
  32 #define NFC_ECC_CNT1               0x00000044
  33 #define NFC_ECC_CNT2               0x00000048
  34 #define NFC_ECC_CNT3               0x0000004C
  35 #define NFC_USER_DATA_BASE         0x00000050
  36 #define NFC_EFNAND_STATUS          0x00000090
  37 #define NFC_SPARE_AREA             0x000000A0
  38 #define NFC_PATTERN_ID             0x000000A4
  39 #define NFC_RAM0_BASE              0x00000400
  40 #define NFC_RAM1_BASE              0x00000800
  41
  42 #define NFC_CTL_EN                 (1 << 0)
  43 #define NFC_CTL_RESET              (1 << 1)
  44 #define NFC_CTL_RAM_METHOD         (1 << 14)
  45 #define NFC_CTL_PAGE_SIZE_MASK     (0xf << 8)
  46 #define NFC_CTL_PAGE_SIZE(a)       ((fls(a) - 11) << 8)
  47
  48
  49 #define NFC_ECC_EN                 (1 << 0)
  50 #define NFC_ECC_PIPELINE           (1 << 3)
  51 #define NFC_ECC_EXCEPTION          (1 << 4)
  52 #define NFC_ECC_BLOCK_SIZE         (1 << 5)
  53 #define NFC_ECC_RANDOM_EN          (1 << 9)
  54 #define NFC_ECC_RANDOM_DIRECTION   (1 << 10)
  55
  56
  57 #define NFC_ADDR_NUM_OFFSET        16
  58 #define NFC_SEND_ADDR              (1 << 19)
  59 #define NFC_ACCESS_DIR             (1 << 20)
  60 #define NFC_DATA_TRANS             (1 << 21)
  61 #define NFC_SEND_CMD1              (1 << 22)
  62 #define NFC_WAIT_FLAG              (1 << 23)
  63 #define NFC_SEND_CMD2              (1 << 24)
  64 #define NFC_SEQ                    (1 << 25)
  65 #define NFC_DATA_SWAP_METHOD       (1 << 26)
  66 #define NFC_ROW_AUTO_INC           (1 << 27)
  67 #define NFC_SEND_CMD3              (1 << 28)
  68 #define NFC_SEND_CMD4              (1 << 29)
  69 #define NFC_RAW_CMD                (0 << 30)
  70 #define NFC_PAGE_CMD               (2 << 30)
  71
  72 #define NFC_ST_CMD_INT_FLAG        (1 << 1)
  73 #define NFC_ST_DMA_INT_FLAG        (1 << 2)
  74
  75 #define NFC_READ_CMD_OFFSET         0
  76 #define NFC_RANDOM_READ_CMD0_OFFSET 8
  77 #define NFC_RANDOM_READ_CMD1_OFFSET 16
  78
  79 #define NFC_CMD_RNDOUTSTART        0xE0
  80 #define NFC_CMD_RNDOUT             0x05
  81 #define NFC_CMD_READSTART          0x30
  82
  83 #define SUNXI_DMA_CFG_REG0              0x300
  84 #define SUNXI_DMA_SRC_START_ADDR_REG0   0x304
  85 #define SUNXI_DMA_DEST_START_ADDRR_REG0 0x308
  86 #define SUNXI_DMA_DDMA_BC_REG0          0x30C
  87 #define SUNXI_DMA_DDMA_PARA_REG0        0x318
  88
  89 #define SUNXI_DMA_DDMA_CFG_REG_LOADING  (1 << 31)
  90 #define SUNXI_DMA_DDMA_CFG_REG_DMA_DEST_DATA_WIDTH_32 (2 << 25)
  91 #define SUNXI_DMA_DDMA_CFG_REG_DDMA_DST_DRQ_TYPE_DRAM (1 << 16)
  92 #define SUNXI_DMA_DDMA_CFG_REG_DMA_SRC_DATA_WIDTH_32 (2 << 9)
  93 #define SUNXI_DMA_DDMA_CFG_REG_DMA_SRC_ADDR_MODE_IO (1 << 5)
  94 #define SUNXI_DMA_DDMA_CFG_REG_DDMA_SRC_DRQ_TYPE_NFC (3 << 0)
  95
  96 #define SUNXI_DMA_DDMA_PARA_REG_SRC_WAIT_CYC (0x0F << 0)
  97 #define SUNXI_DMA_DDMA_PARA_REG_SRC_BLK_SIZE (0x7F << 8)
  98
  99 struct nfc_config {
 100         int page_size;
 101         int ecc_strength;
 102         int ecc_size;
 103         int addr_cycles;
 104         int nseeds;
 105         bool randomize;
 106         bool valid;
 107 };
 108
 109 /* minimal "boot0" style NAND support for Allwinner A20 */
 110
 111 /* random seed used by linux */
 112 const uint16_t random_seed[128] = {
 113         0x2b75, 0x0bd0, 0x5ca3, 0x62d1, 0x1c93, 0x07e9, 0x2162, 0x3a72,
 114         0x0d67, 0x67f9, 0x1be7, 0x077d, 0x032f, 0x0dac, 0x2716, 0x2436,
 115         0x7922, 0x1510, 0x3860, 0x5287, 0x480f, 0x4252, 0x1789, 0x5a2d,
 116         0x2a49, 0x5e10, 0x437f, 0x4b4e, 0x2f45, 0x216e, 0x5cb7, 0x7130,
 117         0x2a3f, 0x60e4, 0x4dc9, 0x0ef0, 0x0f52, 0x1bb9, 0x6211, 0x7a56,
 118         0x226d, 0x4ea7, 0x6f36, 0x3692, 0x38bf, 0x0c62, 0x05eb, 0x4c55,
 119         0x60f4, 0x728c, 0x3b6f, 0x2037, 0x7f69, 0x0936, 0x651a, 0x4ceb,
 120         0x6218, 0x79f3, 0x383f, 0x18d9, 0x4f05, 0x5c82, 0x2912, 0x6f17,
 121         0x6856, 0x5938, 0x1007, 0x61ab, 0x3e7f, 0x57c2, 0x542f, 0x4f62,
 122         0x7454, 0x2eac, 0x7739, 0x42d4, 0x2f90, 0x435a, 0x2e52, 0x2064,
 123         0x637c, 0x66ad, 0x2c90, 0x0bad, 0x759c, 0x0029, 0x0986, 0x7126,
 124         0x1ca7, 0x1605, 0x386a, 0x27f5, 0x1380, 0x6d75, 0x24c3, 0x0f8e,
 125         0x2b7a, 0x1418, 0x1fd1, 0x7dc1, 0x2d8e, 0x43af, 0x2267, 0x7da3,
 126         0x4e3d, 0x1338, 0x50db, 0x454d, 0x764d, 0x40a3, 0x42e6, 0x262b,
 127         0x2d2e, 0x1aea, 0x2e17, 0x173d, 0x3a6e, 0x71bf, 0x25f9, 0x0a5d,
 128         0x7c57, 0x0fbe, 0x46ce, 0x4939, 0x6b17, 0x37bb, 0x3e91, 0x76db,
 129 };
 130
 131 #define DEFAULT_TIMEOUT_US      100000
 132
 133 static int check_value_inner(int offset, int expected_bits,
 134                              int timeout_us, int negation)
 135 {
 136         do {
 137                 int val = readl(offset) & expected_bits;
 138                 if (negation ? !val : val)
 139                         return 1;
 140                 udelay(1);
 141         } while (--timeout_us);
 142
 143         return 0;
 144 }
 145
 146 static inline int check_value(int offset, int expected_bits,
 147                               int timeout_us)
 148 {
 149         return check_value_inner(offset, expected_bits, timeout_us, 0);
 150 }
 151
 152 static inline int check_value_negated(int offset, int unexpected_bits,
 153                                       int timeout_us)
 154 {
 155         return check_value_inner(offset, unexpected_bits, timeout_us, 1);
 156 }
 157
 158 static int nand_wait_cmd_fifo_empty(void)
 159 {
 160         if (!check_value_negated(SUNXI_NFC_BASE + NFC_ST, NFC_ST_CMD_FIFO_STAT,
 161                                  DEFAULT_TIMEOUT_US)) {
 162                 printf("nand: timeout waiting for empty cmd FIFO\n");
 163                 return -ETIMEDOUT;
 164         }
 165
 166         return 0;
 167 }
 168
 169 static int nand_wait_int(void)
 170 {
 171         if (!check_value(SUNXI_NFC_BASE + NFC_ST, NFC_ST_CMD_INT_FLAG,
 172                          DEFAULT_TIMEOUT_US)) {
 173                 printf("nand: timeout waiting for interruption\n");
 174                 return -ETIMEDOUT;
 175         }
 176
 177         return 0;
 178 }
 179
 180 static int nand_exec_cmd(u32 cmd)
 181 {
 182         int ret;
 183
 184         ret = nand_wait_cmd_fifo_empty();
 185         if (ret)
 186                 return ret;
 187
 188         writel(NFC_ST_CMD_INT_FLAG, SUNXI_NFC_BASE + NFC_ST);
 189         writel(cmd, SUNXI_NFC_BASE + NFC_CMD);
 190
 191         return nand_wait_int();
 192 }
 193
 194 void nand_init(void)
 195 {
 196         uint32_t val;
 197
 198         board_nand_init();
 199
 200         val = readl(SUNXI_NFC_BASE + NFC_CTL);
 201         /* enable and reset CTL */
 202         writel(val | NFC_CTL_EN | NFC_CTL_RESET,
 203                SUNXI_NFC_BASE + NFC_CTL);
 204
 205         if (!check_value_negated(SUNXI_NFC_BASE + NFC_CTL,
 206                                  NFC_CTL_RESET, DEFAULT_TIMEOUT_US)) {
 207                 printf("Couldn't initialize nand\n");
 208         }
 209
 210         /* reset NAND */
 211         nand_exec_cmd(NFC_SEND_CMD1 | NFC_WAIT_FLAG | NAND_CMD_RESET);
 212 }
 213
 214 static void nand_apply_config(const struct nfc_config *conf)
 215 {
 216         u32 val;
 217
 218         nand_wait_cmd_fifo_empty();
 219
 220         val = readl(SUNXI_NFC_BASE + NFC_CTL);
 221         val &= ~NFC_CTL_PAGE_SIZE_MASK;
 222         writel(val | NFC_CTL_RAM_METHOD | NFC_CTL_PAGE_SIZE(conf->page_size),
 223                SUNXI_NFC_BASE + NFC_CTL);
 224         writel(conf->ecc_size, SUNXI_NFC_BASE + NFC_CNT);
 225         writel(conf->page_size, SUNXI_NFC_BASE + NFC_SPARE_AREA);
 226 }
 227
 228 static int nand_load_page(const struct nfc_config *conf, u32 offs)
 229 {
 230         int page = offs / conf->page_size;
 231
 232         writel((NFC_CMD_RNDOUTSTART << NFC_RANDOM_READ_CMD1_OFFSET) |
 233                (NFC_CMD_RNDOUT << NFC_RANDOM_READ_CMD0_OFFSET) |
 234                (NFC_CMD_READSTART << NFC_READ_CMD_OFFSET),
 235                SUNXI_NFC_BASE + NFC_RCMD_SET);
 236         writel(((page & 0xFFFF) << 16), SUNXI_NFC_BASE + NFC_ADDR_LOW);
 237         writel((page >> 16) & 0xFF, SUNXI_NFC_BASE + NFC_ADDR_HIGH);
 238
 239         return nand_exec_cmd(NFC_SEND_CMD1 | NFC_SEND_CMD2 | NFC_RAW_CMD |
 240                              NFC_SEND_ADDR | NFC_WAIT_FLAG |
 241                              ((conf->addr_cycles - 1) << NFC_ADDR_NUM_OFFSET));
 242 }
 243
 244 static int nand_reset_column(void)
 245 {
 246         writel((NFC_CMD_RNDOUTSTART << NFC_RANDOM_READ_CMD1_OFFSET) |
 247                (NFC_CMD_RNDOUT << NFC_RANDOM_READ_CMD0_OFFSET) |
 248                (NFC_CMD_RNDOUTSTART << NFC_READ_CMD_OFFSET),
 249                SUNXI_NFC_BASE + NFC_RCMD_SET);
 250         writel(0, SUNXI_NFC_BASE + NFC_ADDR_LOW);
 251
 252         return nand_exec_cmd(NFC_SEND_CMD1 | NFC_SEND_CMD2 | NFC_RAW_CMD |
 253                              (1 << NFC_ADDR_NUM_OFFSET) | NFC_SEND_ADDR |
 254                              NFC_CMD_RNDOUT);
 255 }
 256
 257 static int nand_read_page(const struct nfc_config *conf, u32 offs,
 258                           void *dest, int len)
 259 {
 260         dma_addr_t dst = (dma_addr_t)dest;
 261         int nsectors = len / conf->ecc_size;
 262         u16 rand_seed = 0;
 263         u32 val;
 264         int page;
 265
 266         page = offs / conf->page_size;
 267
 268         if (offs % conf->page_size || len % conf->ecc_size ||
 269             len > conf->page_size || len < 0)
 270                 return -EINVAL;
 271
 272         /* clear ecc status */
 273         writel(0, SUNXI_NFC_BASE + NFC_ECC_ST);
 274
 275         /* Choose correct seed if randomized */
 276         if (conf->randomize)
 277                 rand_seed = random_seed[page % conf->nseeds];
 278
 279         writel((rand_seed << 16) | (conf->ecc_strength << 12) |
 280                 (conf->randomize ? NFC_ECC_RANDOM_EN : 0) |
 281                 (conf->ecc_size == 512 ? NFC_ECC_BLOCK_SIZE : 0) |
 282                 NFC_ECC_EN | NFC_ECC_PIPELINE | NFC_ECC_EXCEPTION,
 283                 SUNXI_NFC_BASE + NFC_ECC_CTL);
 284
 285         flush_dcache_range(dst, ALIGN(dst + conf->ecc_size, ARCH_DMA_MINALIGN));
 286
 287         /* SUNXI_DMA */
 288         writel(0x0, SUNXI_DMA_BASE + SUNXI_DMA_CFG_REG0); /* clr dma cmd */
 289         /* read from REG_IO_DATA */
 290         writel(SUNXI_NFC_BASE + NFC_IO_DATA,
 291                SUNXI_DMA_BASE + SUNXI_DMA_SRC_START_ADDR_REG0);
 292         /* read to RAM */
 293         writel(dst, SUNXI_DMA_BASE + SUNXI_DMA_DEST_START_ADDRR_REG0);
 294         writel(SUNXI_DMA_DDMA_PARA_REG_SRC_WAIT_CYC |
 295                SUNXI_DMA_DDMA_PARA_REG_SRC_BLK_SIZE,
 296                SUNXI_DMA_BASE + SUNXI_DMA_DDMA_PARA_REG0);
 297         writel(len, SUNXI_DMA_BASE + SUNXI_DMA_DDMA_BC_REG0);
 298         writel(SUNXI_DMA_DDMA_CFG_REG_LOADING |
 299                SUNXI_DMA_DDMA_CFG_REG_DMA_DEST_DATA_WIDTH_32 |
 300                SUNXI_DMA_DDMA_CFG_REG_DDMA_DST_DRQ_TYPE_DRAM |
 301                SUNXI_DMA_DDMA_CFG_REG_DMA_SRC_DATA_WIDTH_32 |
 302                SUNXI_DMA_DDMA_CFG_REG_DMA_SRC_ADDR_MODE_IO |
 303                SUNXI_DMA_DDMA_CFG_REG_DDMA_SRC_DRQ_TYPE_NFC,
 304                SUNXI_DMA_BASE + SUNXI_DMA_CFG_REG0);
 305
 306         writel(nsectors, SUNXI_NFC_BASE + NFC_SECTOR_NUM);
 307         writel(NFC_ST_DMA_INT_FLAG, SUNXI_NFC_BASE + NFC_ST);
 308         writel(NFC_DATA_TRANS | NFC_PAGE_CMD | NFC_DATA_SWAP_METHOD,
 309                SUNXI_NFC_BASE + NFC_CMD);
 310
 311         if (!check_value(SUNXI_NFC_BASE + NFC_ST, NFC_ST_DMA_INT_FLAG,
 312                          DEFAULT_TIMEOUT_US)) {
 313                 printf("Error while initializing dma interrupt\n");
 314                 return -EIO;
 315         }
 316         writel(NFC_ST_DMA_INT_FLAG, SUNXI_NFC_BASE + NFC_ST);
 317
 318         if (!check_value_negated(SUNXI_DMA_BASE + SUNXI_DMA_CFG_REG0,
 319                                  SUNXI_DMA_DDMA_CFG_REG_LOADING,
 320                                  DEFAULT_TIMEOUT_US)) {
 321                 printf("Error while waiting for dma transfer to finish\n");
 322                 return -EIO;
 323         }
 324
 325         invalidate_dcache_range(dst,
 326                                 ALIGN(dst + conf->ecc_size, ARCH_DMA_MINALIGN));
 327
 328         val = readl(SUNXI_NFC_BASE + NFC_ECC_ST);
 329
 330         /* ECC error detected. */
 331         if (val & 0xffff)
 332                 return -EIO;
 333
 334         /*
 335          * Return 1 if the page is empty.
 336          * We consider the page as empty if the first ECC block is marked
 337          * empty.
 338          */
 339         return (val & 0x10000) ? 1 : 0;
 340 }
 341
 342 static int nand_max_ecc_strength(struct nfc_config *conf)
 343 {
 344         static const int ecc_bytes[] = { 32, 46, 54, 60, 74, 88, 102, 110, 116 };
 345         int max_oobsize, max_ecc_bytes;
 346         int nsectors = conf->page_size / conf->ecc_size;
 347         int i;
 348
 349         /*
 350          * ECC strength is limited by the size of the OOB area which is
 351          * correlated with the page size.
 352          */
 353         switch (conf->page_size) {
 354         case 2048:
 355                 max_oobsize = 64;
 356                 break;
 357         case 4096:
 358                 max_oobsize = 256;
 359                 break;
 360         case 8192:
 361                 max_oobsize = 640;
 362                 break;
 363         case 16384:
 364                 max_oobsize = 1664;
 365                 break;
 366         default:
 367                 return -EINVAL;
 368         }
 369
 370         max_ecc_bytes = max_oobsize / nsectors;
 371
 372         for (i = 0; i < ARRAY_SIZE(ecc_bytes); i++) {
 373                 if (ecc_bytes[i] > max_ecc_bytes)
 374                         break;
 375         }
 376
 377         if (!i)
 378                 return -EINVAL;
 379
 380         return i - 1;
 381 }
 382
 383 static int nand_detect_ecc_config(struct nfc_config *conf, u32 offs,
 384                                   void *dest)
 385 {
 386         /* NAND with pages > 4k will likely require 1k sector size. */
 387         int min_ecc_size = conf->page_size > 4096 ? 1024 : 512;
 388         int page = offs / conf->page_size;
 389         int ret;
 390
 391         /*
 392          * In most cases, 1k sectors are preferred over 512b ones, start
 393          * testing this config first.
 394          */
 395         for (conf->ecc_size = 1024; conf->ecc_size >= min_ecc_size;
 396              conf->ecc_size >>= 1) {
 397                 int max_ecc_strength = nand_max_ecc_strength(conf);
 398
 399                 nand_apply_config(conf);
 400
 401                 /*
 402                  * We are starting from the maximum ECC strength because
 403                  * most of the time NAND vendors provide an OOB area that
 404                  * barely meets the ECC requirements.
 405                  */
 406                 for (conf->ecc_strength = max_ecc_strength;
 407                      conf->ecc_strength >= 0;
 408                      conf->ecc_strength--) {
 409                         conf->randomize = false;
 410                         if (nand_reset_column())
 411                                 return -EIO;
 412
 413                         /*
 414                          * Only read the first sector to speedup detection.
 415                          */
 416                         ret = nand_read_page(conf, offs, dest, conf->ecc_size);
 417                         if (!ret) {
 418                                 return 0;
 419                         } else if (ret > 0) {
 420                                 /*
 421                                  * If page is empty we can't deduce anything
 422                                  * about the ECC config => stop the detection.
 423                                  */
 424                                 return -EINVAL;
 425                         }
 426
 427                         conf->randomize = true;
 428                         conf->nseeds = ARRAY_SIZE(random_seed);
 429                         do {
 430                                 if (nand_reset_column())
 431                                         return -EIO;
 432
 433                                 if (!nand_read_page(conf, offs, dest,
 434                                                     conf->ecc_size))
 435                                         return 0;
 436
 437                                 /*
 438                                  * Find the next ->nseeds value that would
 439                                  * change the randomizer seed for the page
 440                                  * we're trying to read.
 441                                  */
 442                                 while (conf->nseeds >= 16) {
 443                                         int seed = page % conf->nseeds;
 444
 445                                         conf->nseeds >>= 1;
 446                                         if (seed != page % conf->nseeds)
 447                                                 break;
 448                                 }
 449                         } while (conf->nseeds >= 16);
 450                 }
 451         }
 452
 453         return -EINVAL;
 454 }
 455
 456 static int nand_detect_config(struct nfc_config *conf, u32 offs, void *dest)
 457 {
 458         if (conf->valid)
 459                 return 0;
 460
 461         /*
 462          * Modern NANDs are more likely than legacy ones, so we start testing
 463          * with 5 address cycles.
 464          */
 465         for (conf->addr_cycles = 5;
 466              conf->addr_cycles >= 4;
 467              conf->addr_cycles--) {
 468                 int max_page_size = conf->addr_cycles == 4 ? 2048 : 16384;
 469
 470                 /*
 471                  * Ignoring 1k pages cause I'm not even sure this case exist
 472                  * in the real world.
 473                  */
 474                 for (conf->page_size = 2048; conf->page_size <= max_page_size;
 475                      conf->page_size <<= 1) {
 476                         if (nand_load_page(conf, offs))
 477                                 return -1;
 478
 479                         if (!nand_detect_ecc_config(conf, offs, dest)) {
 480                                 conf->valid = true;
 481                                 return 0;
 482                         }
 483                 }
 484         }
 485
 486         return -EINVAL;
 487 }
 488
 489 static int nand_read_buffer(struct nfc_config *conf, uint32_t offs,
 490                             unsigned int size, void *dest)
 491 {
 492         int first_seed = 0, page, ret;
 493
 494         size = ALIGN(size, conf->page_size);
 495         page = offs / conf->page_size;
 496         if (conf->randomize)
 497                 first_seed = page % conf->nseeds;
 498
 499         for (; size; size -= conf->page_size) {
 500                 if (nand_load_page(conf, offs))
 501                         return -1;
 502
 503                 ret = nand_read_page(conf, offs, dest, conf->page_size);
 504                 /*
 505                  * The ->nseeds value should be equal to the number of pages
 506                  * in an eraseblock. Since we don't know this information in
 507                  * advance we might have picked a wrong value.
 508                  */
 509                 if (ret < 0 && conf->randomize) {
 510                         int cur_seed = page % conf->nseeds;
 511
 512                         /*
 513                          * We already tried all the seed values => we are
 514                          * facing a real corruption.
 515                          */
 516                         if (cur_seed < first_seed)
 517                                 return -EIO;
 518
 519                         /* Try to adjust ->nseeds and read the page again... */
 520                         conf->nseeds = cur_seed;
 521
 522                         if (nand_reset_column())
 523                                 return -EIO;
 524
 525                         /* ... it still fails => it's a real corruption. */
 526                         if (nand_read_page(conf, offs, dest, conf->page_size))
 527                                 return -EIO;
 528                 } else if (ret && conf->randomize) {
 529                         memset(dest, 0xff, conf->page_size);
 530                 }
 531
 532                 page++;
 533                 offs += conf->page_size;
 534                 dest += conf->page_size;
 535         }
 536
 537         return 0;
 538 }
 539
 540 int nand_spl_load_image(uint32_t offs, unsigned int size, void *dest)
 541 {
 542         static struct nfc_config conf = { };
 543         int ret;
 544
 545         ret = nand_detect_config(&conf, offs, dest);
 546         if (ret)
 547                 return ret;
 548
 549         return nand_read_buffer(&conf, offs, size, dest);
 550 }
 551
 552 void nand_deselect(void)
 553 {
 554         struct sunxi_ccm_reg *const ccm =
 555                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 556
 557         clrbits_le32(&ccm->ahb_gate0, (CLK_GATE_OPEN << AHB_GATE_OFFSET_NAND0));
 558 #ifdef CONFIG_MACH_SUN9I
 559         clrbits_le32(&ccm->ahb_gate1, (1 << AHB_GATE_OFFSET_DMA));
 560 #else
 561         clrbits_le32(&ccm->ahb_gate0, (1 << AHB_GATE_OFFSET_DMA));
 562 #endif
 563         clrbits_le32(&ccm->nand0_clk_cfg, CCM_NAND_CTRL_ENABLE | AHB_DIV_1);
 564 }