drivers/mtd/nand/sunxi_nand_spl.c

   1 /*
   2  * Copyright (c) 2014-2015, Antmicro Ltd <www.antmicro.com>
   3  * Copyright (c) 2015, AW-SOM Technologies <www.aw-som.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <asm/arch/clock.h>
   9 #include <asm/io.h>
  10 #include <common.h>
  11 #include <config.h>
  12 #include <nand.h>
  13
  14 /* registers */
  15 #define NFC_CTL                    0x00000000
  16 #define NFC_ST                     0x00000004
  17 #define NFC_INT                    0x00000008
  18 #define NFC_TIMING_CTL             0x0000000C
  19 #define NFC_TIMING_CFG             0x00000010
  20 #define NFC_ADDR_LOW               0x00000014
  21 #define NFC_ADDR_HIGH              0x00000018
  22 #define NFC_SECTOR_NUM             0x0000001C
  23 #define NFC_CNT                    0x00000020
  24 #define NFC_CMD                    0x00000024
  25 #define NFC_RCMD_SET               0x00000028
  26 #define NFC_WCMD_SET               0x0000002C
  27 #define NFC_IO_DATA                0x00000030
  28 #define NFC_ECC_CTL                0x00000034
  29 #define NFC_ECC_ST                 0x00000038
  30 #define NFC_DEBUG                  0x0000003C
  31 #define NFC_ECC_CNT0               0x00000040
  32 #define NFC_ECC_CNT1               0x00000044
  33 #define NFC_ECC_CNT2               0x00000048
  34 #define NFC_ECC_CNT3               0x0000004C
  35 #define NFC_USER_DATA_BASE         0x00000050
  36 #define NFC_EFNAND_STATUS          0x00000090
  37 #define NFC_SPARE_AREA             0x000000A0
  38 #define NFC_PATTERN_ID             0x000000A4
  39 #define NFC_RAM0_BASE              0x00000400
  40 #define NFC_RAM1_BASE              0x00000800
  41
  42 #define NFC_CTL_EN                 (1 << 0)
  43 #define NFC_CTL_RESET              (1 << 1)
  44 #define NFC_CTL_RAM_METHOD         (1 << 14)
  45 #define NFC_CTL_PAGE_SIZE_MASK     (0xf << 8)
  46 #define NFC_CTL_PAGE_SIZE(a)       ((fls(a) - 11) << 8)
  47
  48
  49 #define NFC_ECC_EN                 (1 << 0)
  50 #define NFC_ECC_PIPELINE           (1 << 3)
  51 #define NFC_ECC_EXCEPTION          (1 << 4)
  52 #define NFC_ECC_BLOCK_SIZE         (1 << 5)
  53 #define NFC_ECC_RANDOM_EN          (1 << 9)
  54 #define NFC_ECC_RANDOM_DIRECTION   (1 << 10)
  55
  56
  57 #define NFC_ADDR_NUM_OFFSET        16
  58 #define NFC_SEND_ADR               (1 << 19)
  59 #define NFC_ACCESS_DIR             (1 << 20)
  60 #define NFC_DATA_TRANS             (1 << 21)
  61 #define NFC_SEND_CMD1              (1 << 22)
  62 #define NFC_WAIT_FLAG              (1 << 23)
  63 #define NFC_SEND_CMD2              (1 << 24)
  64 #define NFC_SEQ                    (1 << 25)
  65 #define NFC_DATA_SWAP_METHOD       (1 << 26)
  66 #define NFC_ROW_AUTO_INC           (1 << 27)
  67 #define NFC_SEND_CMD3              (1 << 28)
  68 #define NFC_SEND_CMD4              (1 << 29)
  69 #define NFC_RAW_CMD                (0 << 30)
  70 #define NFC_PAGE_CMD               (2 << 30)
  71
  72 #define NFC_ST_CMD_INT_FLAG        (1 << 1)
  73 #define NFC_ST_DMA_INT_FLAG        (1 << 2)
  74
  75 #define NFC_READ_CMD_OFFSET         0
  76 #define NFC_RANDOM_READ_CMD0_OFFSET 8
  77 #define NFC_RANDOM_READ_CMD1_OFFSET 16
  78
  79 #define NFC_CMD_RNDOUTSTART        0xE0
  80 #define NFC_CMD_RNDOUT             0x05
  81 #define NFC_CMD_READSTART          0x30
  82
  83 #define SUNXI_DMA_CFG_REG0              0x300
  84 #define SUNXI_DMA_SRC_START_ADDR_REG0   0x304
  85 #define SUNXI_DMA_DEST_START_ADDRR_REG0 0x308
  86 #define SUNXI_DMA_DDMA_BC_REG0          0x30C
  87 #define SUNXI_DMA_DDMA_PARA_REG0        0x318
  88
  89 #define SUNXI_DMA_DDMA_CFG_REG_LOADING  (1 << 31)
  90 #define SUNXI_DMA_DDMA_CFG_REG_DMA_DEST_DATA_WIDTH_32 (2 << 25)
  91 #define SUNXI_DMA_DDMA_CFG_REG_DDMA_DST_DRQ_TYPE_DRAM (1 << 16)
  92 #define SUNXI_DMA_DDMA_CFG_REG_DMA_SRC_DATA_WIDTH_32 (2 << 9)
  93 #define SUNXI_DMA_DDMA_CFG_REG_DMA_SRC_ADDR_MODE_IO (1 << 5)
  94 #define SUNXI_DMA_DDMA_CFG_REG_DDMA_SRC_DRQ_TYPE_NFC (3 << 0)
  95
  96 #define SUNXI_DMA_DDMA_PARA_REG_SRC_WAIT_CYC (0x0F << 0)
  97 #define SUNXI_DMA_DDMA_PARA_REG_SRC_BLK_SIZE (0x7F << 8)
  98
  99 struct nfc_config {
 100         int page_size;
 101         int ecc_strength;
 102         int ecc_size;
 103         int addr_cycles;
 104         int nseeds;
 105         bool randomize;
 106 };
 107
 108 /* minimal "boot0" style NAND support for Allwinner A20 */
 109
 110 /* random seed used by linux */
 111 const uint16_t random_seed[128] = {
 112         0x2b75, 0x0bd0, 0x5ca3, 0x62d1, 0x1c93, 0x07e9, 0x2162, 0x3a72,
 113         0x0d67, 0x67f9, 0x1be7, 0x077d, 0x032f, 0x0dac, 0x2716, 0x2436,
 114         0x7922, 0x1510, 0x3860, 0x5287, 0x480f, 0x4252, 0x1789, 0x5a2d,
 115         0x2a49, 0x5e10, 0x437f, 0x4b4e, 0x2f45, 0x216e, 0x5cb7, 0x7130,
 116         0x2a3f, 0x60e4, 0x4dc9, 0x0ef0, 0x0f52, 0x1bb9, 0x6211, 0x7a56,
 117         0x226d, 0x4ea7, 0x6f36, 0x3692, 0x38bf, 0x0c62, 0x05eb, 0x4c55,
 118         0x60f4, 0x728c, 0x3b6f, 0x2037, 0x7f69, 0x0936, 0x651a, 0x4ceb,
 119         0x6218, 0x79f3, 0x383f, 0x18d9, 0x4f05, 0x5c82, 0x2912, 0x6f17,
 120         0x6856, 0x5938, 0x1007, 0x61ab, 0x3e7f, 0x57c2, 0x542f, 0x4f62,
 121         0x7454, 0x2eac, 0x7739, 0x42d4, 0x2f90, 0x435a, 0x2e52, 0x2064,
 122         0x637c, 0x66ad, 0x2c90, 0x0bad, 0x759c, 0x0029, 0x0986, 0x7126,
 123         0x1ca7, 0x1605, 0x386a, 0x27f5, 0x1380, 0x6d75, 0x24c3, 0x0f8e,
 124         0x2b7a, 0x1418, 0x1fd1, 0x7dc1, 0x2d8e, 0x43af, 0x2267, 0x7da3,
 125         0x4e3d, 0x1338, 0x50db, 0x454d, 0x764d, 0x40a3, 0x42e6, 0x262b,
 126         0x2d2e, 0x1aea, 0x2e17, 0x173d, 0x3a6e, 0x71bf, 0x25f9, 0x0a5d,
 127         0x7c57, 0x0fbe, 0x46ce, 0x4939, 0x6b17, 0x37bb, 0x3e91, 0x76db,
 128 };
 129
 130 #define DEFAULT_TIMEOUT_US      100000
 131
 132 static int check_value_inner(int offset, int expected_bits,
 133                              int timeout_us, int negation)
 134 {
 135         do {
 136                 int val = readl(offset) & expected_bits;
 137                 if (negation ? !val : val)
 138                         return 1;
 139                 udelay(1);
 140         } while (--timeout_us);
 141
 142         return 0;
 143 }
 144
 145 static inline int check_value(int offset, int expected_bits,
 146                               int timeout_us)
 147 {
 148         return check_value_inner(offset, expected_bits, timeout_us, 0);
 149 }
 150
 151 static inline int check_value_negated(int offset, int unexpected_bits,
 152                                       int timeout_us)
 153 {
 154         return check_value_inner(offset, unexpected_bits, timeout_us, 1);
 155 }
 156
 157 void nand_init(void)
 158 {
 159         uint32_t val;
 160
 161         board_nand_init();
 162
 163         val = readl(SUNXI_NFC_BASE + NFC_CTL);
 164         /* enable and reset CTL */
 165         writel(val | NFC_CTL_EN | NFC_CTL_RESET,
 166                SUNXI_NFC_BASE + NFC_CTL);
 167
 168         if (!check_value_negated(SUNXI_NFC_BASE + NFC_CTL,
 169                                  NFC_CTL_RESET, DEFAULT_TIMEOUT_US)) {
 170                 printf("Couldn't initialize nand\n");
 171         }
 172
 173         /* reset NAND */
 174         writel(NFC_ST_CMD_INT_FLAG, SUNXI_NFC_BASE + NFC_ST);
 175         writel(NFC_SEND_CMD1 | NFC_WAIT_FLAG | NAND_CMD_RESET,
 176                SUNXI_NFC_BASE + NFC_CMD);
 177
 178         if (!check_value(SUNXI_NFC_BASE + NFC_ST, NFC_ST_CMD_INT_FLAG,
 179                          DEFAULT_TIMEOUT_US)) {
 180                 printf("Error timeout waiting for nand reset\n");
 181                 return;
 182         }
 183         writel(NFC_ST_CMD_INT_FLAG, SUNXI_NFC_BASE + NFC_ST);
 184 }
 185
 186 static void nand_apply_config(const struct nfc_config *conf)
 187 {
 188         u32 val;
 189
 190         val = readl(SUNXI_NFC_BASE + NFC_CTL);
 191         val &= ~NFC_CTL_PAGE_SIZE_MASK;
 192         writel(val | NFC_CTL_RAM_METHOD | NFC_CTL_PAGE_SIZE(conf->page_size),
 193                SUNXI_NFC_BASE + NFC_CTL);
 194         writel(conf->ecc_size, SUNXI_NFC_BASE + NFC_CNT);
 195         writel(conf->page_size, SUNXI_NFC_BASE + NFC_SPARE_AREA);
 196 }
 197
 198 static int nand_load_page(const struct nfc_config *conf, u32 offs)
 199 {
 200         int page = offs / conf->page_size;
 201
 202         writel((NFC_CMD_RNDOUTSTART << NFC_RANDOM_READ_CMD1_OFFSET) |
 203                (NFC_CMD_RNDOUT << NFC_RANDOM_READ_CMD0_OFFSET) |
 204                (NFC_CMD_READSTART << NFC_READ_CMD_OFFSET),
 205                SUNXI_NFC_BASE + NFC_RCMD_SET);
 206         writel(((page & 0xFFFF) << 16), SUNXI_NFC_BASE + NFC_ADDR_LOW);
 207         writel((page >> 16) & 0xFF, SUNXI_NFC_BASE + NFC_ADDR_HIGH);
 208         writel(NFC_ST_CMD_INT_FLAG, SUNXI_NFC_BASE + NFC_ST);
 209         writel(NFC_SEND_CMD1 | NFC_SEND_CMD2 | NFC_RAW_CMD | NFC_WAIT_FLAG |
 210                ((conf->addr_cycles - 1) << NFC_ADDR_NUM_OFFSET) | NFC_SEND_ADR,
 211                SUNXI_NFC_BASE + NFC_CMD);
 212
 213         if (!check_value(SUNXI_NFC_BASE + NFC_ST, NFC_ST_CMD_INT_FLAG,
 214                          DEFAULT_TIMEOUT_US)) {
 215                 printf("Error while initializing dma interrupt\n");
 216                 return -EIO;
 217         }
 218
 219         return 0;
 220 }
 221
 222 static int nand_read_page(const struct nfc_config *conf, u32 offs,
 223                           void *dest, int len)
 224 {
 225         dma_addr_t dst = (dma_addr_t)dest;
 226         int nsectors = len / conf->ecc_size;
 227         u16 rand_seed;
 228         u32 val;
 229         int page;
 230
 231         page = offs / conf->page_size;
 232
 233         if (offs % conf->page_size || len % conf->ecc_size ||
 234             len > conf->page_size || len < 0)
 235                 return -EINVAL;
 236
 237         /* clear ecc status */
 238         writel(0, SUNXI_NFC_BASE + NFC_ECC_ST);
 239
 240         /* Choose correct seed */
 241         rand_seed = random_seed[page % conf->nseeds];
 242
 243         writel((rand_seed << 16) | (conf->ecc_strength << 12) |
 244                 (conf->randomize ? NFC_ECC_RANDOM_EN : 0) |
 245                 (conf->ecc_size == 512 ? NFC_ECC_BLOCK_SIZE : 0) |
 246                 NFC_ECC_EN | NFC_ECC_PIPELINE | NFC_ECC_EXCEPTION,
 247                 SUNXI_NFC_BASE + NFC_ECC_CTL);
 248
 249         flush_dcache_range(dst, ALIGN(dst + conf->ecc_size, ARCH_DMA_MINALIGN));
 250
 251         /* SUNXI_DMA */
 252         writel(0x0, SUNXI_DMA_BASE + SUNXI_DMA_CFG_REG0); /* clr dma cmd */
 253         /* read from REG_IO_DATA */
 254         writel(SUNXI_NFC_BASE + NFC_IO_DATA,
 255                SUNXI_DMA_BASE + SUNXI_DMA_SRC_START_ADDR_REG0);
 256         /* read to RAM */
 257         writel(dst, SUNXI_DMA_BASE + SUNXI_DMA_DEST_START_ADDRR_REG0);
 258         writel(SUNXI_DMA_DDMA_PARA_REG_SRC_WAIT_CYC |
 259                SUNXI_DMA_DDMA_PARA_REG_SRC_BLK_SIZE,
 260                SUNXI_DMA_BASE + SUNXI_DMA_DDMA_PARA_REG0);
 261         writel(len, SUNXI_DMA_BASE + SUNXI_DMA_DDMA_BC_REG0);
 262         writel(SUNXI_DMA_DDMA_CFG_REG_LOADING |
 263                SUNXI_DMA_DDMA_CFG_REG_DMA_DEST_DATA_WIDTH_32 |
 264                SUNXI_DMA_DDMA_CFG_REG_DDMA_DST_DRQ_TYPE_DRAM |
 265                SUNXI_DMA_DDMA_CFG_REG_DMA_SRC_DATA_WIDTH_32 |
 266                SUNXI_DMA_DDMA_CFG_REG_DMA_SRC_ADDR_MODE_IO |
 267                SUNXI_DMA_DDMA_CFG_REG_DDMA_SRC_DRQ_TYPE_NFC,
 268                SUNXI_DMA_BASE + SUNXI_DMA_CFG_REG0);
 269
 270         writel(nsectors, SUNXI_NFC_BASE + NFC_SECTOR_NUM);
 271         writel(NFC_ST_DMA_INT_FLAG, SUNXI_NFC_BASE + NFC_ST);
 272         writel(NFC_DATA_TRANS | NFC_PAGE_CMD | NFC_DATA_SWAP_METHOD,
 273                SUNXI_NFC_BASE + NFC_CMD);
 274
 275         if (!check_value(SUNXI_NFC_BASE + NFC_ST, NFC_ST_DMA_INT_FLAG,
 276                          DEFAULT_TIMEOUT_US)) {
 277                 printf("Error while initializing dma interrupt\n");
 278                 return -EIO;
 279         }
 280         writel(NFC_ST_DMA_INT_FLAG, SUNXI_NFC_BASE + NFC_ST);
 281
 282         if (!check_value_negated(SUNXI_DMA_BASE + SUNXI_DMA_CFG_REG0,
 283                                  SUNXI_DMA_DDMA_CFG_REG_LOADING,
 284                                  DEFAULT_TIMEOUT_US)) {
 285                 printf("Error while waiting for dma transfer to finish\n");
 286                 return -EIO;
 287         }
 288
 289         invalidate_dcache_range(dst,
 290                                 ALIGN(dst + conf->ecc_size, ARCH_DMA_MINALIGN));
 291
 292         val = readl(SUNXI_NFC_BASE + NFC_ECC_ST);
 293
 294         /* ECC error detected. */
 295         if (val & 0xffff)
 296                 return -EIO;
 297
 298         /*
 299          * Return 1 if the page is empty.
 300          * We consider the page as empty if the first ECC block is marked
 301          * empty.
 302          */
 303         return (val & 0x10000) ? 1 : 0;
 304 }
 305
 306 static int nand_read_ecc(int page_size, int ecc_strength, int ecc_page_size,
 307         int addr_cycles, uint32_t offs, uint32_t size, void *dest)
 308 {
 309         void *end = dest + size;
 310         static const u8 strengths[] = { 16, 24, 28, 32, 40, 48, 56, 60, 64 };
 311         struct nfc_config conf = {
 312                 .page_size = page_size,
 313                 .ecc_size = ecc_page_size,
 314                 .addr_cycles = addr_cycles,
 315                 .nseeds = ARRAY_SIZE(random_seed),
 316                 .randomize = true,
 317         };
 318         int i;
 319
 320         for (i = 0; i < ARRAY_SIZE(strengths); i++) {
 321                 if (ecc_strength == strengths[i]) {
 322                         conf.ecc_strength = i;
 323                         break;
 324                 }
 325         }
 326
 327
 328         nand_apply_config(&conf);
 329
 330         for ( ;dest < end; dest += ecc_page_size, offs += page_size) {
 331                 if (nand_load_page(&conf, offs))
 332                         return -1;
 333
 334                 if (nand_read_page(&conf, offs, dest, page_size))
 335                         return -1;
 336         }
 337
 338         return 0;
 339 }
 340
 341 static int nand_read_buffer(uint32_t offs, unsigned int size, void *dest)
 342 {
 343         const struct {
 344                 int page_size;
 345                 int ecc_strength;
 346                 int ecc_page_size;
 347                 int addr_cycles;
 348         } nand_configs[] = {
 349                 {  8192, 40, 1024, 5 },
 350                 { 16384, 56, 1024, 5 },
 351                 {  8192, 24, 1024, 5 },
 352                 {  4096, 24, 1024, 5 },
 353         };
 354         static int nand_config = -1;
 355         int i;
 356
 357         if (nand_config == -1) {
 358                 for (i = 0; i < ARRAY_SIZE(nand_configs); i++) {
 359                         debug("nand: trying page %d ecc %d / %d addr %d: ",
 360                               nand_configs[i].page_size,
 361                               nand_configs[i].ecc_strength,
 362                               nand_configs[i].ecc_page_size,
 363                               nand_configs[i].addr_cycles);
 364                         if (nand_read_ecc(nand_configs[i].page_size,
 365                                           nand_configs[i].ecc_strength,
 366                                           nand_configs[i].ecc_page_size,
 367                                           nand_configs[i].addr_cycles,
 368                                           offs, size, dest) == 0) {
 369                                 debug("success\n");
 370                                 nand_config = i;
 371                                 return 0;
 372                         }
 373                         debug("failed\n");
 374                 }
 375                 return -1;
 376         }
 377
 378         return nand_read_ecc(nand_configs[nand_config].page_size,
 379                              nand_configs[nand_config].ecc_strength,
 380                              nand_configs[nand_config].ecc_page_size,
 381                              nand_configs[nand_config].addr_cycles,
 382                              offs, size, dest);
 383 }
 384
 385 int nand_spl_load_image(uint32_t offs, unsigned int size, void *dest)
 386 {
 387         return nand_read_buffer(offs, size, dest);
 388 }
 389
 390 void nand_deselect(void)
 391 {
 392         struct sunxi_ccm_reg *const ccm =
 393                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 394
 395         clrbits_le32(&ccm->ahb_gate0, (CLK_GATE_OPEN << AHB_GATE_OFFSET_NAND0));
 396 #ifdef CONFIG_MACH_SUN9I
 397         clrbits_le32(&ccm->ahb_gate1, (1 << AHB_GATE_OFFSET_DMA));
 398 #else
 399         clrbits_le32(&ccm->ahb_gate0, (1 << AHB_GATE_OFFSET_DMA));
 400 #endif
 401         clrbits_le32(&ccm->nand0_clk_cfg, CCM_NAND_CTRL_ENABLE | AHB_DIV_1);
 402 }