2 * Copyright (c) 2014-2015, Antmicro Ltd <www.antmicro.com>
3 * Copyright (c) 2015, AW-SOM Technologies <www.aw-som.com>
5 * SPDX-License-Identifier: GPL-2.0+
8 #include <asm/arch/clock.h>
15 #define NFC_CTL 0x00000000
16 #define NFC_ST 0x00000004
17 #define NFC_INT 0x00000008
18 #define NFC_TIMING_CTL 0x0000000C
19 #define NFC_TIMING_CFG 0x00000010
20 #define NFC_ADDR_LOW 0x00000014
21 #define NFC_ADDR_HIGH 0x00000018
22 #define NFC_SECTOR_NUM 0x0000001C
23 #define NFC_CNT 0x00000020
24 #define NFC_CMD 0x00000024
25 #define NFC_RCMD_SET 0x00000028
26 #define NFC_WCMD_SET 0x0000002C
27 #define NFC_IO_DATA 0x00000030
28 #define NFC_ECC_CTL 0x00000034
29 #define NFC_ECC_ST 0x00000038
30 #define NFC_DEBUG 0x0000003C
31 #define NFC_ECC_CNT0 0x00000040
32 #define NFC_ECC_CNT1 0x00000044
33 #define NFC_ECC_CNT2 0x00000048
34 #define NFC_ECC_CNT3 0x0000004C
35 #define NFC_USER_DATA_BASE 0x00000050
36 #define NFC_EFNAND_STATUS 0x00000090
37 #define NFC_SPARE_AREA 0x000000A0
38 #define NFC_PATTERN_ID 0x000000A4
39 #define NFC_RAM0_BASE 0x00000400
40 #define NFC_RAM1_BASE 0x00000800
42 #define NFC_CTL_EN (1 << 0)
43 #define NFC_CTL_RESET (1 << 1)
44 #define NFC_CTL_RAM_METHOD (1 << 14)
45 #define NFC_CTL_PAGE_SIZE_MASK (0xf << 8)
46 #define NFC_CTL_PAGE_SIZE(a) ((fls(a) - 11) << 8)
49 #define NFC_ECC_EN (1 << 0)
50 #define NFC_ECC_PIPELINE (1 << 3)
51 #define NFC_ECC_EXCEPTION (1 << 4)
52 #define NFC_ECC_BLOCK_SIZE (1 << 5)
53 #define NFC_ECC_RANDOM_EN (1 << 9)
54 #define NFC_ECC_RANDOM_DIRECTION (1 << 10)
57 #define NFC_ADDR_NUM_OFFSET 16
58 #define NFC_SEND_ADR (1 << 19)
59 #define NFC_ACCESS_DIR (1 << 20)
60 #define NFC_DATA_TRANS (1 << 21)
61 #define NFC_SEND_CMD1 (1 << 22)
62 #define NFC_WAIT_FLAG (1 << 23)
63 #define NFC_SEND_CMD2 (1 << 24)
64 #define NFC_SEQ (1 << 25)
65 #define NFC_DATA_SWAP_METHOD (1 << 26)
66 #define NFC_ROW_AUTO_INC (1 << 27)
67 #define NFC_SEND_CMD3 (1 << 28)
68 #define NFC_SEND_CMD4 (1 << 29)
69 #define NFC_RAW_CMD (0 << 30)
70 #define NFC_PAGE_CMD (2 << 30)
72 #define NFC_ST_CMD_INT_FLAG (1 << 1)
73 #define NFC_ST_DMA_INT_FLAG (1 << 2)
75 #define NFC_READ_CMD_OFFSET 0
76 #define NFC_RANDOM_READ_CMD0_OFFSET 8
77 #define NFC_RANDOM_READ_CMD1_OFFSET 16
79 #define NFC_CMD_RNDOUTSTART 0xE0
80 #define NFC_CMD_RNDOUT 0x05
81 #define NFC_CMD_READSTART 0x30
83 #define SUNXI_DMA_CFG_REG0 0x300
84 #define SUNXI_DMA_SRC_START_ADDR_REG0 0x304
85 #define SUNXI_DMA_DEST_START_ADDRR_REG0 0x308
86 #define SUNXI_DMA_DDMA_BC_REG0 0x30C
87 #define SUNXI_DMA_DDMA_PARA_REG0 0x318
89 #define SUNXI_DMA_DDMA_CFG_REG_LOADING (1 << 31)
90 #define SUNXI_DMA_DDMA_CFG_REG_DMA_DEST_DATA_WIDTH_32 (2 << 25)
91 #define SUNXI_DMA_DDMA_CFG_REG_DDMA_DST_DRQ_TYPE_DRAM (1 << 16)
92 #define SUNXI_DMA_DDMA_CFG_REG_DMA_SRC_DATA_WIDTH_32 (2 << 9)
93 #define SUNXI_DMA_DDMA_CFG_REG_DMA_SRC_ADDR_MODE_IO (1 << 5)
94 #define SUNXI_DMA_DDMA_CFG_REG_DDMA_SRC_DRQ_TYPE_NFC (3 << 0)
96 #define SUNXI_DMA_DDMA_PARA_REG_SRC_WAIT_CYC (0x0F << 0)
97 #define SUNXI_DMA_DDMA_PARA_REG_SRC_BLK_SIZE (0x7F << 8)
109 /* minimal "boot0" style NAND support for Allwinner A20 */
111 /* random seed used by linux */
112 const uint16_t random_seed[128] = {
113 0x2b75, 0x0bd0, 0x5ca3, 0x62d1, 0x1c93, 0x07e9, 0x2162, 0x3a72,
114 0x0d67, 0x67f9, 0x1be7, 0x077d, 0x032f, 0x0dac, 0x2716, 0x2436,
115 0x7922, 0x1510, 0x3860, 0x5287, 0x480f, 0x4252, 0x1789, 0x5a2d,
116 0x2a49, 0x5e10, 0x437f, 0x4b4e, 0x2f45, 0x216e, 0x5cb7, 0x7130,
117 0x2a3f, 0x60e4, 0x4dc9, 0x0ef0, 0x0f52, 0x1bb9, 0x6211, 0x7a56,
118 0x226d, 0x4ea7, 0x6f36, 0x3692, 0x38bf, 0x0c62, 0x05eb, 0x4c55,
119 0x60f4, 0x728c, 0x3b6f, 0x2037, 0x7f69, 0x0936, 0x651a, 0x4ceb,
120 0x6218, 0x79f3, 0x383f, 0x18d9, 0x4f05, 0x5c82, 0x2912, 0x6f17,
121 0x6856, 0x5938, 0x1007, 0x61ab, 0x3e7f, 0x57c2, 0x542f, 0x4f62,
122 0x7454, 0x2eac, 0x7739, 0x42d4, 0x2f90, 0x435a, 0x2e52, 0x2064,
123 0x637c, 0x66ad, 0x2c90, 0x0bad, 0x759c, 0x0029, 0x0986, 0x7126,
124 0x1ca7, 0x1605, 0x386a, 0x27f5, 0x1380, 0x6d75, 0x24c3, 0x0f8e,
125 0x2b7a, 0x1418, 0x1fd1, 0x7dc1, 0x2d8e, 0x43af, 0x2267, 0x7da3,
126 0x4e3d, 0x1338, 0x50db, 0x454d, 0x764d, 0x40a3, 0x42e6, 0x262b,
127 0x2d2e, 0x1aea, 0x2e17, 0x173d, 0x3a6e, 0x71bf, 0x25f9, 0x0a5d,
128 0x7c57, 0x0fbe, 0x46ce, 0x4939, 0x6b17, 0x37bb, 0x3e91, 0x76db,
131 #define DEFAULT_TIMEOUT_US 100000
133 static int check_value_inner(int offset, int expected_bits,
134 int timeout_us, int negation)
137 int val = readl(offset) & expected_bits;
138 if (negation ? !val : val)
141 } while (--timeout_us);
146 static inline int check_value(int offset, int expected_bits,
149 return check_value_inner(offset, expected_bits, timeout_us, 0);
152 static inline int check_value_negated(int offset, int unexpected_bits,
155 return check_value_inner(offset, unexpected_bits, timeout_us, 1);
164 val = readl(SUNXI_NFC_BASE + NFC_CTL);
165 /* enable and reset CTL */
166 writel(val | NFC_CTL_EN | NFC_CTL_RESET,
167 SUNXI_NFC_BASE + NFC_CTL);
169 if (!check_value_negated(SUNXI_NFC_BASE + NFC_CTL,
170 NFC_CTL_RESET, DEFAULT_TIMEOUT_US)) {
171 printf("Couldn't initialize nand\n");
175 writel(NFC_ST_CMD_INT_FLAG, SUNXI_NFC_BASE + NFC_ST);
176 writel(NFC_SEND_CMD1 | NFC_WAIT_FLAG | NAND_CMD_RESET,
177 SUNXI_NFC_BASE + NFC_CMD);
179 if (!check_value(SUNXI_NFC_BASE + NFC_ST, NFC_ST_CMD_INT_FLAG,
180 DEFAULT_TIMEOUT_US)) {
181 printf("Error timeout waiting for nand reset\n");
184 writel(NFC_ST_CMD_INT_FLAG, SUNXI_NFC_BASE + NFC_ST);
187 static void nand_apply_config(const struct nfc_config *conf)
191 val = readl(SUNXI_NFC_BASE + NFC_CTL);
192 val &= ~NFC_CTL_PAGE_SIZE_MASK;
193 writel(val | NFC_CTL_RAM_METHOD | NFC_CTL_PAGE_SIZE(conf->page_size),
194 SUNXI_NFC_BASE + NFC_CTL);
195 writel(conf->ecc_size, SUNXI_NFC_BASE + NFC_CNT);
196 writel(conf->page_size, SUNXI_NFC_BASE + NFC_SPARE_AREA);
199 static int nand_load_page(const struct nfc_config *conf, u32 offs)
201 int page = offs / conf->page_size;
203 writel((NFC_CMD_RNDOUTSTART << NFC_RANDOM_READ_CMD1_OFFSET) |
204 (NFC_CMD_RNDOUT << NFC_RANDOM_READ_CMD0_OFFSET) |
205 (NFC_CMD_READSTART << NFC_READ_CMD_OFFSET),
206 SUNXI_NFC_BASE + NFC_RCMD_SET);
207 writel(((page & 0xFFFF) << 16), SUNXI_NFC_BASE + NFC_ADDR_LOW);
208 writel((page >> 16) & 0xFF, SUNXI_NFC_BASE + NFC_ADDR_HIGH);
209 writel(NFC_ST_CMD_INT_FLAG, SUNXI_NFC_BASE + NFC_ST);
210 writel(NFC_SEND_CMD1 | NFC_SEND_CMD2 | NFC_RAW_CMD | NFC_WAIT_FLAG |
211 ((conf->addr_cycles - 1) << NFC_ADDR_NUM_OFFSET) | NFC_SEND_ADR,
212 SUNXI_NFC_BASE + NFC_CMD);
214 if (!check_value(SUNXI_NFC_BASE + NFC_ST, NFC_ST_CMD_INT_FLAG,
215 DEFAULT_TIMEOUT_US)) {
216 printf("Error while initializing dma interrupt\n");
223 static int nand_reset_column(void)
225 writel((NFC_CMD_RNDOUTSTART << NFC_RANDOM_READ_CMD1_OFFSET) |
226 (NFC_CMD_RNDOUT << NFC_RANDOM_READ_CMD0_OFFSET) |
227 (NFC_CMD_RNDOUTSTART << NFC_READ_CMD_OFFSET),
228 SUNXI_NFC_BASE + NFC_RCMD_SET);
229 writel(0, SUNXI_NFC_BASE + NFC_ADDR_LOW);
230 writel(NFC_SEND_CMD1 | NFC_SEND_CMD2 | NFC_RAW_CMD |
231 (1 << NFC_ADDR_NUM_OFFSET) | NFC_SEND_ADR | NFC_CMD_RNDOUT,
232 SUNXI_NFC_BASE + NFC_CMD);
234 if (!check_value(SUNXI_NFC_BASE + NFC_ST, NFC_ST_CMD_INT_FLAG,
235 DEFAULT_TIMEOUT_US)) {
236 printf("Error while initializing dma interrupt\n");
243 static int nand_read_page(const struct nfc_config *conf, u32 offs,
246 dma_addr_t dst = (dma_addr_t)dest;
247 int nsectors = len / conf->ecc_size;
252 page = offs / conf->page_size;
254 if (offs % conf->page_size || len % conf->ecc_size ||
255 len > conf->page_size || len < 0)
258 /* clear ecc status */
259 writel(0, SUNXI_NFC_BASE + NFC_ECC_ST);
261 /* Choose correct seed */
262 rand_seed = random_seed[page % conf->nseeds];
264 writel((rand_seed << 16) | (conf->ecc_strength << 12) |
265 (conf->randomize ? NFC_ECC_RANDOM_EN : 0) |
266 (conf->ecc_size == 512 ? NFC_ECC_BLOCK_SIZE : 0) |
267 NFC_ECC_EN | NFC_ECC_PIPELINE | NFC_ECC_EXCEPTION,
268 SUNXI_NFC_BASE + NFC_ECC_CTL);
270 flush_dcache_range(dst, ALIGN(dst + conf->ecc_size, ARCH_DMA_MINALIGN));
273 writel(0x0, SUNXI_DMA_BASE + SUNXI_DMA_CFG_REG0); /* clr dma cmd */
274 /* read from REG_IO_DATA */
275 writel(SUNXI_NFC_BASE + NFC_IO_DATA,
276 SUNXI_DMA_BASE + SUNXI_DMA_SRC_START_ADDR_REG0);
278 writel(dst, SUNXI_DMA_BASE + SUNXI_DMA_DEST_START_ADDRR_REG0);
279 writel(SUNXI_DMA_DDMA_PARA_REG_SRC_WAIT_CYC |
280 SUNXI_DMA_DDMA_PARA_REG_SRC_BLK_SIZE,
281 SUNXI_DMA_BASE + SUNXI_DMA_DDMA_PARA_REG0);
282 writel(len, SUNXI_DMA_BASE + SUNXI_DMA_DDMA_BC_REG0);
283 writel(SUNXI_DMA_DDMA_CFG_REG_LOADING |
284 SUNXI_DMA_DDMA_CFG_REG_DMA_DEST_DATA_WIDTH_32 |
285 SUNXI_DMA_DDMA_CFG_REG_DDMA_DST_DRQ_TYPE_DRAM |
286 SUNXI_DMA_DDMA_CFG_REG_DMA_SRC_DATA_WIDTH_32 |
287 SUNXI_DMA_DDMA_CFG_REG_DMA_SRC_ADDR_MODE_IO |
288 SUNXI_DMA_DDMA_CFG_REG_DDMA_SRC_DRQ_TYPE_NFC,
289 SUNXI_DMA_BASE + SUNXI_DMA_CFG_REG0);
291 writel(nsectors, SUNXI_NFC_BASE + NFC_SECTOR_NUM);
292 writel(NFC_ST_DMA_INT_FLAG, SUNXI_NFC_BASE + NFC_ST);
293 writel(NFC_DATA_TRANS | NFC_PAGE_CMD | NFC_DATA_SWAP_METHOD,
294 SUNXI_NFC_BASE + NFC_CMD);
296 if (!check_value(SUNXI_NFC_BASE + NFC_ST, NFC_ST_DMA_INT_FLAG,
297 DEFAULT_TIMEOUT_US)) {
298 printf("Error while initializing dma interrupt\n");
301 writel(NFC_ST_DMA_INT_FLAG, SUNXI_NFC_BASE + NFC_ST);
303 if (!check_value_negated(SUNXI_DMA_BASE + SUNXI_DMA_CFG_REG0,
304 SUNXI_DMA_DDMA_CFG_REG_LOADING,
305 DEFAULT_TIMEOUT_US)) {
306 printf("Error while waiting for dma transfer to finish\n");
310 invalidate_dcache_range(dst,
311 ALIGN(dst + conf->ecc_size, ARCH_DMA_MINALIGN));
313 val = readl(SUNXI_NFC_BASE + NFC_ECC_ST);
315 /* ECC error detected. */
320 * Return 1 if the page is empty.
321 * We consider the page as empty if the first ECC block is marked
324 return (val & 0x10000) ? 1 : 0;
327 static int nand_max_ecc_strength(struct nfc_config *conf)
329 static const int ecc_bytes[] = { 32, 46, 54, 60, 74, 88, 102, 110, 116 };
330 int max_oobsize, max_ecc_bytes;
331 int nsectors = conf->page_size / conf->ecc_size;
335 * ECC strength is limited by the size of the OOB area which is
336 * correlated with the page size.
338 switch (conf->page_size) {
355 max_ecc_bytes = max_oobsize / nsectors;
357 for (i = 0; i < ARRAY_SIZE(ecc_bytes); i++) {
358 if (ecc_bytes[i] > max_ecc_bytes)
368 static int nand_detect_ecc_config(struct nfc_config *conf, u32 offs,
371 /* NAND with pages > 4k will likely require 1k sector size. */
372 int min_ecc_size = conf->page_size > 4096 ? 1024 : 512;
373 int page = offs / conf->page_size;
377 * In most cases, 1k sectors are preferred over 512b ones, start
378 * testing this config first.
380 for (conf->ecc_size = 1024; conf->ecc_size >= min_ecc_size;
381 conf->ecc_size >>= 1) {
382 int max_ecc_strength = nand_max_ecc_strength(conf);
384 nand_apply_config(conf);
387 * We are starting from the maximum ECC strength because
388 * most of the time NAND vendors provide an OOB area that
389 * barely meets the ECC requirements.
391 for (conf->ecc_strength = max_ecc_strength;
392 conf->ecc_strength >= 0;
393 conf->ecc_strength--) {
394 conf->randomize = false;
395 if (nand_reset_column())
399 * Only read the first sector to speedup detection.
401 ret = nand_read_page(conf, offs, dest, conf->ecc_size);
404 } else if (ret > 0) {
406 * If page is empty we can't deduce anything
407 * about the ECC config => stop the detection.
412 conf->randomize = true;
413 conf->nseeds = ARRAY_SIZE(random_seed);
415 if (nand_reset_column())
418 if (!nand_read_page(conf, offs, dest,
423 * Find the next ->nseeds value that would
424 * change the randomizer seed for the page
425 * we're trying to read.
427 while (conf->nseeds >= 16) {
428 int seed = page % conf->nseeds;
431 if (seed != page % conf->nseeds)
434 } while (conf->nseeds >= 16);
441 static int nand_detect_config(struct nfc_config *conf, u32 offs, void *dest)
447 * Modern NANDs are more likely than legacy ones, so we start testing
448 * with 5 address cycles.
450 for (conf->addr_cycles = 5;
451 conf->addr_cycles >= 4;
452 conf->addr_cycles--) {
453 int max_page_size = conf->addr_cycles == 4 ? 2048 : 16384;
456 * Ignoring 1k pages cause I'm not even sure this case exist
459 for (conf->page_size = 2048; conf->page_size <= max_page_size;
460 conf->page_size <<= 1) {
461 if (nand_load_page(conf, offs))
464 if (!nand_detect_ecc_config(conf, offs, dest)) {
474 static int nand_read_buffer(struct nfc_config *conf, uint32_t offs,
475 unsigned int size, void *dest)
477 int first_seed, page, ret;
479 size = ALIGN(size, conf->page_size);
480 page = offs / conf->page_size;
481 first_seed = page % conf->nseeds;
483 for (; size; size -= conf->page_size) {
484 if (nand_load_page(conf, offs))
487 ret = nand_read_page(conf, offs, dest, conf->page_size);
489 * The ->nseeds value should be equal to the number of pages
490 * in an eraseblock. Since we don't know this information in
491 * advance we might have picked a wrong value.
493 if (ret < 0 && conf->randomize) {
494 int cur_seed = page % conf->nseeds;
497 * We already tried all the seed values => we are
498 * facing a real corruption.
500 if (cur_seed < first_seed)
503 /* Try to adjust ->nseeds and read the page again... */
504 conf->nseeds = cur_seed;
506 if (nand_reset_column())
509 /* ... it still fails => it's a real corruption. */
510 if (nand_read_page(conf, offs, dest, conf->page_size))
512 } else if (ret && conf->randomize) {
513 memset(dest, 0xff, conf->page_size);
517 offs += conf->page_size;
518 dest += conf->page_size;
524 int nand_spl_load_image(uint32_t offs, unsigned int size, void *dest)
526 static struct nfc_config conf = { };
529 ret = nand_detect_config(&conf, offs, dest);
533 return nand_read_buffer(&conf, offs, size, dest);
536 void nand_deselect(void)
538 struct sunxi_ccm_reg *const ccm =
539 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
541 clrbits_le32(&ccm->ahb_gate0, (CLK_GATE_OPEN << AHB_GATE_OFFSET_NAND0));
542 #ifdef CONFIG_MACH_SUN9I
543 clrbits_le32(&ccm->ahb_gate1, (1 << AHB_GATE_OFFSET_DMA));
545 clrbits_le32(&ccm->ahb_gate0, (1 << AHB_GATE_OFFSET_DMA));
547 clrbits_le32(&ccm->nand0_clk_cfg, CCM_NAND_CTRL_ENABLE | AHB_DIV_1);