2 * Copyright (C) 2013 Boris BREZILLON <b.brezillon.dev@gmail.com>
3 * Copyright (C) 2015 Roy Spliet <r.spliet@ultimaker.com>
6 * https://github.com/yuq/sunxi-nfc-mtd
7 * Copyright (C) 2013 Qiang Yu <yuq825@gmail.com>
9 * https://github.com/hno/Allwinner-Info
10 * Copyright (C) 2013 Henrik Nordström <Henrik Nordström>
12 * Copyright (C) 2013 Dmitriy B. <rzk333@gmail.com>
13 * Copyright (C) 2013 Sergey Lapin <slapin@ossfans.org>
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
25 * SPDX-License-Identifier: GPL-2.0+
33 #include <linux/kernel.h>
34 #include <linux/mtd/mtd.h>
35 #include <linux/mtd/rawnand.h>
36 #include <linux/mtd/partitions.h>
40 #include <asm/arch/clock.h>
42 DECLARE_GLOBAL_DATA_PTR;
44 #define NFC_REG_CTL 0x0000
45 #define NFC_REG_ST 0x0004
46 #define NFC_REG_INT 0x0008
47 #define NFC_REG_TIMING_CTL 0x000C
48 #define NFC_REG_TIMING_CFG 0x0010
49 #define NFC_REG_ADDR_LOW 0x0014
50 #define NFC_REG_ADDR_HIGH 0x0018
51 #define NFC_REG_SECTOR_NUM 0x001C
52 #define NFC_REG_CNT 0x0020
53 #define NFC_REG_CMD 0x0024
54 #define NFC_REG_RCMD_SET 0x0028
55 #define NFC_REG_WCMD_SET 0x002C
56 #define NFC_REG_IO_DATA 0x0030
57 #define NFC_REG_ECC_CTL 0x0034
58 #define NFC_REG_ECC_ST 0x0038
59 #define NFC_REG_DEBUG 0x003C
60 #define NFC_REG_ECC_ERR_CNT(x) ((0x0040 + (x)) & ~0x3)
61 #define NFC_REG_USER_DATA(x) (0x0050 + ((x) * 4))
62 #define NFC_REG_SPARE_AREA 0x00A0
63 #define NFC_REG_PAT_ID 0x00A4
64 #define NFC_RAM0_BASE 0x0400
65 #define NFC_RAM1_BASE 0x0800
67 /* define bit use in NFC_CTL */
69 #define NFC_RESET BIT(1)
70 #define NFC_BUS_WIDTH_MSK BIT(2)
71 #define NFC_BUS_WIDTH_8 (0 << 2)
72 #define NFC_BUS_WIDTH_16 (1 << 2)
73 #define NFC_RB_SEL_MSK BIT(3)
74 #define NFC_RB_SEL(x) ((x) << 3)
75 #define NFC_CE_SEL_MSK (0x7 << 24)
76 #define NFC_CE_SEL(x) ((x) << 24)
77 #define NFC_CE_CTL BIT(6)
78 #define NFC_PAGE_SHIFT_MSK (0xf << 8)
79 #define NFC_PAGE_SHIFT(x) (((x) < 10 ? 0 : (x) - 10) << 8)
80 #define NFC_SAM BIT(12)
81 #define NFC_RAM_METHOD BIT(14)
82 #define NFC_DEBUG_CTL BIT(31)
84 /* define bit use in NFC_ST */
85 #define NFC_RB_B2R BIT(0)
86 #define NFC_CMD_INT_FLAG BIT(1)
87 #define NFC_DMA_INT_FLAG BIT(2)
88 #define NFC_CMD_FIFO_STATUS BIT(3)
89 #define NFC_STA BIT(4)
90 #define NFC_NATCH_INT_FLAG BIT(5)
91 #define NFC_RB_STATE(x) BIT(x + 8)
93 /* define bit use in NFC_INT */
94 #define NFC_B2R_INT_ENABLE BIT(0)
95 #define NFC_CMD_INT_ENABLE BIT(1)
96 #define NFC_DMA_INT_ENABLE BIT(2)
97 #define NFC_INT_MASK (NFC_B2R_INT_ENABLE | \
98 NFC_CMD_INT_ENABLE | \
101 /* define bit use in NFC_TIMING_CTL */
102 #define NFC_TIMING_CTL_EDO BIT(8)
104 /* define NFC_TIMING_CFG register layout */
105 #define NFC_TIMING_CFG(tWB, tADL, tWHR, tRHW, tCAD) \
106 (((tWB) & 0x3) | (((tADL) & 0x3) << 2) | \
107 (((tWHR) & 0x3) << 4) | (((tRHW) & 0x3) << 6) | \
108 (((tCAD) & 0x7) << 8))
110 /* define bit use in NFC_CMD */
111 #define NFC_CMD_LOW_BYTE_MSK 0xff
112 #define NFC_CMD_HIGH_BYTE_MSK (0xff << 8)
113 #define NFC_CMD(x) (x)
114 #define NFC_ADR_NUM_MSK (0x7 << 16)
115 #define NFC_ADR_NUM(x) (((x) - 1) << 16)
116 #define NFC_SEND_ADR BIT(19)
117 #define NFC_ACCESS_DIR BIT(20)
118 #define NFC_DATA_TRANS BIT(21)
119 #define NFC_SEND_CMD1 BIT(22)
120 #define NFC_WAIT_FLAG BIT(23)
121 #define NFC_SEND_CMD2 BIT(24)
122 #define NFC_SEQ BIT(25)
123 #define NFC_DATA_SWAP_METHOD BIT(26)
124 #define NFC_ROW_AUTO_INC BIT(27)
125 #define NFC_SEND_CMD3 BIT(28)
126 #define NFC_SEND_CMD4 BIT(29)
127 #define NFC_CMD_TYPE_MSK (0x3 << 30)
128 #define NFC_NORMAL_OP (0 << 30)
129 #define NFC_ECC_OP (1 << 30)
130 #define NFC_PAGE_OP (2 << 30)
132 /* define bit use in NFC_RCMD_SET */
133 #define NFC_READ_CMD_MSK 0xff
134 #define NFC_RND_READ_CMD0_MSK (0xff << 8)
135 #define NFC_RND_READ_CMD1_MSK (0xff << 16)
137 /* define bit use in NFC_WCMD_SET */
138 #define NFC_PROGRAM_CMD_MSK 0xff
139 #define NFC_RND_WRITE_CMD_MSK (0xff << 8)
140 #define NFC_READ_CMD0_MSK (0xff << 16)
141 #define NFC_READ_CMD1_MSK (0xff << 24)
143 /* define bit use in NFC_ECC_CTL */
144 #define NFC_ECC_EN BIT(0)
145 #define NFC_ECC_PIPELINE BIT(3)
146 #define NFC_ECC_EXCEPTION BIT(4)
147 #define NFC_ECC_BLOCK_SIZE_MSK BIT(5)
148 #define NFC_ECC_BLOCK_512 (1 << 5)
149 #define NFC_RANDOM_EN BIT(9)
150 #define NFC_RANDOM_DIRECTION BIT(10)
151 #define NFC_ECC_MODE_MSK (0xf << 12)
152 #define NFC_ECC_MODE(x) ((x) << 12)
153 #define NFC_RANDOM_SEED_MSK (0x7fff << 16)
154 #define NFC_RANDOM_SEED(x) ((x) << 16)
156 /* define bit use in NFC_ECC_ST */
157 #define NFC_ECC_ERR(x) BIT(x)
158 #define NFC_ECC_PAT_FOUND(x) BIT(x + 16)
159 #define NFC_ECC_ERR_CNT(b, x) (((x) >> ((b) * 8)) & 0xff)
161 #define NFC_DEFAULT_TIMEOUT_MS 1000
163 #define NFC_SRAM_SIZE 1024
168 * Ready/Busy detection type: describes the Ready/Busy detection modes
170 * @RB_NONE: no external detection available, rely on STATUS command
171 * and software timeouts
172 * @RB_NATIVE: use sunxi NAND controller Ready/Busy support. The Ready/Busy
173 * pin of the NAND flash chip must be connected to one of the
174 * native NAND R/B pins (those which can be muxed to the NAND
176 * @RB_GPIO: use a simple GPIO to handle Ready/Busy status. The Ready/Busy
177 * pin of the NAND flash chip must be connected to a GPIO capable
180 enum sunxi_nand_rb_type {
187 * Ready/Busy structure: stores information related to Ready/Busy detection
189 * @type: the Ready/Busy detection mode
190 * @info: information related to the R/B detection mode. Either a gpio
191 * id or a native R/B id (those supported by the NAND controller).
193 struct sunxi_nand_rb {
194 enum sunxi_nand_rb_type type;
196 struct gpio_desc gpio;
202 * Chip Select structure: stores information related to NAND Chip Select
204 * @cs: the NAND CS id used to communicate with a NAND Chip
205 * @rb: the Ready/Busy description
207 struct sunxi_nand_chip_sel {
209 struct sunxi_nand_rb rb;
213 * sunxi HW ECC infos: stores information related to HW ECC support
215 * @mode: the sunxi ECC mode field deduced from ECC requirements
216 * @layout: the OOB layout depending on the ECC requirements and the
219 struct sunxi_nand_hw_ecc {
221 struct nand_ecclayout layout;
225 * NAND chip structure: stores NAND chip device related information
227 * @node: used to store NAND chips into a list
228 * @nand: base NAND chip structure
229 * @mtd: base MTD structure
230 * @clk_rate: clk_rate required for this NAND chip
231 * @timing_cfg TIMING_CFG register value for this NAND chip
232 * @selected: current active CS
233 * @nsels: number of CS lines required by the NAND chip
234 * @sels: array of CS lines descriptions
236 struct sunxi_nand_chip {
237 struct list_head node;
238 struct nand_chip nand;
239 unsigned long clk_rate;
248 struct sunxi_nand_chip_sel sels[0];
251 static inline struct sunxi_nand_chip *to_sunxi_nand(struct nand_chip *nand)
253 return container_of(nand, struct sunxi_nand_chip, nand);
257 * NAND Controller structure: stores sunxi NAND controller information
259 * @controller: base controller structure
260 * @dev: parent device (used to print error messages)
261 * @regs: NAND controller registers
262 * @ahb_clk: NAND Controller AHB clock
263 * @mod_clk: NAND Controller mod clock
264 * @assigned_cs: bitmask describing already assigned CS lines
265 * @clk_rate: NAND controller current clock rate
266 * @chips: a list containing all the NAND chips attached to
267 * this NAND controller
268 * @complete: a completion object used to wait for NAND
272 struct nand_hw_control controller;
277 unsigned long assigned_cs;
278 unsigned long clk_rate;
279 struct list_head chips;
282 static inline struct sunxi_nfc *to_sunxi_nfc(struct nand_hw_control *ctrl)
284 return container_of(ctrl, struct sunxi_nfc, controller);
287 static void sunxi_nfc_set_clk_rate(unsigned long hz)
289 struct sunxi_ccm_reg *const ccm =
290 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
293 div_m = (clock_get_pll6() + hz - 1) / hz;
294 for (div_n = 0; div_n < 3 && div_m > 16; div_n++) {
302 /* config mod clock */
303 writel(CCM_NAND_CTRL_ENABLE | CCM_NAND_CTRL_PLL6 |
304 CCM_NAND_CTRL_N(div_n) | CCM_NAND_CTRL_M(div_m),
305 &ccm->nand0_clk_cfg);
307 /* gate on nand clock */
308 setbits_le32(&ccm->ahb_gate0, (1 << AHB_GATE_OFFSET_NAND0));
309 #ifdef CONFIG_MACH_SUN9I
310 setbits_le32(&ccm->ahb_gate1, (1 << AHB_GATE_OFFSET_DMA));
312 setbits_le32(&ccm->ahb_gate0, (1 << AHB_GATE_OFFSET_DMA));
316 static int sunxi_nfc_wait_int(struct sunxi_nfc *nfc, u32 flags,
317 unsigned int timeout_ms)
319 unsigned int timeout_ticks;
320 u32 time_start, status;
321 int ret = -ETIMEDOUT;
324 timeout_ms = NFC_DEFAULT_TIMEOUT_MS;
326 timeout_ticks = (timeout_ms * CONFIG_SYS_HZ) / 1000;
328 time_start = get_timer(0);
331 status = readl(nfc->regs + NFC_REG_ST);
332 if ((status & flags) == flags) {
338 } while (get_timer(time_start) < timeout_ticks);
340 writel(status & flags, nfc->regs + NFC_REG_ST);
345 static int sunxi_nfc_wait_cmd_fifo_empty(struct sunxi_nfc *nfc)
347 unsigned long timeout = (CONFIG_SYS_HZ *
348 NFC_DEFAULT_TIMEOUT_MS) / 1000;
351 time_start = get_timer(0);
353 if (!(readl(nfc->regs + NFC_REG_ST) & NFC_CMD_FIFO_STATUS))
355 } while (get_timer(time_start) < timeout);
357 dev_err(nfc->dev, "wait for empty cmd FIFO timedout\n");
361 static int sunxi_nfc_rst(struct sunxi_nfc *nfc)
363 unsigned long timeout = (CONFIG_SYS_HZ *
364 NFC_DEFAULT_TIMEOUT_MS) / 1000;
367 writel(0, nfc->regs + NFC_REG_ECC_CTL);
368 writel(NFC_RESET, nfc->regs + NFC_REG_CTL);
370 time_start = get_timer(0);
372 if (!(readl(nfc->regs + NFC_REG_CTL) & NFC_RESET))
374 } while (get_timer(time_start) < timeout);
376 dev_err(nfc->dev, "wait for NAND controller reset timedout\n");
380 static int sunxi_nfc_dev_ready(struct mtd_info *mtd)
382 struct nand_chip *nand = mtd_to_nand(mtd);
383 struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
384 struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
385 struct sunxi_nand_rb *rb;
386 unsigned long timeo = (sunxi_nand->nand.state == FL_ERASING ? 400 : 20);
389 if (sunxi_nand->selected < 0)
392 rb = &sunxi_nand->sels[sunxi_nand->selected].rb;
396 ret = !!(readl(nfc->regs + NFC_REG_ST) &
397 NFC_RB_STATE(rb->info.nativeid));
401 sunxi_nfc_wait_int(nfc, NFC_RB_B2R, timeo);
402 ret = !!(readl(nfc->regs + NFC_REG_ST) &
403 NFC_RB_STATE(rb->info.nativeid));
406 ret = dm_gpio_get_value(&rb->info.gpio);
411 dev_err(nfc->dev, "cannot check R/B NAND status!\n");
418 static void sunxi_nfc_select_chip(struct mtd_info *mtd, int chip)
420 struct nand_chip *nand = mtd_to_nand(mtd);
421 struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
422 struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
423 struct sunxi_nand_chip_sel *sel;
426 if (chip > 0 && chip >= sunxi_nand->nsels)
429 if (chip == sunxi_nand->selected)
432 ctl = readl(nfc->regs + NFC_REG_CTL) &
433 ~(NFC_PAGE_SHIFT_MSK | NFC_CE_SEL_MSK | NFC_RB_SEL_MSK | NFC_EN);
436 sel = &sunxi_nand->sels[chip];
438 ctl |= NFC_CE_SEL(sel->cs) | NFC_EN |
439 NFC_PAGE_SHIFT(nand->page_shift - 10);
440 if (sel->rb.type == RB_NONE) {
441 nand->dev_ready = NULL;
443 nand->dev_ready = sunxi_nfc_dev_ready;
444 if (sel->rb.type == RB_NATIVE)
445 ctl |= NFC_RB_SEL(sel->rb.info.nativeid);
448 writel(mtd->writesize, nfc->regs + NFC_REG_SPARE_AREA);
450 if (nfc->clk_rate != sunxi_nand->clk_rate) {
451 sunxi_nfc_set_clk_rate(sunxi_nand->clk_rate);
452 nfc->clk_rate = sunxi_nand->clk_rate;
456 writel(sunxi_nand->timing_ctl, nfc->regs + NFC_REG_TIMING_CTL);
457 writel(sunxi_nand->timing_cfg, nfc->regs + NFC_REG_TIMING_CFG);
458 writel(ctl, nfc->regs + NFC_REG_CTL);
460 sunxi_nand->selected = chip;
463 static void sunxi_nfc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
465 struct nand_chip *nand = mtd_to_nand(mtd);
466 struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
467 struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
474 cnt = min(len - offs, NFC_SRAM_SIZE);
476 ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
480 writel(cnt, nfc->regs + NFC_REG_CNT);
481 tmp = NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD;
482 writel(tmp, nfc->regs + NFC_REG_CMD);
484 ret = sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
489 memcpy_fromio(buf + offs, nfc->regs + NFC_RAM0_BASE,
495 static void sunxi_nfc_write_buf(struct mtd_info *mtd, const uint8_t *buf,
498 struct nand_chip *nand = mtd_to_nand(mtd);
499 struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
500 struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
507 cnt = min(len - offs, NFC_SRAM_SIZE);
509 ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
513 writel(cnt, nfc->regs + NFC_REG_CNT);
514 memcpy_toio(nfc->regs + NFC_RAM0_BASE, buf + offs, cnt);
515 tmp = NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD |
517 writel(tmp, nfc->regs + NFC_REG_CMD);
519 ret = sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
527 static uint8_t sunxi_nfc_read_byte(struct mtd_info *mtd)
531 sunxi_nfc_read_buf(mtd, &ret, 1);
536 static void sunxi_nfc_cmd_ctrl(struct mtd_info *mtd, int dat,
539 struct nand_chip *nand = mtd_to_nand(mtd);
540 struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
541 struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
545 ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
549 if (ctrl & NAND_CTRL_CHANGE) {
550 tmp = readl(nfc->regs + NFC_REG_CTL);
555 writel(tmp, nfc->regs + NFC_REG_CTL);
558 if (dat == NAND_CMD_NONE && (ctrl & NAND_NCE) &&
559 !(ctrl & (NAND_CLE | NAND_ALE))) {
562 if (!sunxi_nand->addr_cycles && !sunxi_nand->cmd_cycles)
565 if (sunxi_nand->cmd_cycles--)
566 cmd |= NFC_SEND_CMD1 | sunxi_nand->cmd[0];
568 if (sunxi_nand->cmd_cycles--) {
569 cmd |= NFC_SEND_CMD2;
570 writel(sunxi_nand->cmd[1],
571 nfc->regs + NFC_REG_RCMD_SET);
574 sunxi_nand->cmd_cycles = 0;
576 if (sunxi_nand->addr_cycles) {
577 cmd |= NFC_SEND_ADR |
578 NFC_ADR_NUM(sunxi_nand->addr_cycles);
579 writel(sunxi_nand->addr[0],
580 nfc->regs + NFC_REG_ADDR_LOW);
583 if (sunxi_nand->addr_cycles > 4)
584 writel(sunxi_nand->addr[1],
585 nfc->regs + NFC_REG_ADDR_HIGH);
587 writel(cmd, nfc->regs + NFC_REG_CMD);
588 sunxi_nand->addr[0] = 0;
589 sunxi_nand->addr[1] = 0;
590 sunxi_nand->addr_cycles = 0;
591 sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
594 if (ctrl & NAND_CLE) {
595 sunxi_nand->cmd[sunxi_nand->cmd_cycles++] = dat;
596 } else if (ctrl & NAND_ALE) {
597 sunxi_nand->addr[sunxi_nand->addr_cycles / 4] |=
598 dat << ((sunxi_nand->addr_cycles % 4) * 8);
599 sunxi_nand->addr_cycles++;
603 /* These seed values have been extracted from Allwinner's BSP */
604 static const u16 sunxi_nfc_randomizer_page_seeds[] = {
605 0x2b75, 0x0bd0, 0x5ca3, 0x62d1, 0x1c93, 0x07e9, 0x2162, 0x3a72,
606 0x0d67, 0x67f9, 0x1be7, 0x077d, 0x032f, 0x0dac, 0x2716, 0x2436,
607 0x7922, 0x1510, 0x3860, 0x5287, 0x480f, 0x4252, 0x1789, 0x5a2d,
608 0x2a49, 0x5e10, 0x437f, 0x4b4e, 0x2f45, 0x216e, 0x5cb7, 0x7130,
609 0x2a3f, 0x60e4, 0x4dc9, 0x0ef0, 0x0f52, 0x1bb9, 0x6211, 0x7a56,
610 0x226d, 0x4ea7, 0x6f36, 0x3692, 0x38bf, 0x0c62, 0x05eb, 0x4c55,
611 0x60f4, 0x728c, 0x3b6f, 0x2037, 0x7f69, 0x0936, 0x651a, 0x4ceb,
612 0x6218, 0x79f3, 0x383f, 0x18d9, 0x4f05, 0x5c82, 0x2912, 0x6f17,
613 0x6856, 0x5938, 0x1007, 0x61ab, 0x3e7f, 0x57c2, 0x542f, 0x4f62,
614 0x7454, 0x2eac, 0x7739, 0x42d4, 0x2f90, 0x435a, 0x2e52, 0x2064,
615 0x637c, 0x66ad, 0x2c90, 0x0bad, 0x759c, 0x0029, 0x0986, 0x7126,
616 0x1ca7, 0x1605, 0x386a, 0x27f5, 0x1380, 0x6d75, 0x24c3, 0x0f8e,
617 0x2b7a, 0x1418, 0x1fd1, 0x7dc1, 0x2d8e, 0x43af, 0x2267, 0x7da3,
618 0x4e3d, 0x1338, 0x50db, 0x454d, 0x764d, 0x40a3, 0x42e6, 0x262b,
619 0x2d2e, 0x1aea, 0x2e17, 0x173d, 0x3a6e, 0x71bf, 0x25f9, 0x0a5d,
620 0x7c57, 0x0fbe, 0x46ce, 0x4939, 0x6b17, 0x37bb, 0x3e91, 0x76db,
624 * sunxi_nfc_randomizer_ecc512_seeds and sunxi_nfc_randomizer_ecc1024_seeds
625 * have been generated using
626 * sunxi_nfc_randomizer_step(seed, (step_size * 8) + 15), which is what
627 * the randomizer engine does internally before de/scrambling OOB data.
629 * Those tables are statically defined to avoid calculating randomizer state
632 static const u16 sunxi_nfc_randomizer_ecc512_seeds[] = {
633 0x3346, 0x367f, 0x1f18, 0x769a, 0x4f64, 0x068c, 0x2ef1, 0x6b64,
634 0x28a9, 0x15d7, 0x30f8, 0x3659, 0x53db, 0x7c5f, 0x71d4, 0x4409,
635 0x26eb, 0x03cc, 0x655d, 0x47d4, 0x4daa, 0x0877, 0x712d, 0x3617,
636 0x3264, 0x49aa, 0x7f9e, 0x588e, 0x4fbc, 0x7176, 0x7f91, 0x6c6d,
637 0x4b95, 0x5fb7, 0x3844, 0x4037, 0x0184, 0x081b, 0x0ee8, 0x5b91,
638 0x293d, 0x1f71, 0x0e6f, 0x402b, 0x5122, 0x1e52, 0x22be, 0x3d2d,
639 0x75bc, 0x7c60, 0x6291, 0x1a2f, 0x61d4, 0x74aa, 0x4140, 0x29ab,
640 0x472d, 0x2852, 0x017e, 0x15e8, 0x5ec2, 0x17cf, 0x7d0f, 0x06b8,
641 0x117a, 0x6b94, 0x789b, 0x3126, 0x6ac5, 0x5be7, 0x150f, 0x51f8,
642 0x7889, 0x0aa5, 0x663d, 0x77e8, 0x0b87, 0x3dcb, 0x360d, 0x218b,
643 0x512f, 0x7dc9, 0x6a4d, 0x630a, 0x3547, 0x1dd2, 0x5aea, 0x69a5,
644 0x7bfa, 0x5e4f, 0x1519, 0x6430, 0x3a0e, 0x5eb3, 0x5425, 0x0c7a,
645 0x5540, 0x3670, 0x63c1, 0x31e9, 0x5a39, 0x2de7, 0x5979, 0x2891,
646 0x1562, 0x014b, 0x5b05, 0x2756, 0x5a34, 0x13aa, 0x6cb5, 0x2c36,
647 0x5e72, 0x1306, 0x0861, 0x15ef, 0x1ee8, 0x5a37, 0x7ac4, 0x45dd,
648 0x44c4, 0x7266, 0x2f41, 0x3ccc, 0x045e, 0x7d40, 0x7c66, 0x0fa0,
651 static const u16 sunxi_nfc_randomizer_ecc1024_seeds[] = {
652 0x2cf5, 0x35f1, 0x63a4, 0x5274, 0x2bd2, 0x778b, 0x7285, 0x32b6,
653 0x6a5c, 0x70d6, 0x757d, 0x6769, 0x5375, 0x1e81, 0x0cf3, 0x3982,
654 0x6787, 0x042a, 0x6c49, 0x1925, 0x56a8, 0x40a9, 0x063e, 0x7bd9,
655 0x4dbf, 0x55ec, 0x672e, 0x7334, 0x5185, 0x4d00, 0x232a, 0x7e07,
656 0x445d, 0x6b92, 0x528f, 0x4255, 0x53ba, 0x7d82, 0x2a2e, 0x3a4e,
657 0x75eb, 0x450c, 0x6844, 0x1b5d, 0x581a, 0x4cc6, 0x0379, 0x37b2,
658 0x419f, 0x0e92, 0x6b27, 0x5624, 0x01e3, 0x07c1, 0x44a5, 0x130c,
659 0x13e8, 0x5910, 0x0876, 0x60c5, 0x54e3, 0x5b7f, 0x2269, 0x509f,
660 0x7665, 0x36fd, 0x3e9a, 0x0579, 0x6295, 0x14ef, 0x0a81, 0x1bcc,
661 0x4b16, 0x64db, 0x0514, 0x4f07, 0x0591, 0x3576, 0x6853, 0x0d9e,
662 0x259f, 0x38b7, 0x64fb, 0x3094, 0x4693, 0x6ddd, 0x29bb, 0x0bc8,
663 0x3f47, 0x490e, 0x0c0e, 0x7933, 0x3c9e, 0x5840, 0x398d, 0x3e68,
664 0x4af1, 0x71f5, 0x57cf, 0x1121, 0x64eb, 0x3579, 0x15ac, 0x584d,
665 0x5f2a, 0x47e2, 0x6528, 0x6eac, 0x196e, 0x6b96, 0x0450, 0x0179,
666 0x609c, 0x06e1, 0x4626, 0x42c7, 0x273e, 0x486f, 0x0705, 0x1601,
667 0x145b, 0x407e, 0x062b, 0x57a5, 0x53f9, 0x5659, 0x4410, 0x3ccd,
670 static u16 sunxi_nfc_randomizer_step(u16 state, int count)
675 * This loop is just a simple implementation of a Fibonacci LFSR using
676 * the x16 + x15 + 1 polynomial.
679 state = ((state >> 1) |
680 (((state ^ (state >> 1)) & 1) << 14)) & 0x7fff;
685 static u16 sunxi_nfc_randomizer_state(struct mtd_info *mtd, int page, bool ecc)
687 const u16 *seeds = sunxi_nfc_randomizer_page_seeds;
688 int mod = mtd->erasesize / mtd->writesize;
690 if (mod > ARRAY_SIZE(sunxi_nfc_randomizer_page_seeds))
691 mod = ARRAY_SIZE(sunxi_nfc_randomizer_page_seeds);
694 if (mtd->ecc_step_size == 512)
695 seeds = sunxi_nfc_randomizer_ecc512_seeds;
697 seeds = sunxi_nfc_randomizer_ecc1024_seeds;
700 return seeds[page % mod];
703 static void sunxi_nfc_randomizer_config(struct mtd_info *mtd,
706 struct nand_chip *nand = mtd_to_nand(mtd);
707 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
708 u32 ecc_ctl = readl(nfc->regs + NFC_REG_ECC_CTL);
711 if (!(nand->options & NAND_NEED_SCRAMBLING))
714 ecc_ctl = readl(nfc->regs + NFC_REG_ECC_CTL);
715 state = sunxi_nfc_randomizer_state(mtd, page, ecc);
716 ecc_ctl = readl(nfc->regs + NFC_REG_ECC_CTL) & ~NFC_RANDOM_SEED_MSK;
717 writel(ecc_ctl | NFC_RANDOM_SEED(state), nfc->regs + NFC_REG_ECC_CTL);
720 static void sunxi_nfc_randomizer_enable(struct mtd_info *mtd)
722 struct nand_chip *nand = mtd_to_nand(mtd);
723 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
725 if (!(nand->options & NAND_NEED_SCRAMBLING))
728 writel(readl(nfc->regs + NFC_REG_ECC_CTL) | NFC_RANDOM_EN,
729 nfc->regs + NFC_REG_ECC_CTL);
732 static void sunxi_nfc_randomizer_disable(struct mtd_info *mtd)
734 struct nand_chip *nand = mtd_to_nand(mtd);
735 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
737 if (!(nand->options & NAND_NEED_SCRAMBLING))
740 writel(readl(nfc->regs + NFC_REG_ECC_CTL) & ~NFC_RANDOM_EN,
741 nfc->regs + NFC_REG_ECC_CTL);
744 static void sunxi_nfc_randomize_bbm(struct mtd_info *mtd, int page, u8 *bbm)
746 u16 state = sunxi_nfc_randomizer_state(mtd, page, true);
749 bbm[1] ^= sunxi_nfc_randomizer_step(state, 8);
752 static void sunxi_nfc_randomizer_write_buf(struct mtd_info *mtd,
753 const uint8_t *buf, int len,
756 sunxi_nfc_randomizer_config(mtd, page, ecc);
757 sunxi_nfc_randomizer_enable(mtd);
758 sunxi_nfc_write_buf(mtd, buf, len);
759 sunxi_nfc_randomizer_disable(mtd);
762 static void sunxi_nfc_randomizer_read_buf(struct mtd_info *mtd, uint8_t *buf,
763 int len, bool ecc, int page)
765 sunxi_nfc_randomizer_config(mtd, page, ecc);
766 sunxi_nfc_randomizer_enable(mtd);
767 sunxi_nfc_read_buf(mtd, buf, len);
768 sunxi_nfc_randomizer_disable(mtd);
771 static void sunxi_nfc_hw_ecc_enable(struct mtd_info *mtd)
773 struct nand_chip *nand = mtd_to_nand(mtd);
774 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
775 struct sunxi_nand_hw_ecc *data = nand->ecc.priv;
778 ecc_ctl = readl(nfc->regs + NFC_REG_ECC_CTL);
779 ecc_ctl &= ~(NFC_ECC_MODE_MSK | NFC_ECC_PIPELINE |
780 NFC_ECC_BLOCK_SIZE_MSK);
781 ecc_ctl |= NFC_ECC_EN | NFC_ECC_MODE(data->mode) | NFC_ECC_EXCEPTION;
783 if (nand->ecc.size == 512)
784 ecc_ctl |= NFC_ECC_BLOCK_512;
786 writel(ecc_ctl, nfc->regs + NFC_REG_ECC_CTL);
789 static void sunxi_nfc_hw_ecc_disable(struct mtd_info *mtd)
791 struct nand_chip *nand = mtd_to_nand(mtd);
792 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
794 writel(readl(nfc->regs + NFC_REG_ECC_CTL) & ~NFC_ECC_EN,
795 nfc->regs + NFC_REG_ECC_CTL);
798 static inline void sunxi_nfc_user_data_to_buf(u32 user_data, u8 *buf)
801 buf[1] = user_data >> 8;
802 buf[2] = user_data >> 16;
803 buf[3] = user_data >> 24;
806 static int sunxi_nfc_hw_ecc_read_chunk(struct mtd_info *mtd,
807 u8 *data, int data_off,
808 u8 *oob, int oob_off,
810 unsigned int *max_bitflips,
813 struct nand_chip *nand = mtd_to_nand(mtd);
814 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
815 struct nand_ecc_ctrl *ecc = &nand->ecc;
820 if (*cur_off != data_off)
821 nand->cmdfunc(mtd, NAND_CMD_RNDOUT, data_off, -1);
823 sunxi_nfc_randomizer_read_buf(mtd, NULL, ecc->size, false, page);
825 if (data_off + ecc->size != oob_off)
826 nand->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_off, -1);
828 ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
832 sunxi_nfc_randomizer_enable(mtd);
833 writel(NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD | NFC_ECC_OP,
834 nfc->regs + NFC_REG_CMD);
836 ret = sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
837 sunxi_nfc_randomizer_disable(mtd);
841 *cur_off = oob_off + ecc->bytes + 4;
843 status = readl(nfc->regs + NFC_REG_ECC_ST);
844 if (status & NFC_ECC_PAT_FOUND(0)) {
847 if (unlikely(!(readl(nfc->regs + NFC_REG_PAT_ID) & 0x1)))
850 memset(data, pattern, ecc->size);
851 memset(oob, pattern, ecc->bytes + 4);
856 ret = NFC_ECC_ERR_CNT(0, readl(nfc->regs + NFC_REG_ECC_ERR_CNT(0)));
858 memcpy_fromio(data, nfc->regs + NFC_RAM0_BASE, ecc->size);
860 nand->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_off, -1);
861 sunxi_nfc_randomizer_read_buf(mtd, oob, ecc->bytes + 4, true, page);
863 if (status & NFC_ECC_ERR(0)) {
865 * Re-read the data with the randomizer disabled to identify
866 * bitflips in erased pages.
868 if (nand->options & NAND_NEED_SCRAMBLING) {
869 nand->cmdfunc(mtd, NAND_CMD_RNDOUT, data_off, -1);
870 nand->read_buf(mtd, data, ecc->size);
871 nand->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_off, -1);
872 nand->read_buf(mtd, oob, ecc->bytes + 4);
875 ret = nand_check_erased_ecc_chunk(data, ecc->size,
877 NULL, 0, ecc->strength);
882 * The engine protects 4 bytes of OOB data per chunk.
883 * Retrieve the corrected OOB bytes.
885 sunxi_nfc_user_data_to_buf(readl(nfc->regs +
886 NFC_REG_USER_DATA(0)),
889 /* De-randomize the Bad Block Marker. */
890 if (bbm && nand->options & NAND_NEED_SCRAMBLING)
891 sunxi_nfc_randomize_bbm(mtd, page, oob);
895 mtd->ecc_stats.failed++;
897 mtd->ecc_stats.corrected += ret;
898 *max_bitflips = max_t(unsigned int, *max_bitflips, ret);
904 static void sunxi_nfc_hw_ecc_read_extra_oob(struct mtd_info *mtd,
905 u8 *oob, int *cur_off,
906 bool randomize, int page)
908 struct nand_chip *nand = mtd_to_nand(mtd);
909 struct nand_ecc_ctrl *ecc = &nand->ecc;
910 int offset = ((ecc->bytes + 4) * ecc->steps);
911 int len = mtd->oobsize - offset;
916 if (*cur_off != offset)
917 nand->cmdfunc(mtd, NAND_CMD_RNDOUT,
918 offset + mtd->writesize, -1);
921 sunxi_nfc_read_buf(mtd, oob + offset, len);
923 sunxi_nfc_randomizer_read_buf(mtd, oob + offset, len,
926 *cur_off = mtd->oobsize + mtd->writesize;
929 static inline u32 sunxi_nfc_buf_to_user_data(const u8 *buf)
931 return buf[0] | (buf[1] << 8) | (buf[2] << 16) | (buf[3] << 24);
934 static int sunxi_nfc_hw_ecc_write_chunk(struct mtd_info *mtd,
935 const u8 *data, int data_off,
936 const u8 *oob, int oob_off,
937 int *cur_off, bool bbm,
940 struct nand_chip *nand = mtd_to_nand(mtd);
941 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
942 struct nand_ecc_ctrl *ecc = &nand->ecc;
945 if (data_off != *cur_off)
946 nand->cmdfunc(mtd, NAND_CMD_RNDIN, data_off, -1);
948 sunxi_nfc_randomizer_write_buf(mtd, data, ecc->size, false, page);
950 /* Fill OOB data in */
951 if ((nand->options & NAND_NEED_SCRAMBLING) && bbm) {
954 memcpy(user_data, oob, 4);
955 sunxi_nfc_randomize_bbm(mtd, page, user_data);
956 writel(sunxi_nfc_buf_to_user_data(user_data),
957 nfc->regs + NFC_REG_USER_DATA(0));
959 writel(sunxi_nfc_buf_to_user_data(oob),
960 nfc->regs + NFC_REG_USER_DATA(0));
963 if (data_off + ecc->size != oob_off)
964 nand->cmdfunc(mtd, NAND_CMD_RNDIN, oob_off, -1);
966 ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
970 sunxi_nfc_randomizer_enable(mtd);
971 writel(NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD |
972 NFC_ACCESS_DIR | NFC_ECC_OP,
973 nfc->regs + NFC_REG_CMD);
975 ret = sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
976 sunxi_nfc_randomizer_disable(mtd);
980 *cur_off = oob_off + ecc->bytes + 4;
985 static void sunxi_nfc_hw_ecc_write_extra_oob(struct mtd_info *mtd,
986 u8 *oob, int *cur_off,
989 struct nand_chip *nand = mtd_to_nand(mtd);
990 struct nand_ecc_ctrl *ecc = &nand->ecc;
991 int offset = ((ecc->bytes + 4) * ecc->steps);
992 int len = mtd->oobsize - offset;
997 if (*cur_off != offset)
998 nand->cmdfunc(mtd, NAND_CMD_RNDIN,
999 offset + mtd->writesize, -1);
1001 sunxi_nfc_randomizer_write_buf(mtd, oob + offset, len, false, page);
1003 *cur_off = mtd->oobsize + mtd->writesize;
1006 static int sunxi_nfc_hw_ecc_read_page(struct mtd_info *mtd,
1007 struct nand_chip *chip, uint8_t *buf,
1008 int oob_required, int page)
1010 struct nand_ecc_ctrl *ecc = &chip->ecc;
1011 unsigned int max_bitflips = 0;
1012 int ret, i, cur_off = 0;
1013 bool raw_mode = false;
1015 sunxi_nfc_hw_ecc_enable(mtd);
1017 for (i = 0; i < ecc->steps; i++) {
1018 int data_off = i * ecc->size;
1019 int oob_off = i * (ecc->bytes + 4);
1020 u8 *data = buf + data_off;
1021 u8 *oob = chip->oob_poi + oob_off;
1023 ret = sunxi_nfc_hw_ecc_read_chunk(mtd, data, data_off, oob,
1024 oob_off + mtd->writesize,
1025 &cur_off, &max_bitflips,
1034 sunxi_nfc_hw_ecc_read_extra_oob(mtd, chip->oob_poi, &cur_off,
1037 sunxi_nfc_hw_ecc_disable(mtd);
1039 return max_bitflips;
1042 static int sunxi_nfc_hw_ecc_read_subpage(struct mtd_info *mtd,
1043 struct nand_chip *chip,
1044 uint32_t data_offs, uint32_t readlen,
1045 uint8_t *bufpoi, int page)
1047 struct nand_ecc_ctrl *ecc = &chip->ecc;
1048 int ret, i, cur_off = 0;
1049 unsigned int max_bitflips = 0;
1051 sunxi_nfc_hw_ecc_enable(mtd);
1053 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1054 for (i = data_offs / ecc->size;
1055 i < DIV_ROUND_UP(data_offs + readlen, ecc->size); i++) {
1056 int data_off = i * ecc->size;
1057 int oob_off = i * (ecc->bytes + 4);
1058 u8 *data = bufpoi + data_off;
1059 u8 *oob = chip->oob_poi + oob_off;
1061 ret = sunxi_nfc_hw_ecc_read_chunk(mtd, data, data_off,
1062 oob, oob_off + mtd->writesize,
1063 &cur_off, &max_bitflips, !i, page);
1068 sunxi_nfc_hw_ecc_disable(mtd);
1070 return max_bitflips;
1073 static int sunxi_nfc_hw_ecc_write_page(struct mtd_info *mtd,
1074 struct nand_chip *chip,
1075 const uint8_t *buf, int oob_required,
1078 struct nand_ecc_ctrl *ecc = &chip->ecc;
1079 int ret, i, cur_off = 0;
1081 sunxi_nfc_hw_ecc_enable(mtd);
1083 for (i = 0; i < ecc->steps; i++) {
1084 int data_off = i * ecc->size;
1085 int oob_off = i * (ecc->bytes + 4);
1086 const u8 *data = buf + data_off;
1087 const u8 *oob = chip->oob_poi + oob_off;
1089 ret = sunxi_nfc_hw_ecc_write_chunk(mtd, data, data_off, oob,
1090 oob_off + mtd->writesize,
1091 &cur_off, !i, page);
1096 if (oob_required || (chip->options & NAND_NEED_SCRAMBLING))
1097 sunxi_nfc_hw_ecc_write_extra_oob(mtd, chip->oob_poi,
1100 sunxi_nfc_hw_ecc_disable(mtd);
1105 static int sunxi_nfc_hw_ecc_write_subpage(struct mtd_info *mtd,
1106 struct nand_chip *chip,
1107 u32 data_offs, u32 data_len,
1108 const u8 *buf, int oob_required,
1111 struct nand_ecc_ctrl *ecc = &chip->ecc;
1112 int ret, i, cur_off = 0;
1114 sunxi_nfc_hw_ecc_enable(mtd);
1116 for (i = data_offs / ecc->size;
1117 i < DIV_ROUND_UP(data_offs + data_len, ecc->size); i++) {
1118 int data_off = i * ecc->size;
1119 int oob_off = i * (ecc->bytes + 4);
1120 const u8 *data = buf + data_off;
1121 const u8 *oob = chip->oob_poi + oob_off;
1123 ret = sunxi_nfc_hw_ecc_write_chunk(mtd, data, data_off, oob,
1124 oob_off + mtd->writesize,
1125 &cur_off, !i, page);
1130 sunxi_nfc_hw_ecc_disable(mtd);
1135 static int sunxi_nfc_hw_syndrome_ecc_read_page(struct mtd_info *mtd,
1136 struct nand_chip *chip,
1137 uint8_t *buf, int oob_required,
1140 struct nand_ecc_ctrl *ecc = &chip->ecc;
1141 unsigned int max_bitflips = 0;
1142 int ret, i, cur_off = 0;
1143 bool raw_mode = false;
1145 sunxi_nfc_hw_ecc_enable(mtd);
1147 for (i = 0; i < ecc->steps; i++) {
1148 int data_off = i * (ecc->size + ecc->bytes + 4);
1149 int oob_off = data_off + ecc->size;
1150 u8 *data = buf + (i * ecc->size);
1151 u8 *oob = chip->oob_poi + (i * (ecc->bytes + 4));
1153 ret = sunxi_nfc_hw_ecc_read_chunk(mtd, data, data_off, oob,
1155 &max_bitflips, !i, page);
1163 sunxi_nfc_hw_ecc_read_extra_oob(mtd, chip->oob_poi, &cur_off,
1166 sunxi_nfc_hw_ecc_disable(mtd);
1168 return max_bitflips;
1171 static int sunxi_nfc_hw_syndrome_ecc_write_page(struct mtd_info *mtd,
1172 struct nand_chip *chip,
1174 int oob_required, int page)
1176 struct nand_ecc_ctrl *ecc = &chip->ecc;
1177 int ret, i, cur_off = 0;
1179 sunxi_nfc_hw_ecc_enable(mtd);
1181 for (i = 0; i < ecc->steps; i++) {
1182 int data_off = i * (ecc->size + ecc->bytes + 4);
1183 int oob_off = data_off + ecc->size;
1184 const u8 *data = buf + (i * ecc->size);
1185 const u8 *oob = chip->oob_poi + (i * (ecc->bytes + 4));
1187 ret = sunxi_nfc_hw_ecc_write_chunk(mtd, data, data_off,
1188 oob, oob_off, &cur_off,
1194 if (oob_required || (chip->options & NAND_NEED_SCRAMBLING))
1195 sunxi_nfc_hw_ecc_write_extra_oob(mtd, chip->oob_poi,
1198 sunxi_nfc_hw_ecc_disable(mtd);
1203 static const s32 tWB_lut[] = {6, 12, 16, 20};
1204 static const s32 tRHW_lut[] = {4, 8, 12, 20};
1206 static int _sunxi_nand_lookup_timing(const s32 *lut, int lut_size, u32 duration,
1209 u32 clk_cycles = DIV_ROUND_UP(duration, clk_period);
1212 for (i = 0; i < lut_size; i++) {
1213 if (clk_cycles <= lut[i])
1221 #define sunxi_nand_lookup_timing(l, p, c) \
1222 _sunxi_nand_lookup_timing(l, ARRAY_SIZE(l), p, c)
1224 static int sunxi_nand_chip_set_timings(struct sunxi_nand_chip *chip,
1225 const struct nand_sdr_timings *timings)
1227 u32 min_clk_period = 0;
1228 s32 tWB, tADL, tWHR, tRHW, tCAD;
1231 if (timings->tCLS_min > min_clk_period)
1232 min_clk_period = timings->tCLS_min;
1235 if (timings->tCLH_min > min_clk_period)
1236 min_clk_period = timings->tCLH_min;
1239 if (timings->tCS_min > min_clk_period)
1240 min_clk_period = timings->tCS_min;
1243 if (timings->tCH_min > min_clk_period)
1244 min_clk_period = timings->tCH_min;
1247 if (timings->tWP_min > min_clk_period)
1248 min_clk_period = timings->tWP_min;
1251 if (timings->tWH_min > min_clk_period)
1252 min_clk_period = timings->tWH_min;
1255 if (timings->tALS_min > min_clk_period)
1256 min_clk_period = timings->tALS_min;
1259 if (timings->tDS_min > min_clk_period)
1260 min_clk_period = timings->tDS_min;
1263 if (timings->tDH_min > min_clk_period)
1264 min_clk_period = timings->tDH_min;
1267 if (timings->tRR_min > (min_clk_period * 3))
1268 min_clk_period = DIV_ROUND_UP(timings->tRR_min, 3);
1271 if (timings->tALH_min > min_clk_period)
1272 min_clk_period = timings->tALH_min;
1275 if (timings->tRP_min > min_clk_period)
1276 min_clk_period = timings->tRP_min;
1279 if (timings->tREH_min > min_clk_period)
1280 min_clk_period = timings->tREH_min;
1283 if (timings->tRC_min > (min_clk_period * 2))
1284 min_clk_period = DIV_ROUND_UP(timings->tRC_min, 2);
1287 if (timings->tWC_min > (min_clk_period * 2))
1288 min_clk_period = DIV_ROUND_UP(timings->tWC_min, 2);
1290 /* T16 - T19 + tCAD */
1291 tWB = sunxi_nand_lookup_timing(tWB_lut, timings->tWB_max,
1294 dev_err(nfc->dev, "unsupported tWB\n");
1298 tADL = DIV_ROUND_UP(timings->tADL_min, min_clk_period) >> 3;
1300 dev_err(nfc->dev, "unsupported tADL\n");
1304 tWHR = DIV_ROUND_UP(timings->tWHR_min, min_clk_period) >> 3;
1306 dev_err(nfc->dev, "unsupported tWHR\n");
1310 tRHW = sunxi_nand_lookup_timing(tRHW_lut, timings->tRHW_min,
1313 dev_err(nfc->dev, "unsupported tRHW\n");
1318 * TODO: according to ONFI specs this value only applies for DDR NAND,
1319 * but Allwinner seems to set this to 0x7. Mimic them for now.
1323 /* TODO: A83 has some more bits for CDQSS, CS, CLHZ, CCS, WC */
1324 chip->timing_cfg = NFC_TIMING_CFG(tWB, tADL, tWHR, tRHW, tCAD);
1327 * ONFI specification 3.1, paragraph 4.15.2 dictates that EDO data
1328 * output cycle timings shall be used if the host drives tRC less than
1331 chip->timing_ctl = (timings->tRC_min < 30000) ? NFC_TIMING_CTL_EDO : 0;
1333 /* Convert min_clk_period from picoseconds to nanoseconds */
1334 min_clk_period = DIV_ROUND_UP(min_clk_period, 1000);
1337 * Convert min_clk_period into a clk frequency, then get the
1338 * appropriate rate for the NAND controller IP given this formula
1339 * (specified in the datasheet):
1340 * nand clk_rate = min_clk_rate
1342 chip->clk_rate = 1000000000L / min_clk_period;
1347 static int sunxi_nand_chip_init_timings(struct sunxi_nand_chip *chip)
1349 struct mtd_info *mtd = nand_to_mtd(&chip->nand);
1350 const struct nand_sdr_timings *timings;
1354 mode = onfi_get_async_timing_mode(&chip->nand);
1355 if (mode == ONFI_TIMING_MODE_UNKNOWN) {
1356 mode = chip->nand.onfi_timing_mode_default;
1358 uint8_t feature[ONFI_SUBFEATURE_PARAM_LEN] = {};
1361 mode = fls(mode) - 1;
1366 for (i = 0; i < chip->nsels; i++) {
1367 chip->nand.select_chip(mtd, i);
1368 ret = chip->nand.onfi_set_features(mtd,
1370 ONFI_FEATURE_ADDR_TIMING_MODE,
1372 chip->nand.select_chip(mtd, -1);
1378 timings = onfi_async_timing_mode_to_sdr_timings(mode);
1379 if (IS_ERR(timings))
1380 return PTR_ERR(timings);
1382 return sunxi_nand_chip_set_timings(chip, timings);
1385 static int sunxi_nand_hw_common_ecc_ctrl_init(struct mtd_info *mtd,
1386 struct nand_ecc_ctrl *ecc)
1388 static const u8 strengths[] = { 16, 24, 28, 32, 40, 48, 56, 60, 64 };
1389 struct sunxi_nand_hw_ecc *data;
1390 struct nand_ecclayout *layout;
1395 data = kzalloc(sizeof(*data), GFP_KERNEL);
1399 if (ecc->size != 512 && ecc->size != 1024)
1402 /* Prefer 1k ECC chunk over 512 ones */
1403 if (ecc->size == 512 && mtd->writesize > 512) {
1408 /* Add ECC info retrieval from DT */
1409 for (i = 0; i < ARRAY_SIZE(strengths); i++) {
1410 if (ecc->strength <= strengths[i])
1414 if (i >= ARRAY_SIZE(strengths)) {
1415 dev_err(nfc->dev, "unsupported strength\n");
1422 /* HW ECC always request ECC bytes for 1024 bytes blocks */
1423 ecc->bytes = DIV_ROUND_UP(ecc->strength * fls(8 * 1024), 8);
1425 /* HW ECC always work with even numbers of ECC bytes */
1426 ecc->bytes = ALIGN(ecc->bytes, 2);
1428 layout = &data->layout;
1429 nsectors = mtd->writesize / ecc->size;
1431 if (mtd->oobsize < ((ecc->bytes + 4) * nsectors)) {
1436 layout->eccbytes = (ecc->bytes * nsectors);
1438 ecc->layout = layout;
1450 static void sunxi_nand_hw_common_ecc_ctrl_cleanup(struct nand_ecc_ctrl *ecc)
1454 #endif /* __UBOOT__ */
1456 static int sunxi_nand_hw_ecc_ctrl_init(struct mtd_info *mtd,
1457 struct nand_ecc_ctrl *ecc)
1459 struct nand_ecclayout *layout;
1464 ret = sunxi_nand_hw_common_ecc_ctrl_init(mtd, ecc);
1468 ecc->read_page = sunxi_nfc_hw_ecc_read_page;
1469 ecc->write_page = sunxi_nfc_hw_ecc_write_page;
1470 ecc->read_subpage = sunxi_nfc_hw_ecc_read_subpage;
1471 ecc->write_subpage = sunxi_nfc_hw_ecc_write_subpage;
1472 layout = ecc->layout;
1473 nsectors = mtd->writesize / ecc->size;
1475 for (i = 0; i < nsectors; i++) {
1477 layout->oobfree[i].offset =
1478 layout->oobfree[i - 1].offset +
1479 layout->oobfree[i - 1].length +
1481 layout->oobfree[i].length = 4;
1484 * The first 2 bytes are used for BB markers, hence we
1485 * only have 2 bytes available in the first user data
1488 layout->oobfree[i].length = 2;
1489 layout->oobfree[i].offset = 2;
1492 for (j = 0; j < ecc->bytes; j++)
1493 layout->eccpos[(ecc->bytes * i) + j] =
1494 layout->oobfree[i].offset +
1495 layout->oobfree[i].length + j;
1498 if (mtd->oobsize > (ecc->bytes + 4) * nsectors) {
1499 layout->oobfree[nsectors].offset =
1500 layout->oobfree[nsectors - 1].offset +
1501 layout->oobfree[nsectors - 1].length +
1503 layout->oobfree[nsectors].length = mtd->oobsize -
1504 ((ecc->bytes + 4) * nsectors);
1510 static int sunxi_nand_hw_syndrome_ecc_ctrl_init(struct mtd_info *mtd,
1511 struct nand_ecc_ctrl *ecc)
1513 struct nand_ecclayout *layout;
1518 ret = sunxi_nand_hw_common_ecc_ctrl_init(mtd, ecc);
1523 ecc->read_page = sunxi_nfc_hw_syndrome_ecc_read_page;
1524 ecc->write_page = sunxi_nfc_hw_syndrome_ecc_write_page;
1526 layout = ecc->layout;
1527 nsectors = mtd->writesize / ecc->size;
1529 for (i = 0; i < (ecc->bytes * nsectors); i++)
1530 layout->eccpos[i] = i;
1532 layout->oobfree[0].length = mtd->oobsize - i;
1533 layout->oobfree[0].offset = i;
1539 static void sunxi_nand_ecc_cleanup(struct nand_ecc_ctrl *ecc)
1541 switch (ecc->mode) {
1543 case NAND_ECC_HW_SYNDROME:
1544 sunxi_nand_hw_common_ecc_ctrl_cleanup(ecc);
1552 #endif /* __UBOOT__ */
1554 static int sunxi_nand_ecc_init(struct mtd_info *mtd, struct nand_ecc_ctrl *ecc)
1556 struct nand_chip *nand = mtd_to_nand(mtd);
1560 ecc->size = nand->ecc_step_ds;
1561 ecc->strength = nand->ecc_strength_ds;
1564 if (!ecc->size || !ecc->strength)
1567 switch (ecc->mode) {
1568 case NAND_ECC_SOFT_BCH:
1571 ret = sunxi_nand_hw_ecc_ctrl_init(mtd, ecc);
1575 case NAND_ECC_HW_SYNDROME:
1576 ret = sunxi_nand_hw_syndrome_ecc_ctrl_init(mtd, ecc);
1581 ecc->layout = kzalloc(sizeof(*ecc->layout), GFP_KERNEL);
1584 ecc->layout->oobfree[0].length = mtd->oobsize;
1594 static int sunxi_nand_chip_init(int node, struct sunxi_nfc *nfc, int devnum)
1596 const struct nand_sdr_timings *timings;
1597 const void *blob = gd->fdt_blob;
1598 struct sunxi_nand_chip *chip;
1599 struct mtd_info *mtd;
1600 struct nand_chip *nand;
1606 if (!fdt_getprop(blob, node, "reg", &nsels))
1609 nsels /= sizeof(u32);
1610 if (!nsels || nsels > 8) {
1611 dev_err(dev, "invalid reg property size\n");
1615 chip = kzalloc(sizeof(*chip) +
1616 (nsels * sizeof(struct sunxi_nand_chip_sel)),
1619 dev_err(dev, "could not allocate chip\n");
1623 chip->nsels = nsels;
1624 chip->selected = -1;
1626 for (i = 0; i < nsels; i++) {
1631 ret = fdtdec_get_int_array(gd->fdt_blob, node, "reg", cs, nsels);
1633 dev_err(dev, "could not retrieve reg property: %d\n", ret);
1637 ret = fdtdec_get_int_array(gd->fdt_blob, node, "allwinner,rb", rb,
1640 dev_err(dev, "could not retrieve reg property: %d\n", ret);
1644 for (i = 0; i < nsels; i++) {
1647 if (tmp > NFC_MAX_CS) {
1649 "invalid reg value: %u (max CS = 7)\n",
1654 if (test_and_set_bit(tmp, &nfc->assigned_cs)) {
1655 dev_err(dev, "CS %d already assigned\n", tmp);
1659 chip->sels[i].cs = tmp;
1662 if (tmp >= 0 && tmp < 2) {
1663 chip->sels[i].rb.type = RB_NATIVE;
1664 chip->sels[i].rb.info.nativeid = tmp;
1666 ret = gpio_request_by_name_nodev(offset_to_ofnode(node),
1668 &chip->sels[i].rb.info.gpio,
1671 chip->sels[i].rb.type = RB_GPIO;
1673 chip->sels[i].rb.type = RB_NONE;
1677 timings = onfi_async_timing_mode_to_sdr_timings(0);
1678 if (IS_ERR(timings)) {
1679 ret = PTR_ERR(timings);
1681 "could not retrieve timings for ONFI mode 0: %d\n",
1686 ret = sunxi_nand_chip_set_timings(chip, timings);
1688 dev_err(dev, "could not configure chip timings: %d\n", ret);
1693 /* Default tR value specified in the ONFI spec (chapter 4.15.1) */
1694 nand->chip_delay = 200;
1695 nand->controller = &nfc->controller;
1697 * Set the ECC mode to the default value in case nothing is specified
1700 nand->ecc.mode = NAND_ECC_HW;
1701 nand->flash_node = node;
1702 nand->select_chip = sunxi_nfc_select_chip;
1703 nand->cmd_ctrl = sunxi_nfc_cmd_ctrl;
1704 nand->read_buf = sunxi_nfc_read_buf;
1705 nand->write_buf = sunxi_nfc_write_buf;
1706 nand->read_byte = sunxi_nfc_read_byte;
1708 mtd = nand_to_mtd(nand);
1709 ret = nand_scan_ident(mtd, nsels, NULL);
1713 if (nand->bbt_options & NAND_BBT_USE_FLASH)
1714 nand->bbt_options |= NAND_BBT_NO_OOB;
1716 if (nand->options & NAND_NEED_SCRAMBLING)
1717 nand->options |= NAND_NO_SUBPAGE_WRITE;
1719 nand->options |= NAND_SUBPAGE_READ;
1721 ret = sunxi_nand_chip_init_timings(chip);
1723 dev_err(dev, "could not configure chip timings: %d\n", ret);
1727 ret = sunxi_nand_ecc_init(mtd, &nand->ecc);
1729 dev_err(dev, "ECC init failed: %d\n", ret);
1733 ret = nand_scan_tail(mtd);
1735 dev_err(dev, "nand_scan_tail failed: %d\n", ret);
1739 ret = nand_register(devnum, mtd);
1741 dev_err(dev, "failed to register mtd device: %d\n", ret);
1745 list_add_tail(&chip->node, &nfc->chips);
1750 static int sunxi_nand_chips_init(int node, struct sunxi_nfc *nfc)
1752 const void *blob = gd->fdt_blob;
1756 for (nand_node = fdt_first_subnode(blob, node); nand_node >= 0;
1757 nand_node = fdt_next_subnode(blob, nand_node))
1761 dev_err(dev, "too many NAND chips: %d (max = 8)\n", i);
1766 for (nand_node = fdt_first_subnode(blob, node); nand_node >= 0;
1767 nand_node = fdt_next_subnode(blob, nand_node)) {
1768 ret = sunxi_nand_chip_init(nand_node, nfc, i++);
1777 static void sunxi_nand_chips_cleanup(struct sunxi_nfc *nfc)
1779 struct sunxi_nand_chip *chip;
1781 while (!list_empty(&nfc->chips)) {
1782 chip = list_first_entry(&nfc->chips, struct sunxi_nand_chip,
1784 nand_release(&chip->mtd);
1785 sunxi_nand_ecc_cleanup(&chip->nand.ecc);
1786 list_del(&chip->node);
1790 #endif /* __UBOOT__ */
1792 void sunxi_nand_init(void)
1794 const void *blob = gd->fdt_blob;
1795 struct sunxi_nfc *nfc;
1800 nfc = kzalloc(sizeof(*nfc), GFP_KERNEL);
1804 spin_lock_init(&nfc->controller.lock);
1805 init_waitqueue_head(&nfc->controller.wq);
1806 INIT_LIST_HEAD(&nfc->chips);
1808 node = fdtdec_next_compatible(blob, 0, COMPAT_SUNXI_NAND);
1810 pr_err("unable to find nfc node in device tree\n");
1814 if (!fdtdec_get_is_enabled(blob, node)) {
1815 pr_err("nfc disabled in device tree\n");
1819 regs = fdtdec_get_addr(blob, node, "reg");
1820 if (regs == FDT_ADDR_T_NONE) {
1821 pr_err("unable to find nfc address in device tree\n");
1825 nfc->regs = (void *)regs;
1827 ret = sunxi_nfc_rst(nfc);
1831 ret = sunxi_nand_chips_init(node, nfc);
1833 dev_err(dev, "failed to init nand chips\n");
1843 MODULE_LICENSE("GPL v2");
1844 MODULE_AUTHOR("Boris BREZILLON");
1845 MODULE_DESCRIPTION("Allwinner NAND Flash Controller driver");