1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2018 Stefan Roese <sr@denx.de>
5 * Derived from drivers/mtd/nand/spi/micron.c
6 * Copyright (c) 2016-2017 Micron Technology, Inc.
11 #include <linux/device.h>
12 #include <linux/kernel.h>
14 #include <linux/mtd/spinand.h>
16 #define SPINAND_MFR_GIGADEVICE 0xC8
17 #define GD5FXGQ4XA_STATUS_ECC_1_7_BITFLIPS (1 << 4)
18 #define GD5FXGQ4XA_STATUS_ECC_8_BITFLIPS (3 << 4)
20 #define GD5FXGQ4XEXXG_REG_STATUS2 0xf0
22 static SPINAND_OP_VARIANTS(read_cache_variants,
23 SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
24 SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
25 SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
26 SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
27 SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
28 SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
30 static SPINAND_OP_VARIANTS(write_cache_variants,
31 SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
32 SPINAND_PROG_LOAD(true, 0, NULL, 0));
34 static SPINAND_OP_VARIANTS(update_cache_variants,
35 SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
36 SPINAND_PROG_LOAD(false, 0, NULL, 0));
38 static int gd5fxgq4xexxg_ooblayout_ecc(struct mtd_info *mtd, int section,
39 struct mtd_oob_region *region)
50 static int gd5fxgq4xexxg_ooblayout_free(struct mtd_info *mtd, int section,
51 struct mtd_oob_region *region)
56 /* Reserve 1 bytes for the BBM. */
63 static int gd5fxgq4xexxg_ecc_get_status(struct spinand_device *spinand,
67 struct spi_mem_op op = SPINAND_GET_FEATURE_OP(GD5FXGQ4XEXXG_REG_STATUS2,
71 switch (status & STATUS_ECC_MASK) {
72 case STATUS_ECC_NO_BITFLIPS:
75 case GD5FXGQ4XA_STATUS_ECC_1_7_BITFLIPS:
77 * Read status2 register to determine a more fine grained
80 ret = spi_mem_exec_op(spinand->slave, &op);
85 * 4 ... 7 bits are flipped (1..4 can't be detected, so
86 * report the maximum of 4 in this case
88 /* bits sorted this way (3...0): ECCS1,ECCS0,ECCSE1,ECCSE0 */
89 return ((status & STATUS_ECC_MASK) >> 2) |
90 ((status2 & STATUS_ECC_MASK) >> 4);
92 case GD5FXGQ4XA_STATUS_ECC_8_BITFLIPS:
95 case STATUS_ECC_UNCOR_ERROR:
105 static const struct mtd_ooblayout_ops gd5fxgq4xexxg_ooblayout = {
106 .ecc = gd5fxgq4xexxg_ooblayout_ecc,
107 .rfree = gd5fxgq4xexxg_ooblayout_free,
110 static const struct spinand_info gigadevice_spinand_table[] = {
111 SPINAND_INFO("GD5F1GQ4UExxG", 0xd1,
112 NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
114 SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
115 &write_cache_variants,
116 &update_cache_variants),
118 SPINAND_ECCINFO(&gd5fxgq4xexxg_ooblayout,
119 gd5fxgq4xexxg_ecc_get_status)),
122 static int gigadevice_spinand_detect(struct spinand_device *spinand)
124 u8 *id = spinand->id.data;
128 * For GD NANDs, There is an address byte needed to shift in before IDs
129 * are read out, so the first byte in raw_id is dummy.
131 if (id[1] != SPINAND_MFR_GIGADEVICE)
134 ret = spinand_match_and_init(spinand, gigadevice_spinand_table,
135 ARRAY_SIZE(gigadevice_spinand_table),
143 static const struct spinand_manufacturer_ops gigadevice_spinand_manuf_ops = {
144 .detect = gigadevice_spinand_detect,
147 const struct spinand_manufacturer gigadevice_spinand_manufacturer = {
148 .id = SPINAND_MFR_GIGADEVICE,
149 .name = "GigaDevice",
150 .ops = &gigadevice_spinand_manuf_ops,