drivers/mtd/nand/spi/gigadevice.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2018 Stefan Roese <sr@denx.de>
   4  *
   5  * Derived from drivers/mtd/nand/spi/micron.c
   6  *   Copyright (c) 2016-2017 Micron Technology, Inc.
   7  */
   8
   9 #ifndef __UBOOT__
  10 #include <linux/device.h>
  11 #include <linux/kernel.h>
  12 #endif
  13 #include <linux/mtd/spinand.h>
  14
  15 #define SPINAND_MFR_GIGADEVICE                  0xC8
  16 #define GD5FXGQ4XA_STATUS_ECC_1_7_BITFLIPS      (1 << 4)
  17 #define GD5FXGQ4XA_STATUS_ECC_8_BITFLIPS        (3 << 4)
  18
  19 #define GD5FXGQ4XEXXG_REG_STATUS2               0xf0
  20
  21 static SPINAND_OP_VARIANTS(read_cache_variants,
  22                 SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
  23                 SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
  24                 SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
  25                 SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
  26                 SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
  27                 SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
  28
  29 static SPINAND_OP_VARIANTS(write_cache_variants,
  30                 SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
  31                 SPINAND_PROG_LOAD(true, 0, NULL, 0));
  32
  33 static SPINAND_OP_VARIANTS(update_cache_variants,
  34                 SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
  35                 SPINAND_PROG_LOAD(false, 0, NULL, 0));
  36
  37 static int gd5fxgq4xexxg_ooblayout_ecc(struct mtd_info *mtd, int section,
  38                                        struct mtd_oob_region *region)
  39 {
  40         if (section)
  41                 return -ERANGE;
  42
  43         region->offset = 64;
  44         region->length = 64;
  45
  46         return 0;
  47 }
  48
  49 static int gd5fxgq4xexxg_ooblayout_free(struct mtd_info *mtd, int section,
  50                                         struct mtd_oob_region *region)
  51 {
  52         if (section)
  53                 return -ERANGE;
  54
  55         /* Reserve 1 bytes for the BBM. */
  56         region->offset = 1;
  57         region->length = 63;
  58
  59         return 0;
  60 }
  61
  62 static int gd5fxgq4xexxg_ecc_get_status(struct spinand_device *spinand,
  63                                         u8 status)
  64 {
  65         u8 status2;
  66         struct spi_mem_op op = SPINAND_GET_FEATURE_OP(GD5FXGQ4XEXXG_REG_STATUS2,
  67                                                       &status2);
  68         int ret;
  69
  70         switch (status & STATUS_ECC_MASK) {
  71         case STATUS_ECC_NO_BITFLIPS:
  72                 return 0;
  73
  74         case GD5FXGQ4XA_STATUS_ECC_1_7_BITFLIPS:
  75                 /*
  76                  * Read status2 register to determine a more fine grained
  77                  * bit error status
  78                  */
  79                 ret = spi_mem_exec_op(spinand->slave, &op);
  80                 if (ret)
  81                         return ret;
  82
  83                 /*
  84                  * 4 ... 7 bits are flipped (1..4 can't be detected, so
  85                  * report the maximum of 4 in this case
  86                  */
  87                 /* bits sorted this way (3...0): ECCS1,ECCS0,ECCSE1,ECCSE0 */
  88                 return ((status & STATUS_ECC_MASK) >> 2) |
  89                         ((status2 & STATUS_ECC_MASK) >> 4);
  90
  91         case GD5FXGQ4XA_STATUS_ECC_8_BITFLIPS:
  92                 return 8;
  93
  94         case STATUS_ECC_UNCOR_ERROR:
  95                 return -EBADMSG;
  96
  97         default:
  98                 break;
  99         }
 100
 101         return -EINVAL;
 102 }
 103
 104 static const struct mtd_ooblayout_ops gd5fxgq4xexxg_ooblayout = {
 105         .ecc = gd5fxgq4xexxg_ooblayout_ecc,
 106         .free = gd5fxgq4xexxg_ooblayout_free,
 107 };
 108
 109 static const struct spinand_info gigadevice_spinand_table[] = {
 110         SPINAND_INFO("GD5F1GQ4UExxG", 0xd1,
 111                      NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
 112                      NAND_ECCREQ(8, 512),
 113                      SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
 114                                               &write_cache_variants,
 115                                               &update_cache_variants),
 116                      0,
 117                      SPINAND_ECCINFO(&gd5fxgq4xexxg_ooblayout,
 118                                      gd5fxgq4xexxg_ecc_get_status)),
 119 };
 120
 121 static int gigadevice_spinand_detect(struct spinand_device *spinand)
 122 {
 123         u8 *id = spinand->id.data;
 124         int ret;
 125
 126         /*
 127          * For GD NANDs, There is an address byte needed to shift in before IDs
 128          * are read out, so the first byte in raw_id is dummy.
 129          */
 130         if (id[1] != SPINAND_MFR_GIGADEVICE)
 131                 return 0;
 132
 133         ret = spinand_match_and_init(spinand, gigadevice_spinand_table,
 134                                      ARRAY_SIZE(gigadevice_spinand_table),
 135                                      id[2]);
 136         if (ret)
 137                 return ret;
 138
 139         return 1;
 140 }
 141
 142 static const struct spinand_manufacturer_ops gigadevice_spinand_manuf_ops = {
 143         .detect = gigadevice_spinand_detect,
 144 };
 145
 146 const struct spinand_manufacturer gigadevice_spinand_manufacturer = {
 147         .id = SPINAND_MFR_GIGADEVICE,
 148         .name = "GigaDevice",
 149         .ops = &gigadevice_spinand_manuf_ops,
 150 };