1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2014-2015, Antmicro Ltd <www.antmicro.com>
4 * Copyright (c) 2015, AW-SOM Technologies <www.aw-som.com>
7 #include <asm/arch/clock.h>
12 #include <linux/bitops.h>
13 #include <linux/ctype.h>
14 #include <linux/delay.h>
17 #define NFC_CTL 0x00000000
18 #define NFC_ST 0x00000004
19 #define NFC_INT 0x00000008
20 #define NFC_TIMING_CTL 0x0000000C
21 #define NFC_TIMING_CFG 0x00000010
22 #define NFC_ADDR_LOW 0x00000014
23 #define NFC_ADDR_HIGH 0x00000018
24 #define NFC_SECTOR_NUM 0x0000001C
25 #define NFC_CNT 0x00000020
26 #define NFC_CMD 0x00000024
27 #define NFC_RCMD_SET 0x00000028
28 #define NFC_WCMD_SET 0x0000002C
29 #define NFC_IO_DATA 0x00000030
30 #define NFC_ECC_CTL 0x00000034
31 #define NFC_ECC_ST 0x00000038
32 #define NFC_DEBUG 0x0000003C
33 #define NFC_ECC_CNT0 0x00000040
34 #define NFC_ECC_CNT1 0x00000044
35 #define NFC_ECC_CNT2 0x00000048
36 #define NFC_ECC_CNT3 0x0000004C
37 #define NFC_USER_DATA_BASE 0x00000050
38 #define NFC_EFNAND_STATUS 0x00000090
39 #define NFC_SPARE_AREA 0x000000A0
40 #define NFC_PATTERN_ID 0x000000A4
41 #define NFC_RAM0_BASE 0x00000400
42 #define NFC_RAM1_BASE 0x00000800
44 #define NFC_CTL_EN (1 << 0)
45 #define NFC_CTL_RESET (1 << 1)
46 #define NFC_CTL_RAM_METHOD (1 << 14)
47 #define NFC_CTL_PAGE_SIZE_MASK (0xf << 8)
48 #define NFC_CTL_PAGE_SIZE(a) ((fls(a) - 11) << 8)
51 #define NFC_ECC_EN (1 << 0)
52 #define NFC_ECC_PIPELINE (1 << 3)
53 #define NFC_ECC_EXCEPTION (1 << 4)
54 #define NFC_ECC_BLOCK_SIZE (1 << 5)
55 #define NFC_ECC_RANDOM_EN (1 << 9)
56 #define NFC_ECC_RANDOM_DIRECTION (1 << 10)
59 #define NFC_ADDR_NUM_OFFSET 16
60 #define NFC_SEND_ADDR (1 << 19)
61 #define NFC_ACCESS_DIR (1 << 20)
62 #define NFC_DATA_TRANS (1 << 21)
63 #define NFC_SEND_CMD1 (1 << 22)
64 #define NFC_WAIT_FLAG (1 << 23)
65 #define NFC_SEND_CMD2 (1 << 24)
66 #define NFC_SEQ (1 << 25)
67 #define NFC_DATA_SWAP_METHOD (1 << 26)
68 #define NFC_ROW_AUTO_INC (1 << 27)
69 #define NFC_SEND_CMD3 (1 << 28)
70 #define NFC_SEND_CMD4 (1 << 29)
71 #define NFC_RAW_CMD (0 << 30)
72 #define NFC_ECC_CMD (1 << 30)
73 #define NFC_PAGE_CMD (2 << 30)
75 #define NFC_ST_CMD_INT_FLAG (1 << 1)
76 #define NFC_ST_DMA_INT_FLAG (1 << 2)
77 #define NFC_ST_CMD_FIFO_STAT (1 << 3)
79 #define NFC_READ_CMD_OFFSET 0
80 #define NFC_RANDOM_READ_CMD0_OFFSET 8
81 #define NFC_RANDOM_READ_CMD1_OFFSET 16
83 #define NFC_CMD_RNDOUTSTART 0xE0
84 #define NFC_CMD_RNDOUT 0x05
85 #define NFC_CMD_READSTART 0x30
97 /* minimal "boot0" style NAND support for Allwinner A20 */
99 /* random seed used by linux */
100 const uint16_t random_seed[128] = {
101 0x2b75, 0x0bd0, 0x5ca3, 0x62d1, 0x1c93, 0x07e9, 0x2162, 0x3a72,
102 0x0d67, 0x67f9, 0x1be7, 0x077d, 0x032f, 0x0dac, 0x2716, 0x2436,
103 0x7922, 0x1510, 0x3860, 0x5287, 0x480f, 0x4252, 0x1789, 0x5a2d,
104 0x2a49, 0x5e10, 0x437f, 0x4b4e, 0x2f45, 0x216e, 0x5cb7, 0x7130,
105 0x2a3f, 0x60e4, 0x4dc9, 0x0ef0, 0x0f52, 0x1bb9, 0x6211, 0x7a56,
106 0x226d, 0x4ea7, 0x6f36, 0x3692, 0x38bf, 0x0c62, 0x05eb, 0x4c55,
107 0x60f4, 0x728c, 0x3b6f, 0x2037, 0x7f69, 0x0936, 0x651a, 0x4ceb,
108 0x6218, 0x79f3, 0x383f, 0x18d9, 0x4f05, 0x5c82, 0x2912, 0x6f17,
109 0x6856, 0x5938, 0x1007, 0x61ab, 0x3e7f, 0x57c2, 0x542f, 0x4f62,
110 0x7454, 0x2eac, 0x7739, 0x42d4, 0x2f90, 0x435a, 0x2e52, 0x2064,
111 0x637c, 0x66ad, 0x2c90, 0x0bad, 0x759c, 0x0029, 0x0986, 0x7126,
112 0x1ca7, 0x1605, 0x386a, 0x27f5, 0x1380, 0x6d75, 0x24c3, 0x0f8e,
113 0x2b7a, 0x1418, 0x1fd1, 0x7dc1, 0x2d8e, 0x43af, 0x2267, 0x7da3,
114 0x4e3d, 0x1338, 0x50db, 0x454d, 0x764d, 0x40a3, 0x42e6, 0x262b,
115 0x2d2e, 0x1aea, 0x2e17, 0x173d, 0x3a6e, 0x71bf, 0x25f9, 0x0a5d,
116 0x7c57, 0x0fbe, 0x46ce, 0x4939, 0x6b17, 0x37bb, 0x3e91, 0x76db,
119 #define DEFAULT_TIMEOUT_US 100000
121 static int check_value_inner(int offset, int expected_bits,
122 int timeout_us, int negation)
125 int val = readl(offset) & expected_bits;
126 if (negation ? !val : val)
129 } while (--timeout_us);
134 static inline int check_value(int offset, int expected_bits,
137 return check_value_inner(offset, expected_bits, timeout_us, 0);
140 static inline int check_value_negated(int offset, int unexpected_bits,
143 return check_value_inner(offset, unexpected_bits, timeout_us, 1);
146 static int nand_wait_cmd_fifo_empty(void)
148 if (!check_value_negated(SUNXI_NFC_BASE + NFC_ST, NFC_ST_CMD_FIFO_STAT,
149 DEFAULT_TIMEOUT_US)) {
150 printf("nand: timeout waiting for empty cmd FIFO\n");
157 static int nand_wait_int(void)
159 if (!check_value(SUNXI_NFC_BASE + NFC_ST, NFC_ST_CMD_INT_FLAG,
160 DEFAULT_TIMEOUT_US)) {
161 printf("nand: timeout waiting for interruption\n");
168 static int nand_exec_cmd(u32 cmd)
172 ret = nand_wait_cmd_fifo_empty();
176 writel(NFC_ST_CMD_INT_FLAG, SUNXI_NFC_BASE + NFC_ST);
177 writel(cmd, SUNXI_NFC_BASE + NFC_CMD);
179 return nand_wait_int();
188 val = readl(SUNXI_NFC_BASE + NFC_CTL);
189 /* enable and reset CTL */
190 writel(val | NFC_CTL_EN | NFC_CTL_RESET,
191 SUNXI_NFC_BASE + NFC_CTL);
193 if (!check_value_negated(SUNXI_NFC_BASE + NFC_CTL,
194 NFC_CTL_RESET, DEFAULT_TIMEOUT_US)) {
195 printf("Couldn't initialize nand\n");
199 nand_exec_cmd(NFC_SEND_CMD1 | NFC_WAIT_FLAG | NAND_CMD_RESET);
202 static void nand_apply_config(const struct nfc_config *conf)
206 nand_wait_cmd_fifo_empty();
208 val = readl(SUNXI_NFC_BASE + NFC_CTL);
209 val &= ~NFC_CTL_PAGE_SIZE_MASK;
210 writel(val | NFC_CTL_RAM_METHOD | NFC_CTL_PAGE_SIZE(conf->page_size),
211 SUNXI_NFC_BASE + NFC_CTL);
212 writel(conf->ecc_size, SUNXI_NFC_BASE + NFC_CNT);
213 writel(conf->page_size, SUNXI_NFC_BASE + NFC_SPARE_AREA);
216 static int nand_load_page(const struct nfc_config *conf, u32 offs)
218 int page = offs / conf->page_size;
220 writel((NFC_CMD_RNDOUTSTART << NFC_RANDOM_READ_CMD1_OFFSET) |
221 (NFC_CMD_RNDOUT << NFC_RANDOM_READ_CMD0_OFFSET) |
222 (NFC_CMD_READSTART << NFC_READ_CMD_OFFSET),
223 SUNXI_NFC_BASE + NFC_RCMD_SET);
224 writel(((page & 0xFFFF) << 16), SUNXI_NFC_BASE + NFC_ADDR_LOW);
225 writel((page >> 16) & 0xFF, SUNXI_NFC_BASE + NFC_ADDR_HIGH);
227 return nand_exec_cmd(NFC_SEND_CMD1 | NFC_SEND_CMD2 | NFC_RAW_CMD |
228 NFC_SEND_ADDR | NFC_WAIT_FLAG |
229 ((conf->addr_cycles - 1) << NFC_ADDR_NUM_OFFSET));
232 static int nand_change_column(u16 column)
236 writel((NFC_CMD_RNDOUTSTART << NFC_RANDOM_READ_CMD1_OFFSET) |
237 (NFC_CMD_RNDOUT << NFC_RANDOM_READ_CMD0_OFFSET) |
238 (NFC_CMD_RNDOUTSTART << NFC_READ_CMD_OFFSET),
239 SUNXI_NFC_BASE + NFC_RCMD_SET);
240 writel(column, SUNXI_NFC_BASE + NFC_ADDR_LOW);
242 ret = nand_exec_cmd(NFC_SEND_CMD1 | NFC_SEND_CMD2 | NFC_RAW_CMD |
243 (1 << NFC_ADDR_NUM_OFFSET) | NFC_SEND_ADDR |
248 /* Ensure tCCS has passed before reading data */
254 static const int ecc_bytes[] = {32, 46, 54, 60, 74, 88, 102, 110, 116};
256 static int nand_read_page(const struct nfc_config *conf, u32 offs,
259 int nsectors = len / conf->ecc_size;
261 int oob_chunk_sz = ecc_bytes[conf->ecc_strength];
262 int page = offs / conf->page_size;
266 if (offs % conf->page_size || len % conf->ecc_size ||
267 len > conf->page_size || len < 0)
270 /* Choose correct seed if randomized */
272 rand_seed = random_seed[page % conf->nseeds];
274 /* Retrieve data from SRAM (PIO) */
275 for (i = 0; i < nsectors; i++) {
276 int data_off = i * conf->ecc_size;
277 int oob_off = conf->page_size + (i * oob_chunk_sz);
278 u8 *data = dest + data_off;
280 /* Clear ECC status and restart ECC engine */
281 writel(0, SUNXI_NFC_BASE + NFC_ECC_ST);
282 writel((rand_seed << 16) | (conf->ecc_strength << 12) |
283 (conf->randomize ? NFC_ECC_RANDOM_EN : 0) |
284 (conf->ecc_size == 512 ? NFC_ECC_BLOCK_SIZE : 0) |
285 NFC_ECC_EN | NFC_ECC_EXCEPTION,
286 SUNXI_NFC_BASE + NFC_ECC_CTL);
288 /* Move the data in SRAM */
289 nand_change_column(data_off);
290 writel(conf->ecc_size, SUNXI_NFC_BASE + NFC_CNT);
291 nand_exec_cmd(NFC_DATA_TRANS);
294 * Let the ECC engine consume the ECC bytes and possibly correct
297 nand_change_column(oob_off);
298 nand_exec_cmd(NFC_DATA_TRANS | NFC_ECC_CMD);
300 /* Get the ECC status */
301 ecc_st = readl(SUNXI_NFC_BASE + NFC_ECC_ST);
303 /* ECC error detected. */
308 * Return 1 if the first chunk is empty (needed for
309 * configuration detection).
311 if (!i && (ecc_st & 0x10000))
314 /* Retrieve the data from SRAM */
315 memcpy_fromio(data, SUNXI_NFC_BASE + NFC_RAM0_BASE,
318 /* Stop the ECC engine */
319 writel(readl(SUNXI_NFC_BASE + NFC_ECC_CTL) & ~NFC_ECC_EN,
320 SUNXI_NFC_BASE + NFC_ECC_CTL);
322 if (data_off + conf->ecc_size >= len)
329 static int nand_max_ecc_strength(struct nfc_config *conf)
331 int max_oobsize, max_ecc_bytes;
332 int nsectors = conf->page_size / conf->ecc_size;
336 * ECC strength is limited by the size of the OOB area which is
337 * correlated with the page size.
339 switch (conf->page_size) {
356 max_ecc_bytes = max_oobsize / nsectors;
358 for (i = 0; i < ARRAY_SIZE(ecc_bytes); i++) {
359 if (ecc_bytes[i] > max_ecc_bytes)
369 static int nand_detect_ecc_config(struct nfc_config *conf, u32 offs,
372 /* NAND with pages > 4k will likely require 1k sector size. */
373 int min_ecc_size = conf->page_size > 4096 ? 1024 : 512;
374 int page = offs / conf->page_size;
378 * In most cases, 1k sectors are preferred over 512b ones, start
379 * testing this config first.
381 for (conf->ecc_size = 1024; conf->ecc_size >= min_ecc_size;
382 conf->ecc_size >>= 1) {
383 int max_ecc_strength = nand_max_ecc_strength(conf);
385 nand_apply_config(conf);
388 * We are starting from the maximum ECC strength because
389 * most of the time NAND vendors provide an OOB area that
390 * barely meets the ECC requirements.
392 for (conf->ecc_strength = max_ecc_strength;
393 conf->ecc_strength >= 0;
394 conf->ecc_strength--) {
395 conf->randomize = false;
396 if (nand_change_column(0))
400 * Only read the first sector to speedup detection.
402 ret = nand_read_page(conf, offs, dest, conf->ecc_size);
405 } else if (ret > 0) {
407 * If page is empty we can't deduce anything
408 * about the ECC config => stop the detection.
413 conf->randomize = true;
414 conf->nseeds = ARRAY_SIZE(random_seed);
416 if (nand_change_column(0))
419 if (!nand_read_page(conf, offs, dest,
424 * Find the next ->nseeds value that would
425 * change the randomizer seed for the page
426 * we're trying to read.
428 while (conf->nseeds >= 16) {
429 int seed = page % conf->nseeds;
432 if (seed != page % conf->nseeds)
435 } while (conf->nseeds >= 16);
442 static int nand_detect_config(struct nfc_config *conf, u32 offs, void *dest)
448 * Modern NANDs are more likely than legacy ones, so we start testing
449 * with 5 address cycles.
451 for (conf->addr_cycles = 5;
452 conf->addr_cycles >= 4;
453 conf->addr_cycles--) {
454 int max_page_size = conf->addr_cycles == 4 ? 2048 : 16384;
457 * Ignoring 1k pages cause I'm not even sure this case exist
460 for (conf->page_size = 2048; conf->page_size <= max_page_size;
461 conf->page_size <<= 1) {
462 if (nand_load_page(conf, offs))
465 if (!nand_detect_ecc_config(conf, offs, dest)) {
475 static int nand_read_buffer(struct nfc_config *conf, uint32_t offs,
476 unsigned int size, void *dest)
478 int first_seed = 0, page, ret;
480 size = ALIGN(size, conf->page_size);
481 page = offs / conf->page_size;
483 first_seed = page % conf->nseeds;
485 for (; size; size -= conf->page_size) {
486 if (nand_load_page(conf, offs))
489 ret = nand_read_page(conf, offs, dest, conf->page_size);
491 * The ->nseeds value should be equal to the number of pages
492 * in an eraseblock. Since we don't know this information in
493 * advance we might have picked a wrong value.
495 if (ret < 0 && conf->randomize) {
496 int cur_seed = page % conf->nseeds;
499 * We already tried all the seed values => we are
500 * facing a real corruption.
502 if (cur_seed < first_seed)
505 /* Try to adjust ->nseeds and read the page again... */
506 conf->nseeds = cur_seed;
508 if (nand_change_column(0))
511 /* ... it still fails => it's a real corruption. */
512 if (nand_read_page(conf, offs, dest, conf->page_size))
514 } else if (ret && conf->randomize) {
515 memset(dest, 0xff, conf->page_size);
519 offs += conf->page_size;
520 dest += conf->page_size;
526 int nand_spl_load_image(uint32_t offs, unsigned int size, void *dest)
528 static struct nfc_config conf = { };
531 ret = nand_detect_config(&conf, offs, dest);
535 return nand_read_buffer(&conf, offs, size, dest);
538 void nand_deselect(void)
540 struct sunxi_ccm_reg *const ccm =
541 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
543 clrbits_le32(&ccm->ahb_gate0, (CLK_GATE_OPEN << AHB_GATE_OFFSET_NAND0));
544 #ifdef CONFIG_MACH_SUN9I
545 clrbits_le32(&ccm->ahb_gate1, (1 << AHB_GATE_OFFSET_DMA));
547 clrbits_le32(&ccm->ahb_gate0, (1 << AHB_GATE_OFFSET_DMA));
549 clrbits_le32(&ccm->nand0_clk_cfg, CCM_NAND_CTRL_ENABLE | AHB_DIV_1);