1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2013 Boris BREZILLON <b.brezillon.dev@gmail.com>
4 * Copyright (C) 2015 Roy Spliet <r.spliet@ultimaker.com>
7 * https://github.com/yuq/sunxi-nfc-mtd
8 * Copyright (C) 2013 Qiang Yu <yuq825@gmail.com>
10 * https://github.com/hno/Allwinner-Info
11 * Copyright (C) 2013 Henrik Nordström <Henrik Nordström>
13 * Copyright (C) 2013 Dmitriy B. <rzk333@gmail.com>
14 * Copyright (C) 2013 Sergey Lapin <slapin@ossfans.org>
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2 of the License, or
19 * (at your option) any later version.
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
32 #include <linux/kernel.h>
33 #include <linux/mtd/mtd.h>
34 #include <linux/mtd/rawnand.h>
35 #include <linux/mtd/partitions.h>
39 #include <asm/arch/clock.h>
41 DECLARE_GLOBAL_DATA_PTR;
43 #define NFC_REG_CTL 0x0000
44 #define NFC_REG_ST 0x0004
45 #define NFC_REG_INT 0x0008
46 #define NFC_REG_TIMING_CTL 0x000C
47 #define NFC_REG_TIMING_CFG 0x0010
48 #define NFC_REG_ADDR_LOW 0x0014
49 #define NFC_REG_ADDR_HIGH 0x0018
50 #define NFC_REG_SECTOR_NUM 0x001C
51 #define NFC_REG_CNT 0x0020
52 #define NFC_REG_CMD 0x0024
53 #define NFC_REG_RCMD_SET 0x0028
54 #define NFC_REG_WCMD_SET 0x002C
55 #define NFC_REG_IO_DATA 0x0030
56 #define NFC_REG_ECC_CTL 0x0034
57 #define NFC_REG_ECC_ST 0x0038
58 #define NFC_REG_DEBUG 0x003C
59 #define NFC_REG_ECC_ERR_CNT(x) ((0x0040 + (x)) & ~0x3)
60 #define NFC_REG_USER_DATA(x) (0x0050 + ((x) * 4))
61 #define NFC_REG_SPARE_AREA 0x00A0
62 #define NFC_REG_PAT_ID 0x00A4
63 #define NFC_RAM0_BASE 0x0400
64 #define NFC_RAM1_BASE 0x0800
66 /* define bit use in NFC_CTL */
68 #define NFC_RESET BIT(1)
69 #define NFC_BUS_WIDTH_MSK BIT(2)
70 #define NFC_BUS_WIDTH_8 (0 << 2)
71 #define NFC_BUS_WIDTH_16 (1 << 2)
72 #define NFC_RB_SEL_MSK BIT(3)
73 #define NFC_RB_SEL(x) ((x) << 3)
74 #define NFC_CE_SEL_MSK (0x7 << 24)
75 #define NFC_CE_SEL(x) ((x) << 24)
76 #define NFC_CE_CTL BIT(6)
77 #define NFC_PAGE_SHIFT_MSK (0xf << 8)
78 #define NFC_PAGE_SHIFT(x) (((x) < 10 ? 0 : (x) - 10) << 8)
79 #define NFC_SAM BIT(12)
80 #define NFC_RAM_METHOD BIT(14)
81 #define NFC_DEBUG_CTL BIT(31)
83 /* define bit use in NFC_ST */
84 #define NFC_RB_B2R BIT(0)
85 #define NFC_CMD_INT_FLAG BIT(1)
86 #define NFC_DMA_INT_FLAG BIT(2)
87 #define NFC_CMD_FIFO_STATUS BIT(3)
88 #define NFC_STA BIT(4)
89 #define NFC_NATCH_INT_FLAG BIT(5)
90 #define NFC_RB_STATE(x) BIT(x + 8)
92 /* define bit use in NFC_INT */
93 #define NFC_B2R_INT_ENABLE BIT(0)
94 #define NFC_CMD_INT_ENABLE BIT(1)
95 #define NFC_DMA_INT_ENABLE BIT(2)
96 #define NFC_INT_MASK (NFC_B2R_INT_ENABLE | \
97 NFC_CMD_INT_ENABLE | \
100 /* define bit use in NFC_TIMING_CTL */
101 #define NFC_TIMING_CTL_EDO BIT(8)
103 /* define NFC_TIMING_CFG register layout */
104 #define NFC_TIMING_CFG(tWB, tADL, tWHR, tRHW, tCAD) \
105 (((tWB) & 0x3) | (((tADL) & 0x3) << 2) | \
106 (((tWHR) & 0x3) << 4) | (((tRHW) & 0x3) << 6) | \
107 (((tCAD) & 0x7) << 8))
109 /* define bit use in NFC_CMD */
110 #define NFC_CMD_LOW_BYTE_MSK 0xff
111 #define NFC_CMD_HIGH_BYTE_MSK (0xff << 8)
112 #define NFC_CMD(x) (x)
113 #define NFC_ADR_NUM_MSK (0x7 << 16)
114 #define NFC_ADR_NUM(x) (((x) - 1) << 16)
115 #define NFC_SEND_ADR BIT(19)
116 #define NFC_ACCESS_DIR BIT(20)
117 #define NFC_DATA_TRANS BIT(21)
118 #define NFC_SEND_CMD1 BIT(22)
119 #define NFC_WAIT_FLAG BIT(23)
120 #define NFC_SEND_CMD2 BIT(24)
121 #define NFC_SEQ BIT(25)
122 #define NFC_DATA_SWAP_METHOD BIT(26)
123 #define NFC_ROW_AUTO_INC BIT(27)
124 #define NFC_SEND_CMD3 BIT(28)
125 #define NFC_SEND_CMD4 BIT(29)
126 #define NFC_CMD_TYPE_MSK (0x3 << 30)
127 #define NFC_NORMAL_OP (0 << 30)
128 #define NFC_ECC_OP (1 << 30)
129 #define NFC_PAGE_OP (2 << 30)
131 /* define bit use in NFC_RCMD_SET */
132 #define NFC_READ_CMD_MSK 0xff
133 #define NFC_RND_READ_CMD0_MSK (0xff << 8)
134 #define NFC_RND_READ_CMD1_MSK (0xff << 16)
136 /* define bit use in NFC_WCMD_SET */
137 #define NFC_PROGRAM_CMD_MSK 0xff
138 #define NFC_RND_WRITE_CMD_MSK (0xff << 8)
139 #define NFC_READ_CMD0_MSK (0xff << 16)
140 #define NFC_READ_CMD1_MSK (0xff << 24)
142 /* define bit use in NFC_ECC_CTL */
143 #define NFC_ECC_EN BIT(0)
144 #define NFC_ECC_PIPELINE BIT(3)
145 #define NFC_ECC_EXCEPTION BIT(4)
146 #define NFC_ECC_BLOCK_SIZE_MSK BIT(5)
147 #define NFC_ECC_BLOCK_512 (1 << 5)
148 #define NFC_RANDOM_EN BIT(9)
149 #define NFC_RANDOM_DIRECTION BIT(10)
150 #define NFC_ECC_MODE_MSK (0xf << 12)
151 #define NFC_ECC_MODE(x) ((x) << 12)
152 #define NFC_RANDOM_SEED_MSK (0x7fff << 16)
153 #define NFC_RANDOM_SEED(x) ((x) << 16)
155 /* define bit use in NFC_ECC_ST */
156 #define NFC_ECC_ERR(x) BIT(x)
157 #define NFC_ECC_PAT_FOUND(x) BIT(x + 16)
158 #define NFC_ECC_ERR_CNT(b, x) (((x) >> ((b) * 8)) & 0xff)
160 #define NFC_DEFAULT_TIMEOUT_MS 1000
162 #define NFC_SRAM_SIZE 1024
167 * Ready/Busy detection type: describes the Ready/Busy detection modes
169 * @RB_NONE: no external detection available, rely on STATUS command
170 * and software timeouts
171 * @RB_NATIVE: use sunxi NAND controller Ready/Busy support. The Ready/Busy
172 * pin of the NAND flash chip must be connected to one of the
173 * native NAND R/B pins (those which can be muxed to the NAND
175 * @RB_GPIO: use a simple GPIO to handle Ready/Busy status. The Ready/Busy
176 * pin of the NAND flash chip must be connected to a GPIO capable
179 enum sunxi_nand_rb_type {
186 * Ready/Busy structure: stores information related to Ready/Busy detection
188 * @type: the Ready/Busy detection mode
189 * @info: information related to the R/B detection mode. Either a gpio
190 * id or a native R/B id (those supported by the NAND controller).
192 struct sunxi_nand_rb {
193 enum sunxi_nand_rb_type type;
195 struct gpio_desc gpio;
201 * Chip Select structure: stores information related to NAND Chip Select
203 * @cs: the NAND CS id used to communicate with a NAND Chip
204 * @rb: the Ready/Busy description
206 struct sunxi_nand_chip_sel {
208 struct sunxi_nand_rb rb;
212 * sunxi HW ECC infos: stores information related to HW ECC support
214 * @mode: the sunxi ECC mode field deduced from ECC requirements
215 * @layout: the OOB layout depending on the ECC requirements and the
218 struct sunxi_nand_hw_ecc {
220 struct nand_ecclayout layout;
224 * NAND chip structure: stores NAND chip device related information
226 * @node: used to store NAND chips into a list
227 * @nand: base NAND chip structure
228 * @mtd: base MTD structure
229 * @clk_rate: clk_rate required for this NAND chip
230 * @timing_cfg TIMING_CFG register value for this NAND chip
231 * @selected: current active CS
232 * @nsels: number of CS lines required by the NAND chip
233 * @sels: array of CS lines descriptions
235 struct sunxi_nand_chip {
236 struct list_head node;
237 struct nand_chip nand;
238 unsigned long clk_rate;
247 struct sunxi_nand_chip_sel sels[0];
250 static inline struct sunxi_nand_chip *to_sunxi_nand(struct nand_chip *nand)
252 return container_of(nand, struct sunxi_nand_chip, nand);
256 * NAND Controller structure: stores sunxi NAND controller information
258 * @controller: base controller structure
259 * @dev: parent device (used to print error messages)
260 * @regs: NAND controller registers
261 * @ahb_clk: NAND Controller AHB clock
262 * @mod_clk: NAND Controller mod clock
263 * @assigned_cs: bitmask describing already assigned CS lines
264 * @clk_rate: NAND controller current clock rate
265 * @chips: a list containing all the NAND chips attached to
266 * this NAND controller
267 * @complete: a completion object used to wait for NAND
271 struct nand_hw_control controller;
276 unsigned long assigned_cs;
277 unsigned long clk_rate;
278 struct list_head chips;
281 static inline struct sunxi_nfc *to_sunxi_nfc(struct nand_hw_control *ctrl)
283 return container_of(ctrl, struct sunxi_nfc, controller);
286 static void sunxi_nfc_set_clk_rate(unsigned long hz)
288 struct sunxi_ccm_reg *const ccm =
289 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
292 div_m = (clock_get_pll6() + hz - 1) / hz;
293 for (div_n = 0; div_n < 3 && div_m > 16; div_n++) {
301 /* config mod clock */
302 writel(CCM_NAND_CTRL_ENABLE | CCM_NAND_CTRL_PLL6 |
303 CCM_NAND_CTRL_N(div_n) | CCM_NAND_CTRL_M(div_m),
304 &ccm->nand0_clk_cfg);
306 /* gate on nand clock */
307 setbits_le32(&ccm->ahb_gate0, (1 << AHB_GATE_OFFSET_NAND0));
308 #ifdef CONFIG_MACH_SUN9I
309 setbits_le32(&ccm->ahb_gate1, (1 << AHB_GATE_OFFSET_DMA));
311 setbits_le32(&ccm->ahb_gate0, (1 << AHB_GATE_OFFSET_DMA));
315 static int sunxi_nfc_wait_int(struct sunxi_nfc *nfc, u32 flags,
316 unsigned int timeout_ms)
318 unsigned int timeout_ticks;
319 u32 time_start, status;
320 int ret = -ETIMEDOUT;
323 timeout_ms = NFC_DEFAULT_TIMEOUT_MS;
325 timeout_ticks = (timeout_ms * CONFIG_SYS_HZ) / 1000;
327 time_start = get_timer(0);
330 status = readl(nfc->regs + NFC_REG_ST);
331 if ((status & flags) == flags) {
337 } while (get_timer(time_start) < timeout_ticks);
339 writel(status & flags, nfc->regs + NFC_REG_ST);
344 static int sunxi_nfc_wait_cmd_fifo_empty(struct sunxi_nfc *nfc)
346 unsigned long timeout = (CONFIG_SYS_HZ *
347 NFC_DEFAULT_TIMEOUT_MS) / 1000;
350 time_start = get_timer(0);
352 if (!(readl(nfc->regs + NFC_REG_ST) & NFC_CMD_FIFO_STATUS))
354 } while (get_timer(time_start) < timeout);
356 dev_err(nfc->dev, "wait for empty cmd FIFO timedout\n");
360 static int sunxi_nfc_rst(struct sunxi_nfc *nfc)
362 unsigned long timeout = (CONFIG_SYS_HZ *
363 NFC_DEFAULT_TIMEOUT_MS) / 1000;
366 writel(0, nfc->regs + NFC_REG_ECC_CTL);
367 writel(NFC_RESET, nfc->regs + NFC_REG_CTL);
369 time_start = get_timer(0);
371 if (!(readl(nfc->regs + NFC_REG_CTL) & NFC_RESET))
373 } while (get_timer(time_start) < timeout);
375 dev_err(nfc->dev, "wait for NAND controller reset timedout\n");
379 static int sunxi_nfc_dev_ready(struct mtd_info *mtd)
381 struct nand_chip *nand = mtd_to_nand(mtd);
382 struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
383 struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
384 struct sunxi_nand_rb *rb;
385 unsigned long timeo = (sunxi_nand->nand.state == FL_ERASING ? 400 : 20);
388 if (sunxi_nand->selected < 0)
391 rb = &sunxi_nand->sels[sunxi_nand->selected].rb;
395 ret = !!(readl(nfc->regs + NFC_REG_ST) &
396 NFC_RB_STATE(rb->info.nativeid));
400 sunxi_nfc_wait_int(nfc, NFC_RB_B2R, timeo);
401 ret = !!(readl(nfc->regs + NFC_REG_ST) &
402 NFC_RB_STATE(rb->info.nativeid));
405 ret = dm_gpio_get_value(&rb->info.gpio);
410 dev_err(nfc->dev, "cannot check R/B NAND status!\n");
417 static void sunxi_nfc_select_chip(struct mtd_info *mtd, int chip)
419 struct nand_chip *nand = mtd_to_nand(mtd);
420 struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
421 struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
422 struct sunxi_nand_chip_sel *sel;
425 if (chip > 0 && chip >= sunxi_nand->nsels)
428 if (chip == sunxi_nand->selected)
431 ctl = readl(nfc->regs + NFC_REG_CTL) &
432 ~(NFC_PAGE_SHIFT_MSK | NFC_CE_SEL_MSK | NFC_RB_SEL_MSK | NFC_EN);
435 sel = &sunxi_nand->sels[chip];
437 ctl |= NFC_CE_SEL(sel->cs) | NFC_EN |
438 NFC_PAGE_SHIFT(nand->page_shift - 10);
439 if (sel->rb.type == RB_NONE) {
440 nand->dev_ready = NULL;
442 nand->dev_ready = sunxi_nfc_dev_ready;
443 if (sel->rb.type == RB_NATIVE)
444 ctl |= NFC_RB_SEL(sel->rb.info.nativeid);
447 writel(mtd->writesize, nfc->regs + NFC_REG_SPARE_AREA);
449 if (nfc->clk_rate != sunxi_nand->clk_rate) {
450 sunxi_nfc_set_clk_rate(sunxi_nand->clk_rate);
451 nfc->clk_rate = sunxi_nand->clk_rate;
455 writel(sunxi_nand->timing_ctl, nfc->regs + NFC_REG_TIMING_CTL);
456 writel(sunxi_nand->timing_cfg, nfc->regs + NFC_REG_TIMING_CFG);
457 writel(ctl, nfc->regs + NFC_REG_CTL);
459 sunxi_nand->selected = chip;
462 static void sunxi_nfc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
464 struct nand_chip *nand = mtd_to_nand(mtd);
465 struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
466 struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
473 cnt = min(len - offs, NFC_SRAM_SIZE);
475 ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
479 writel(cnt, nfc->regs + NFC_REG_CNT);
480 tmp = NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD;
481 writel(tmp, nfc->regs + NFC_REG_CMD);
483 ret = sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
488 memcpy_fromio(buf + offs, nfc->regs + NFC_RAM0_BASE,
494 static void sunxi_nfc_write_buf(struct mtd_info *mtd, const uint8_t *buf,
497 struct nand_chip *nand = mtd_to_nand(mtd);
498 struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
499 struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
506 cnt = min(len - offs, NFC_SRAM_SIZE);
508 ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
512 writel(cnt, nfc->regs + NFC_REG_CNT);
513 memcpy_toio(nfc->regs + NFC_RAM0_BASE, buf + offs, cnt);
514 tmp = NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD |
516 writel(tmp, nfc->regs + NFC_REG_CMD);
518 ret = sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
526 static uint8_t sunxi_nfc_read_byte(struct mtd_info *mtd)
530 sunxi_nfc_read_buf(mtd, &ret, 1);
535 static void sunxi_nfc_cmd_ctrl(struct mtd_info *mtd, int dat,
538 struct nand_chip *nand = mtd_to_nand(mtd);
539 struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
540 struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
544 ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
548 if (ctrl & NAND_CTRL_CHANGE) {
549 tmp = readl(nfc->regs + NFC_REG_CTL);
554 writel(tmp, nfc->regs + NFC_REG_CTL);
557 if (dat == NAND_CMD_NONE && (ctrl & NAND_NCE) &&
558 !(ctrl & (NAND_CLE | NAND_ALE))) {
561 if (!sunxi_nand->addr_cycles && !sunxi_nand->cmd_cycles)
564 if (sunxi_nand->cmd_cycles--)
565 cmd |= NFC_SEND_CMD1 | sunxi_nand->cmd[0];
567 if (sunxi_nand->cmd_cycles--) {
568 cmd |= NFC_SEND_CMD2;
569 writel(sunxi_nand->cmd[1],
570 nfc->regs + NFC_REG_RCMD_SET);
573 sunxi_nand->cmd_cycles = 0;
575 if (sunxi_nand->addr_cycles) {
576 cmd |= NFC_SEND_ADR |
577 NFC_ADR_NUM(sunxi_nand->addr_cycles);
578 writel(sunxi_nand->addr[0],
579 nfc->regs + NFC_REG_ADDR_LOW);
582 if (sunxi_nand->addr_cycles > 4)
583 writel(sunxi_nand->addr[1],
584 nfc->regs + NFC_REG_ADDR_HIGH);
586 writel(cmd, nfc->regs + NFC_REG_CMD);
587 sunxi_nand->addr[0] = 0;
588 sunxi_nand->addr[1] = 0;
589 sunxi_nand->addr_cycles = 0;
590 sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
593 if (ctrl & NAND_CLE) {
594 sunxi_nand->cmd[sunxi_nand->cmd_cycles++] = dat;
595 } else if (ctrl & NAND_ALE) {
596 sunxi_nand->addr[sunxi_nand->addr_cycles / 4] |=
597 dat << ((sunxi_nand->addr_cycles % 4) * 8);
598 sunxi_nand->addr_cycles++;
602 /* These seed values have been extracted from Allwinner's BSP */
603 static const u16 sunxi_nfc_randomizer_page_seeds[] = {
604 0x2b75, 0x0bd0, 0x5ca3, 0x62d1, 0x1c93, 0x07e9, 0x2162, 0x3a72,
605 0x0d67, 0x67f9, 0x1be7, 0x077d, 0x032f, 0x0dac, 0x2716, 0x2436,
606 0x7922, 0x1510, 0x3860, 0x5287, 0x480f, 0x4252, 0x1789, 0x5a2d,
607 0x2a49, 0x5e10, 0x437f, 0x4b4e, 0x2f45, 0x216e, 0x5cb7, 0x7130,
608 0x2a3f, 0x60e4, 0x4dc9, 0x0ef0, 0x0f52, 0x1bb9, 0x6211, 0x7a56,
609 0x226d, 0x4ea7, 0x6f36, 0x3692, 0x38bf, 0x0c62, 0x05eb, 0x4c55,
610 0x60f4, 0x728c, 0x3b6f, 0x2037, 0x7f69, 0x0936, 0x651a, 0x4ceb,
611 0x6218, 0x79f3, 0x383f, 0x18d9, 0x4f05, 0x5c82, 0x2912, 0x6f17,
612 0x6856, 0x5938, 0x1007, 0x61ab, 0x3e7f, 0x57c2, 0x542f, 0x4f62,
613 0x7454, 0x2eac, 0x7739, 0x42d4, 0x2f90, 0x435a, 0x2e52, 0x2064,
614 0x637c, 0x66ad, 0x2c90, 0x0bad, 0x759c, 0x0029, 0x0986, 0x7126,
615 0x1ca7, 0x1605, 0x386a, 0x27f5, 0x1380, 0x6d75, 0x24c3, 0x0f8e,
616 0x2b7a, 0x1418, 0x1fd1, 0x7dc1, 0x2d8e, 0x43af, 0x2267, 0x7da3,
617 0x4e3d, 0x1338, 0x50db, 0x454d, 0x764d, 0x40a3, 0x42e6, 0x262b,
618 0x2d2e, 0x1aea, 0x2e17, 0x173d, 0x3a6e, 0x71bf, 0x25f9, 0x0a5d,
619 0x7c57, 0x0fbe, 0x46ce, 0x4939, 0x6b17, 0x37bb, 0x3e91, 0x76db,
623 * sunxi_nfc_randomizer_ecc512_seeds and sunxi_nfc_randomizer_ecc1024_seeds
624 * have been generated using
625 * sunxi_nfc_randomizer_step(seed, (step_size * 8) + 15), which is what
626 * the randomizer engine does internally before de/scrambling OOB data.
628 * Those tables are statically defined to avoid calculating randomizer state
631 static const u16 sunxi_nfc_randomizer_ecc512_seeds[] = {
632 0x3346, 0x367f, 0x1f18, 0x769a, 0x4f64, 0x068c, 0x2ef1, 0x6b64,
633 0x28a9, 0x15d7, 0x30f8, 0x3659, 0x53db, 0x7c5f, 0x71d4, 0x4409,
634 0x26eb, 0x03cc, 0x655d, 0x47d4, 0x4daa, 0x0877, 0x712d, 0x3617,
635 0x3264, 0x49aa, 0x7f9e, 0x588e, 0x4fbc, 0x7176, 0x7f91, 0x6c6d,
636 0x4b95, 0x5fb7, 0x3844, 0x4037, 0x0184, 0x081b, 0x0ee8, 0x5b91,
637 0x293d, 0x1f71, 0x0e6f, 0x402b, 0x5122, 0x1e52, 0x22be, 0x3d2d,
638 0x75bc, 0x7c60, 0x6291, 0x1a2f, 0x61d4, 0x74aa, 0x4140, 0x29ab,
639 0x472d, 0x2852, 0x017e, 0x15e8, 0x5ec2, 0x17cf, 0x7d0f, 0x06b8,
640 0x117a, 0x6b94, 0x789b, 0x3126, 0x6ac5, 0x5be7, 0x150f, 0x51f8,
641 0x7889, 0x0aa5, 0x663d, 0x77e8, 0x0b87, 0x3dcb, 0x360d, 0x218b,
642 0x512f, 0x7dc9, 0x6a4d, 0x630a, 0x3547, 0x1dd2, 0x5aea, 0x69a5,
643 0x7bfa, 0x5e4f, 0x1519, 0x6430, 0x3a0e, 0x5eb3, 0x5425, 0x0c7a,
644 0x5540, 0x3670, 0x63c1, 0x31e9, 0x5a39, 0x2de7, 0x5979, 0x2891,
645 0x1562, 0x014b, 0x5b05, 0x2756, 0x5a34, 0x13aa, 0x6cb5, 0x2c36,
646 0x5e72, 0x1306, 0x0861, 0x15ef, 0x1ee8, 0x5a37, 0x7ac4, 0x45dd,
647 0x44c4, 0x7266, 0x2f41, 0x3ccc, 0x045e, 0x7d40, 0x7c66, 0x0fa0,
650 static const u16 sunxi_nfc_randomizer_ecc1024_seeds[] = {
651 0x2cf5, 0x35f1, 0x63a4, 0x5274, 0x2bd2, 0x778b, 0x7285, 0x32b6,
652 0x6a5c, 0x70d6, 0x757d, 0x6769, 0x5375, 0x1e81, 0x0cf3, 0x3982,
653 0x6787, 0x042a, 0x6c49, 0x1925, 0x56a8, 0x40a9, 0x063e, 0x7bd9,
654 0x4dbf, 0x55ec, 0x672e, 0x7334, 0x5185, 0x4d00, 0x232a, 0x7e07,
655 0x445d, 0x6b92, 0x528f, 0x4255, 0x53ba, 0x7d82, 0x2a2e, 0x3a4e,
656 0x75eb, 0x450c, 0x6844, 0x1b5d, 0x581a, 0x4cc6, 0x0379, 0x37b2,
657 0x419f, 0x0e92, 0x6b27, 0x5624, 0x01e3, 0x07c1, 0x44a5, 0x130c,
658 0x13e8, 0x5910, 0x0876, 0x60c5, 0x54e3, 0x5b7f, 0x2269, 0x509f,
659 0x7665, 0x36fd, 0x3e9a, 0x0579, 0x6295, 0x14ef, 0x0a81, 0x1bcc,
660 0x4b16, 0x64db, 0x0514, 0x4f07, 0x0591, 0x3576, 0x6853, 0x0d9e,
661 0x259f, 0x38b7, 0x64fb, 0x3094, 0x4693, 0x6ddd, 0x29bb, 0x0bc8,
662 0x3f47, 0x490e, 0x0c0e, 0x7933, 0x3c9e, 0x5840, 0x398d, 0x3e68,
663 0x4af1, 0x71f5, 0x57cf, 0x1121, 0x64eb, 0x3579, 0x15ac, 0x584d,
664 0x5f2a, 0x47e2, 0x6528, 0x6eac, 0x196e, 0x6b96, 0x0450, 0x0179,
665 0x609c, 0x06e1, 0x4626, 0x42c7, 0x273e, 0x486f, 0x0705, 0x1601,
666 0x145b, 0x407e, 0x062b, 0x57a5, 0x53f9, 0x5659, 0x4410, 0x3ccd,
669 static u16 sunxi_nfc_randomizer_step(u16 state, int count)
674 * This loop is just a simple implementation of a Fibonacci LFSR using
675 * the x16 + x15 + 1 polynomial.
678 state = ((state >> 1) |
679 (((state ^ (state >> 1)) & 1) << 14)) & 0x7fff;
684 static u16 sunxi_nfc_randomizer_state(struct mtd_info *mtd, int page, bool ecc)
686 const u16 *seeds = sunxi_nfc_randomizer_page_seeds;
687 int mod = mtd->erasesize / mtd->writesize;
689 if (mod > ARRAY_SIZE(sunxi_nfc_randomizer_page_seeds))
690 mod = ARRAY_SIZE(sunxi_nfc_randomizer_page_seeds);
693 if (mtd->ecc_step_size == 512)
694 seeds = sunxi_nfc_randomizer_ecc512_seeds;
696 seeds = sunxi_nfc_randomizer_ecc1024_seeds;
699 return seeds[page % mod];
702 static void sunxi_nfc_randomizer_config(struct mtd_info *mtd,
705 struct nand_chip *nand = mtd_to_nand(mtd);
706 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
707 u32 ecc_ctl = readl(nfc->regs + NFC_REG_ECC_CTL);
710 if (!(nand->options & NAND_NEED_SCRAMBLING))
713 ecc_ctl = readl(nfc->regs + NFC_REG_ECC_CTL);
714 state = sunxi_nfc_randomizer_state(mtd, page, ecc);
715 ecc_ctl = readl(nfc->regs + NFC_REG_ECC_CTL) & ~NFC_RANDOM_SEED_MSK;
716 writel(ecc_ctl | NFC_RANDOM_SEED(state), nfc->regs + NFC_REG_ECC_CTL);
719 static void sunxi_nfc_randomizer_enable(struct mtd_info *mtd)
721 struct nand_chip *nand = mtd_to_nand(mtd);
722 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
724 if (!(nand->options & NAND_NEED_SCRAMBLING))
727 writel(readl(nfc->regs + NFC_REG_ECC_CTL) | NFC_RANDOM_EN,
728 nfc->regs + NFC_REG_ECC_CTL);
731 static void sunxi_nfc_randomizer_disable(struct mtd_info *mtd)
733 struct nand_chip *nand = mtd_to_nand(mtd);
734 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
736 if (!(nand->options & NAND_NEED_SCRAMBLING))
739 writel(readl(nfc->regs + NFC_REG_ECC_CTL) & ~NFC_RANDOM_EN,
740 nfc->regs + NFC_REG_ECC_CTL);
743 static void sunxi_nfc_randomize_bbm(struct mtd_info *mtd, int page, u8 *bbm)
745 u16 state = sunxi_nfc_randomizer_state(mtd, page, true);
748 bbm[1] ^= sunxi_nfc_randomizer_step(state, 8);
751 static void sunxi_nfc_randomizer_write_buf(struct mtd_info *mtd,
752 const uint8_t *buf, int len,
755 sunxi_nfc_randomizer_config(mtd, page, ecc);
756 sunxi_nfc_randomizer_enable(mtd);
757 sunxi_nfc_write_buf(mtd, buf, len);
758 sunxi_nfc_randomizer_disable(mtd);
761 static void sunxi_nfc_randomizer_read_buf(struct mtd_info *mtd, uint8_t *buf,
762 int len, bool ecc, int page)
764 sunxi_nfc_randomizer_config(mtd, page, ecc);
765 sunxi_nfc_randomizer_enable(mtd);
766 sunxi_nfc_read_buf(mtd, buf, len);
767 sunxi_nfc_randomizer_disable(mtd);
770 static void sunxi_nfc_hw_ecc_enable(struct mtd_info *mtd)
772 struct nand_chip *nand = mtd_to_nand(mtd);
773 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
774 struct sunxi_nand_hw_ecc *data = nand->ecc.priv;
777 ecc_ctl = readl(nfc->regs + NFC_REG_ECC_CTL);
778 ecc_ctl &= ~(NFC_ECC_MODE_MSK | NFC_ECC_PIPELINE |
779 NFC_ECC_BLOCK_SIZE_MSK);
780 ecc_ctl |= NFC_ECC_EN | NFC_ECC_MODE(data->mode) | NFC_ECC_EXCEPTION;
782 if (nand->ecc.size == 512)
783 ecc_ctl |= NFC_ECC_BLOCK_512;
785 writel(ecc_ctl, nfc->regs + NFC_REG_ECC_CTL);
788 static void sunxi_nfc_hw_ecc_disable(struct mtd_info *mtd)
790 struct nand_chip *nand = mtd_to_nand(mtd);
791 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
793 writel(readl(nfc->regs + NFC_REG_ECC_CTL) & ~NFC_ECC_EN,
794 nfc->regs + NFC_REG_ECC_CTL);
797 static inline void sunxi_nfc_user_data_to_buf(u32 user_data, u8 *buf)
800 buf[1] = user_data >> 8;
801 buf[2] = user_data >> 16;
802 buf[3] = user_data >> 24;
805 static int sunxi_nfc_hw_ecc_read_chunk(struct mtd_info *mtd,
806 u8 *data, int data_off,
807 u8 *oob, int oob_off,
809 unsigned int *max_bitflips,
812 struct nand_chip *nand = mtd_to_nand(mtd);
813 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
814 struct nand_ecc_ctrl *ecc = &nand->ecc;
819 if (*cur_off != data_off)
820 nand->cmdfunc(mtd, NAND_CMD_RNDOUT, data_off, -1);
822 sunxi_nfc_randomizer_read_buf(mtd, NULL, ecc->size, false, page);
824 if (data_off + ecc->size != oob_off)
825 nand->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_off, -1);
827 ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
831 sunxi_nfc_randomizer_enable(mtd);
832 writel(NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD | NFC_ECC_OP,
833 nfc->regs + NFC_REG_CMD);
835 ret = sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
836 sunxi_nfc_randomizer_disable(mtd);
840 *cur_off = oob_off + ecc->bytes + 4;
842 status = readl(nfc->regs + NFC_REG_ECC_ST);
843 if (status & NFC_ECC_PAT_FOUND(0)) {
846 if (unlikely(!(readl(nfc->regs + NFC_REG_PAT_ID) & 0x1)))
849 memset(data, pattern, ecc->size);
850 memset(oob, pattern, ecc->bytes + 4);
855 ret = NFC_ECC_ERR_CNT(0, readl(nfc->regs + NFC_REG_ECC_ERR_CNT(0)));
857 memcpy_fromio(data, nfc->regs + NFC_RAM0_BASE, ecc->size);
859 nand->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_off, -1);
860 sunxi_nfc_randomizer_read_buf(mtd, oob, ecc->bytes + 4, true, page);
862 if (status & NFC_ECC_ERR(0)) {
864 * Re-read the data with the randomizer disabled to identify
865 * bitflips in erased pages.
867 if (nand->options & NAND_NEED_SCRAMBLING) {
868 nand->cmdfunc(mtd, NAND_CMD_RNDOUT, data_off, -1);
869 nand->read_buf(mtd, data, ecc->size);
870 nand->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_off, -1);
871 nand->read_buf(mtd, oob, ecc->bytes + 4);
874 ret = nand_check_erased_ecc_chunk(data, ecc->size,
876 NULL, 0, ecc->strength);
881 * The engine protects 4 bytes of OOB data per chunk.
882 * Retrieve the corrected OOB bytes.
884 sunxi_nfc_user_data_to_buf(readl(nfc->regs +
885 NFC_REG_USER_DATA(0)),
888 /* De-randomize the Bad Block Marker. */
889 if (bbm && nand->options & NAND_NEED_SCRAMBLING)
890 sunxi_nfc_randomize_bbm(mtd, page, oob);
894 mtd->ecc_stats.failed++;
896 mtd->ecc_stats.corrected += ret;
897 *max_bitflips = max_t(unsigned int, *max_bitflips, ret);
903 static void sunxi_nfc_hw_ecc_read_extra_oob(struct mtd_info *mtd,
904 u8 *oob, int *cur_off,
905 bool randomize, int page)
907 struct nand_chip *nand = mtd_to_nand(mtd);
908 struct nand_ecc_ctrl *ecc = &nand->ecc;
909 int offset = ((ecc->bytes + 4) * ecc->steps);
910 int len = mtd->oobsize - offset;
915 if (*cur_off != offset)
916 nand->cmdfunc(mtd, NAND_CMD_RNDOUT,
917 offset + mtd->writesize, -1);
920 sunxi_nfc_read_buf(mtd, oob + offset, len);
922 sunxi_nfc_randomizer_read_buf(mtd, oob + offset, len,
925 *cur_off = mtd->oobsize + mtd->writesize;
928 static inline u32 sunxi_nfc_buf_to_user_data(const u8 *buf)
930 return buf[0] | (buf[1] << 8) | (buf[2] << 16) | (buf[3] << 24);
933 static int sunxi_nfc_hw_ecc_write_chunk(struct mtd_info *mtd,
934 const u8 *data, int data_off,
935 const u8 *oob, int oob_off,
936 int *cur_off, bool bbm,
939 struct nand_chip *nand = mtd_to_nand(mtd);
940 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
941 struct nand_ecc_ctrl *ecc = &nand->ecc;
944 if (data_off != *cur_off)
945 nand->cmdfunc(mtd, NAND_CMD_RNDIN, data_off, -1);
947 sunxi_nfc_randomizer_write_buf(mtd, data, ecc->size, false, page);
949 /* Fill OOB data in */
950 if ((nand->options & NAND_NEED_SCRAMBLING) && bbm) {
953 memcpy(user_data, oob, 4);
954 sunxi_nfc_randomize_bbm(mtd, page, user_data);
955 writel(sunxi_nfc_buf_to_user_data(user_data),
956 nfc->regs + NFC_REG_USER_DATA(0));
958 writel(sunxi_nfc_buf_to_user_data(oob),
959 nfc->regs + NFC_REG_USER_DATA(0));
962 if (data_off + ecc->size != oob_off)
963 nand->cmdfunc(mtd, NAND_CMD_RNDIN, oob_off, -1);
965 ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
969 sunxi_nfc_randomizer_enable(mtd);
970 writel(NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD |
971 NFC_ACCESS_DIR | NFC_ECC_OP,
972 nfc->regs + NFC_REG_CMD);
974 ret = sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
975 sunxi_nfc_randomizer_disable(mtd);
979 *cur_off = oob_off + ecc->bytes + 4;
984 static void sunxi_nfc_hw_ecc_write_extra_oob(struct mtd_info *mtd,
985 u8 *oob, int *cur_off,
988 struct nand_chip *nand = mtd_to_nand(mtd);
989 struct nand_ecc_ctrl *ecc = &nand->ecc;
990 int offset = ((ecc->bytes + 4) * ecc->steps);
991 int len = mtd->oobsize - offset;
996 if (*cur_off != offset)
997 nand->cmdfunc(mtd, NAND_CMD_RNDIN,
998 offset + mtd->writesize, -1);
1000 sunxi_nfc_randomizer_write_buf(mtd, oob + offset, len, false, page);
1002 *cur_off = mtd->oobsize + mtd->writesize;
1005 static int sunxi_nfc_hw_ecc_read_page(struct mtd_info *mtd,
1006 struct nand_chip *chip, uint8_t *buf,
1007 int oob_required, int page)
1009 struct nand_ecc_ctrl *ecc = &chip->ecc;
1010 unsigned int max_bitflips = 0;
1011 int ret, i, cur_off = 0;
1012 bool raw_mode = false;
1014 sunxi_nfc_hw_ecc_enable(mtd);
1016 for (i = 0; i < ecc->steps; i++) {
1017 int data_off = i * ecc->size;
1018 int oob_off = i * (ecc->bytes + 4);
1019 u8 *data = buf + data_off;
1020 u8 *oob = chip->oob_poi + oob_off;
1022 ret = sunxi_nfc_hw_ecc_read_chunk(mtd, data, data_off, oob,
1023 oob_off + mtd->writesize,
1024 &cur_off, &max_bitflips,
1033 sunxi_nfc_hw_ecc_read_extra_oob(mtd, chip->oob_poi, &cur_off,
1036 sunxi_nfc_hw_ecc_disable(mtd);
1038 return max_bitflips;
1041 static int sunxi_nfc_hw_ecc_read_subpage(struct mtd_info *mtd,
1042 struct nand_chip *chip,
1043 uint32_t data_offs, uint32_t readlen,
1044 uint8_t *bufpoi, int page)
1046 struct nand_ecc_ctrl *ecc = &chip->ecc;
1047 int ret, i, cur_off = 0;
1048 unsigned int max_bitflips = 0;
1050 sunxi_nfc_hw_ecc_enable(mtd);
1052 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1053 for (i = data_offs / ecc->size;
1054 i < DIV_ROUND_UP(data_offs + readlen, ecc->size); i++) {
1055 int data_off = i * ecc->size;
1056 int oob_off = i * (ecc->bytes + 4);
1057 u8 *data = bufpoi + data_off;
1058 u8 *oob = chip->oob_poi + oob_off;
1060 ret = sunxi_nfc_hw_ecc_read_chunk(mtd, data, data_off,
1061 oob, oob_off + mtd->writesize,
1062 &cur_off, &max_bitflips, !i, page);
1067 sunxi_nfc_hw_ecc_disable(mtd);
1069 return max_bitflips;
1072 static int sunxi_nfc_hw_ecc_write_page(struct mtd_info *mtd,
1073 struct nand_chip *chip,
1074 const uint8_t *buf, int oob_required,
1077 struct nand_ecc_ctrl *ecc = &chip->ecc;
1078 int ret, i, cur_off = 0;
1080 sunxi_nfc_hw_ecc_enable(mtd);
1082 for (i = 0; i < ecc->steps; i++) {
1083 int data_off = i * ecc->size;
1084 int oob_off = i * (ecc->bytes + 4);
1085 const u8 *data = buf + data_off;
1086 const u8 *oob = chip->oob_poi + oob_off;
1088 ret = sunxi_nfc_hw_ecc_write_chunk(mtd, data, data_off, oob,
1089 oob_off + mtd->writesize,
1090 &cur_off, !i, page);
1095 if (oob_required || (chip->options & NAND_NEED_SCRAMBLING))
1096 sunxi_nfc_hw_ecc_write_extra_oob(mtd, chip->oob_poi,
1099 sunxi_nfc_hw_ecc_disable(mtd);
1104 static int sunxi_nfc_hw_ecc_write_subpage(struct mtd_info *mtd,
1105 struct nand_chip *chip,
1106 u32 data_offs, u32 data_len,
1107 const u8 *buf, int oob_required,
1110 struct nand_ecc_ctrl *ecc = &chip->ecc;
1111 int ret, i, cur_off = 0;
1113 sunxi_nfc_hw_ecc_enable(mtd);
1115 for (i = data_offs / ecc->size;
1116 i < DIV_ROUND_UP(data_offs + data_len, ecc->size); i++) {
1117 int data_off = i * ecc->size;
1118 int oob_off = i * (ecc->bytes + 4);
1119 const u8 *data = buf + data_off;
1120 const u8 *oob = chip->oob_poi + oob_off;
1122 ret = sunxi_nfc_hw_ecc_write_chunk(mtd, data, data_off, oob,
1123 oob_off + mtd->writesize,
1124 &cur_off, !i, page);
1129 sunxi_nfc_hw_ecc_disable(mtd);
1134 static int sunxi_nfc_hw_syndrome_ecc_read_page(struct mtd_info *mtd,
1135 struct nand_chip *chip,
1136 uint8_t *buf, int oob_required,
1139 struct nand_ecc_ctrl *ecc = &chip->ecc;
1140 unsigned int max_bitflips = 0;
1141 int ret, i, cur_off = 0;
1142 bool raw_mode = false;
1144 sunxi_nfc_hw_ecc_enable(mtd);
1146 for (i = 0; i < ecc->steps; i++) {
1147 int data_off = i * (ecc->size + ecc->bytes + 4);
1148 int oob_off = data_off + ecc->size;
1149 u8 *data = buf + (i * ecc->size);
1150 u8 *oob = chip->oob_poi + (i * (ecc->bytes + 4));
1152 ret = sunxi_nfc_hw_ecc_read_chunk(mtd, data, data_off, oob,
1154 &max_bitflips, !i, page);
1162 sunxi_nfc_hw_ecc_read_extra_oob(mtd, chip->oob_poi, &cur_off,
1165 sunxi_nfc_hw_ecc_disable(mtd);
1167 return max_bitflips;
1170 static int sunxi_nfc_hw_syndrome_ecc_write_page(struct mtd_info *mtd,
1171 struct nand_chip *chip,
1173 int oob_required, int page)
1175 struct nand_ecc_ctrl *ecc = &chip->ecc;
1176 int ret, i, cur_off = 0;
1178 sunxi_nfc_hw_ecc_enable(mtd);
1180 for (i = 0; i < ecc->steps; i++) {
1181 int data_off = i * (ecc->size + ecc->bytes + 4);
1182 int oob_off = data_off + ecc->size;
1183 const u8 *data = buf + (i * ecc->size);
1184 const u8 *oob = chip->oob_poi + (i * (ecc->bytes + 4));
1186 ret = sunxi_nfc_hw_ecc_write_chunk(mtd, data, data_off,
1187 oob, oob_off, &cur_off,
1193 if (oob_required || (chip->options & NAND_NEED_SCRAMBLING))
1194 sunxi_nfc_hw_ecc_write_extra_oob(mtd, chip->oob_poi,
1197 sunxi_nfc_hw_ecc_disable(mtd);
1202 static const s32 tWB_lut[] = {6, 12, 16, 20};
1203 static const s32 tRHW_lut[] = {4, 8, 12, 20};
1205 static int _sunxi_nand_lookup_timing(const s32 *lut, int lut_size, u32 duration,
1208 u32 clk_cycles = DIV_ROUND_UP(duration, clk_period);
1211 for (i = 0; i < lut_size; i++) {
1212 if (clk_cycles <= lut[i])
1220 #define sunxi_nand_lookup_timing(l, p, c) \
1221 _sunxi_nand_lookup_timing(l, ARRAY_SIZE(l), p, c)
1223 static int sunxi_nand_chip_set_timings(struct sunxi_nand_chip *chip,
1224 const struct nand_sdr_timings *timings)
1226 u32 min_clk_period = 0;
1227 s32 tWB, tADL, tWHR, tRHW, tCAD;
1230 if (timings->tCLS_min > min_clk_period)
1231 min_clk_period = timings->tCLS_min;
1234 if (timings->tCLH_min > min_clk_period)
1235 min_clk_period = timings->tCLH_min;
1238 if (timings->tCS_min > min_clk_period)
1239 min_clk_period = timings->tCS_min;
1242 if (timings->tCH_min > min_clk_period)
1243 min_clk_period = timings->tCH_min;
1246 if (timings->tWP_min > min_clk_period)
1247 min_clk_period = timings->tWP_min;
1250 if (timings->tWH_min > min_clk_period)
1251 min_clk_period = timings->tWH_min;
1254 if (timings->tALS_min > min_clk_period)
1255 min_clk_period = timings->tALS_min;
1258 if (timings->tDS_min > min_clk_period)
1259 min_clk_period = timings->tDS_min;
1262 if (timings->tDH_min > min_clk_period)
1263 min_clk_period = timings->tDH_min;
1266 if (timings->tRR_min > (min_clk_period * 3))
1267 min_clk_period = DIV_ROUND_UP(timings->tRR_min, 3);
1270 if (timings->tALH_min > min_clk_period)
1271 min_clk_period = timings->tALH_min;
1274 if (timings->tRP_min > min_clk_period)
1275 min_clk_period = timings->tRP_min;
1278 if (timings->tREH_min > min_clk_period)
1279 min_clk_period = timings->tREH_min;
1282 if (timings->tRC_min > (min_clk_period * 2))
1283 min_clk_period = DIV_ROUND_UP(timings->tRC_min, 2);
1286 if (timings->tWC_min > (min_clk_period * 2))
1287 min_clk_period = DIV_ROUND_UP(timings->tWC_min, 2);
1289 /* T16 - T19 + tCAD */
1290 tWB = sunxi_nand_lookup_timing(tWB_lut, timings->tWB_max,
1293 dev_err(nfc->dev, "unsupported tWB\n");
1297 tADL = DIV_ROUND_UP(timings->tADL_min, min_clk_period) >> 3;
1299 dev_err(nfc->dev, "unsupported tADL\n");
1303 tWHR = DIV_ROUND_UP(timings->tWHR_min, min_clk_period) >> 3;
1305 dev_err(nfc->dev, "unsupported tWHR\n");
1309 tRHW = sunxi_nand_lookup_timing(tRHW_lut, timings->tRHW_min,
1312 dev_err(nfc->dev, "unsupported tRHW\n");
1317 * TODO: according to ONFI specs this value only applies for DDR NAND,
1318 * but Allwinner seems to set this to 0x7. Mimic them for now.
1322 /* TODO: A83 has some more bits for CDQSS, CS, CLHZ, CCS, WC */
1323 chip->timing_cfg = NFC_TIMING_CFG(tWB, tADL, tWHR, tRHW, tCAD);
1326 * ONFI specification 3.1, paragraph 4.15.2 dictates that EDO data
1327 * output cycle timings shall be used if the host drives tRC less than
1330 chip->timing_ctl = (timings->tRC_min < 30000) ? NFC_TIMING_CTL_EDO : 0;
1332 /* Convert min_clk_period from picoseconds to nanoseconds */
1333 min_clk_period = DIV_ROUND_UP(min_clk_period, 1000);
1336 * Convert min_clk_period into a clk frequency, then get the
1337 * appropriate rate for the NAND controller IP given this formula
1338 * (specified in the datasheet):
1339 * nand clk_rate = min_clk_rate
1341 chip->clk_rate = 1000000000L / min_clk_period;
1346 static int sunxi_nand_chip_init_timings(struct sunxi_nand_chip *chip)
1348 struct mtd_info *mtd = nand_to_mtd(&chip->nand);
1349 const struct nand_sdr_timings *timings;
1353 mode = onfi_get_async_timing_mode(&chip->nand);
1354 if (mode == ONFI_TIMING_MODE_UNKNOWN) {
1355 mode = chip->nand.onfi_timing_mode_default;
1357 uint8_t feature[ONFI_SUBFEATURE_PARAM_LEN] = {};
1360 mode = fls(mode) - 1;
1365 for (i = 0; i < chip->nsels; i++) {
1366 chip->nand.select_chip(mtd, i);
1367 ret = chip->nand.onfi_set_features(mtd,
1369 ONFI_FEATURE_ADDR_TIMING_MODE,
1371 chip->nand.select_chip(mtd, -1);
1372 if (ret && ret != -ENOTSUPP)
1377 timings = onfi_async_timing_mode_to_sdr_timings(mode);
1378 if (IS_ERR(timings))
1379 return PTR_ERR(timings);
1381 return sunxi_nand_chip_set_timings(chip, timings);
1384 static int sunxi_nand_hw_common_ecc_ctrl_init(struct mtd_info *mtd,
1385 struct nand_ecc_ctrl *ecc)
1387 static const u8 strengths[] = { 16, 24, 28, 32, 40, 48, 56, 60, 64 };
1388 struct sunxi_nand_hw_ecc *data;
1389 struct nand_ecclayout *layout;
1394 data = kzalloc(sizeof(*data), GFP_KERNEL);
1398 if (ecc->size != 512 && ecc->size != 1024)
1401 /* Prefer 1k ECC chunk over 512 ones */
1402 if (ecc->size == 512 && mtd->writesize > 512) {
1407 /* Add ECC info retrieval from DT */
1408 for (i = 0; i < ARRAY_SIZE(strengths); i++) {
1409 if (ecc->strength <= strengths[i]) {
1411 * Update ecc->strength value with the actual strength
1412 * that will be used by the ECC engine.
1414 ecc->strength = strengths[i];
1419 if (i >= ARRAY_SIZE(strengths)) {
1420 dev_err(nfc->dev, "unsupported strength\n");
1427 /* HW ECC always request ECC bytes for 1024 bytes blocks */
1428 ecc->bytes = DIV_ROUND_UP(ecc->strength * fls(8 * 1024), 8);
1430 /* HW ECC always work with even numbers of ECC bytes */
1431 ecc->bytes = ALIGN(ecc->bytes, 2);
1433 layout = &data->layout;
1434 nsectors = mtd->writesize / ecc->size;
1436 if (mtd->oobsize < ((ecc->bytes + 4) * nsectors)) {
1441 layout->eccbytes = (ecc->bytes * nsectors);
1443 ecc->layout = layout;
1455 static void sunxi_nand_hw_common_ecc_ctrl_cleanup(struct nand_ecc_ctrl *ecc)
1459 #endif /* __UBOOT__ */
1461 static int sunxi_nand_hw_ecc_ctrl_init(struct mtd_info *mtd,
1462 struct nand_ecc_ctrl *ecc)
1464 struct nand_ecclayout *layout;
1469 ret = sunxi_nand_hw_common_ecc_ctrl_init(mtd, ecc);
1473 ecc->read_page = sunxi_nfc_hw_ecc_read_page;
1474 ecc->write_page = sunxi_nfc_hw_ecc_write_page;
1475 ecc->read_subpage = sunxi_nfc_hw_ecc_read_subpage;
1476 ecc->write_subpage = sunxi_nfc_hw_ecc_write_subpage;
1477 layout = ecc->layout;
1478 nsectors = mtd->writesize / ecc->size;
1480 for (i = 0; i < nsectors; i++) {
1482 layout->oobfree[i].offset =
1483 layout->oobfree[i - 1].offset +
1484 layout->oobfree[i - 1].length +
1486 layout->oobfree[i].length = 4;
1489 * The first 2 bytes are used for BB markers, hence we
1490 * only have 2 bytes available in the first user data
1493 layout->oobfree[i].length = 2;
1494 layout->oobfree[i].offset = 2;
1497 for (j = 0; j < ecc->bytes; j++)
1498 layout->eccpos[(ecc->bytes * i) + j] =
1499 layout->oobfree[i].offset +
1500 layout->oobfree[i].length + j;
1503 if (mtd->oobsize > (ecc->bytes + 4) * nsectors) {
1504 layout->oobfree[nsectors].offset =
1505 layout->oobfree[nsectors - 1].offset +
1506 layout->oobfree[nsectors - 1].length +
1508 layout->oobfree[nsectors].length = mtd->oobsize -
1509 ((ecc->bytes + 4) * nsectors);
1515 static int sunxi_nand_hw_syndrome_ecc_ctrl_init(struct mtd_info *mtd,
1516 struct nand_ecc_ctrl *ecc)
1518 struct nand_ecclayout *layout;
1523 ret = sunxi_nand_hw_common_ecc_ctrl_init(mtd, ecc);
1528 ecc->read_page = sunxi_nfc_hw_syndrome_ecc_read_page;
1529 ecc->write_page = sunxi_nfc_hw_syndrome_ecc_write_page;
1531 layout = ecc->layout;
1532 nsectors = mtd->writesize / ecc->size;
1534 for (i = 0; i < (ecc->bytes * nsectors); i++)
1535 layout->eccpos[i] = i;
1537 layout->oobfree[0].length = mtd->oobsize - i;
1538 layout->oobfree[0].offset = i;
1544 static void sunxi_nand_ecc_cleanup(struct nand_ecc_ctrl *ecc)
1546 switch (ecc->mode) {
1548 case NAND_ECC_HW_SYNDROME:
1549 sunxi_nand_hw_common_ecc_ctrl_cleanup(ecc);
1557 #endif /* __UBOOT__ */
1559 static int sunxi_nand_ecc_init(struct mtd_info *mtd, struct nand_ecc_ctrl *ecc)
1561 struct nand_chip *nand = mtd_to_nand(mtd);
1565 ecc->size = nand->ecc_step_ds;
1566 ecc->strength = nand->ecc_strength_ds;
1569 if (!ecc->size || !ecc->strength)
1572 switch (ecc->mode) {
1573 case NAND_ECC_SOFT_BCH:
1576 ret = sunxi_nand_hw_ecc_ctrl_init(mtd, ecc);
1580 case NAND_ECC_HW_SYNDROME:
1581 ret = sunxi_nand_hw_syndrome_ecc_ctrl_init(mtd, ecc);
1586 ecc->layout = kzalloc(sizeof(*ecc->layout), GFP_KERNEL);
1589 ecc->layout->oobfree[0].length = mtd->oobsize;
1599 static int sunxi_nand_chip_init(int node, struct sunxi_nfc *nfc, int devnum)
1601 const struct nand_sdr_timings *timings;
1602 const void *blob = gd->fdt_blob;
1603 struct sunxi_nand_chip *chip;
1604 struct mtd_info *mtd;
1605 struct nand_chip *nand;
1611 if (!fdt_getprop(blob, node, "reg", &nsels))
1614 nsels /= sizeof(u32);
1615 if (!nsels || nsels > 8) {
1616 dev_err(dev, "invalid reg property size\n");
1620 chip = kzalloc(sizeof(*chip) +
1621 (nsels * sizeof(struct sunxi_nand_chip_sel)),
1624 dev_err(dev, "could not allocate chip\n");
1628 chip->nsels = nsels;
1629 chip->selected = -1;
1631 for (i = 0; i < nsels; i++) {
1636 ret = fdtdec_get_int_array(gd->fdt_blob, node, "reg", cs, nsels);
1638 dev_err(dev, "could not retrieve reg property: %d\n", ret);
1642 ret = fdtdec_get_int_array(gd->fdt_blob, node, "allwinner,rb", rb,
1645 dev_err(dev, "could not retrieve reg property: %d\n", ret);
1649 for (i = 0; i < nsels; i++) {
1652 if (tmp > NFC_MAX_CS) {
1654 "invalid reg value: %u (max CS = 7)\n",
1659 if (test_and_set_bit(tmp, &nfc->assigned_cs)) {
1660 dev_err(dev, "CS %d already assigned\n", tmp);
1664 chip->sels[i].cs = tmp;
1667 if (tmp >= 0 && tmp < 2) {
1668 chip->sels[i].rb.type = RB_NATIVE;
1669 chip->sels[i].rb.info.nativeid = tmp;
1671 ret = gpio_request_by_name_nodev(offset_to_ofnode(node),
1673 &chip->sels[i].rb.info.gpio,
1676 chip->sels[i].rb.type = RB_GPIO;
1678 chip->sels[i].rb.type = RB_NONE;
1682 timings = onfi_async_timing_mode_to_sdr_timings(0);
1683 if (IS_ERR(timings)) {
1684 ret = PTR_ERR(timings);
1686 "could not retrieve timings for ONFI mode 0: %d\n",
1691 ret = sunxi_nand_chip_set_timings(chip, timings);
1693 dev_err(dev, "could not configure chip timings: %d\n", ret);
1698 /* Default tR value specified in the ONFI spec (chapter 4.15.1) */
1699 nand->chip_delay = 200;
1700 nand->controller = &nfc->controller;
1702 * Set the ECC mode to the default value in case nothing is specified
1705 nand->ecc.mode = NAND_ECC_HW;
1706 nand->flash_node = node;
1707 nand->select_chip = sunxi_nfc_select_chip;
1708 nand->cmd_ctrl = sunxi_nfc_cmd_ctrl;
1709 nand->read_buf = sunxi_nfc_read_buf;
1710 nand->write_buf = sunxi_nfc_write_buf;
1711 nand->read_byte = sunxi_nfc_read_byte;
1713 mtd = nand_to_mtd(nand);
1714 ret = nand_scan_ident(mtd, nsels, NULL);
1718 if (nand->bbt_options & NAND_BBT_USE_FLASH)
1719 nand->bbt_options |= NAND_BBT_NO_OOB;
1721 if (nand->options & NAND_NEED_SCRAMBLING)
1722 nand->options |= NAND_NO_SUBPAGE_WRITE;
1724 nand->options |= NAND_SUBPAGE_READ;
1726 ret = sunxi_nand_chip_init_timings(chip);
1728 dev_err(dev, "could not configure chip timings: %d\n", ret);
1732 ret = sunxi_nand_ecc_init(mtd, &nand->ecc);
1734 dev_err(dev, "ECC init failed: %d\n", ret);
1738 ret = nand_scan_tail(mtd);
1740 dev_err(dev, "nand_scan_tail failed: %d\n", ret);
1744 ret = nand_register(devnum, mtd);
1746 dev_err(dev, "failed to register mtd device: %d\n", ret);
1750 list_add_tail(&chip->node, &nfc->chips);
1755 static int sunxi_nand_chips_init(int node, struct sunxi_nfc *nfc)
1757 const void *blob = gd->fdt_blob;
1761 for (nand_node = fdt_first_subnode(blob, node); nand_node >= 0;
1762 nand_node = fdt_next_subnode(blob, nand_node))
1766 dev_err(dev, "too many NAND chips: %d (max = 8)\n", i);
1771 for (nand_node = fdt_first_subnode(blob, node); nand_node >= 0;
1772 nand_node = fdt_next_subnode(blob, nand_node)) {
1773 ret = sunxi_nand_chip_init(nand_node, nfc, i++);
1782 static void sunxi_nand_chips_cleanup(struct sunxi_nfc *nfc)
1784 struct sunxi_nand_chip *chip;
1786 while (!list_empty(&nfc->chips)) {
1787 chip = list_first_entry(&nfc->chips, struct sunxi_nand_chip,
1789 nand_release(&chip->mtd);
1790 sunxi_nand_ecc_cleanup(&chip->nand.ecc);
1791 list_del(&chip->node);
1795 #endif /* __UBOOT__ */
1797 void sunxi_nand_init(void)
1799 const void *blob = gd->fdt_blob;
1800 struct sunxi_nfc *nfc;
1805 nfc = kzalloc(sizeof(*nfc), GFP_KERNEL);
1809 spin_lock_init(&nfc->controller.lock);
1810 init_waitqueue_head(&nfc->controller.wq);
1811 INIT_LIST_HEAD(&nfc->chips);
1813 node = fdtdec_next_compatible(blob, 0, COMPAT_SUNXI_NAND);
1815 pr_err("unable to find nfc node in device tree\n");
1819 if (!fdtdec_get_is_enabled(blob, node)) {
1820 pr_err("nfc disabled in device tree\n");
1824 regs = fdtdec_get_addr(blob, node, "reg");
1825 if (regs == FDT_ADDR_T_NONE) {
1826 pr_err("unable to find nfc address in device tree\n");
1830 nfc->regs = (void *)regs;
1832 ret = sunxi_nfc_rst(nfc);
1836 ret = sunxi_nand_chips_init(node, nfc);
1838 dev_err(dev, "failed to init nand chips\n");
1848 MODULE_LICENSE("GPL v2");
1849 MODULE_AUTHOR("Boris BREZILLON");
1850 MODULE_DESCRIPTION("Allwinner NAND Flash Controller driver");