drivers/mtd/nand/raw/stm32_fmc2_nand.c

   1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
   2 /*
   3  * Copyright (C) STMicroelectronics 2019
   4  * Author: Christophe Kerello <christophe.kerello@st.com>
   5  */
   6
   7 #include <common.h>
   8 #include <clk.h>
   9 #include <dm.h>
  10 #include <log.h>
  11 #include <nand.h>
  12 #include <reset.h>
  13 #include <linux/bitops.h>
  14 #include <linux/delay.h>
  15 #include <linux/err.h>
  16 #include <linux/iopoll.h>
  17 #include <linux/ioport.h>
  18
  19 /* Bad block marker length */
  20 #define FMC2_BBM_LEN                    2
  21
  22 /* ECC step size */
  23 #define FMC2_ECC_STEP_SIZE              512
  24
  25 /* Command delay */
  26 #define FMC2_RB_DELAY_US                30
  27
  28 /* Max chip enable */
  29 #define FMC2_MAX_CE                     2
  30
  31 /* Timings */
  32 #define FMC2_THIZ                       1
  33 #define FMC2_TIO                        8000
  34 #define FMC2_TSYNC                      3000
  35 #define FMC2_PCR_TIMING_MASK            0xf
  36 #define FMC2_PMEM_PATT_TIMING_MASK      0xff
  37
  38 /* FMC2 Controller Registers */
  39 #define FMC2_BCR1                       0x0
  40 #define FMC2_PCR                        0x80
  41 #define FMC2_SR                         0x84
  42 #define FMC2_PMEM                       0x88
  43 #define FMC2_PATT                       0x8c
  44 #define FMC2_HECCR                      0x94
  45 #define FMC2_BCHISR                     0x254
  46 #define FMC2_BCHICR                     0x258
  47 #define FMC2_BCHPBR1                    0x260
  48 #define FMC2_BCHPBR2                    0x264
  49 #define FMC2_BCHPBR3                    0x268
  50 #define FMC2_BCHPBR4                    0x26c
  51 #define FMC2_BCHDSR0                    0x27c
  52 #define FMC2_BCHDSR1                    0x280
  53 #define FMC2_BCHDSR2                    0x284
  54 #define FMC2_BCHDSR3                    0x288
  55 #define FMC2_BCHDSR4                    0x28c
  56
  57 /* Register: FMC2_BCR1 */
  58 #define FMC2_BCR1_FMC2EN                BIT(31)
  59
  60 /* Register: FMC2_PCR */
  61 #define FMC2_PCR_PWAITEN                BIT(1)
  62 #define FMC2_PCR_PBKEN                  BIT(2)
  63 #define FMC2_PCR_PWID_MASK              GENMASK(5, 4)
  64 #define FMC2_PCR_PWID(x)                (((x) & 0x3) << 4)
  65 #define FMC2_PCR_PWID_BUSWIDTH_8        0
  66 #define FMC2_PCR_PWID_BUSWIDTH_16       1
  67 #define FMC2_PCR_ECCEN                  BIT(6)
  68 #define FMC2_PCR_ECCALG                 BIT(8)
  69 #define FMC2_PCR_TCLR_MASK              GENMASK(12, 9)
  70 #define FMC2_PCR_TCLR(x)                (((x) & 0xf) << 9)
  71 #define FMC2_PCR_TCLR_DEFAULT           0xf
  72 #define FMC2_PCR_TAR_MASK               GENMASK(16, 13)
  73 #define FMC2_PCR_TAR(x)                 (((x) & 0xf) << 13)
  74 #define FMC2_PCR_TAR_DEFAULT            0xf
  75 #define FMC2_PCR_ECCSS_MASK             GENMASK(19, 17)
  76 #define FMC2_PCR_ECCSS(x)               (((x) & 0x7) << 17)
  77 #define FMC2_PCR_ECCSS_512              1
  78 #define FMC2_PCR_ECCSS_2048             3
  79 #define FMC2_PCR_BCHECC                 BIT(24)
  80 #define FMC2_PCR_WEN                    BIT(25)
  81
  82 /* Register: FMC2_SR */
  83 #define FMC2_SR_NWRF                    BIT(6)
  84
  85 /* Register: FMC2_PMEM */
  86 #define FMC2_PMEM_MEMSET(x)             (((x) & 0xff) << 0)
  87 #define FMC2_PMEM_MEMWAIT(x)            (((x) & 0xff) << 8)
  88 #define FMC2_PMEM_MEMHOLD(x)            (((x) & 0xff) << 16)
  89 #define FMC2_PMEM_MEMHIZ(x)             (((x) & 0xff) << 24)
  90 #define FMC2_PMEM_DEFAULT               0x0a0a0a0a
  91
  92 /* Register: FMC2_PATT */
  93 #define FMC2_PATT_ATTSET(x)             (((x) & 0xff) << 0)
  94 #define FMC2_PATT_ATTWAIT(x)            (((x) & 0xff) << 8)
  95 #define FMC2_PATT_ATTHOLD(x)            (((x) & 0xff) << 16)
  96 #define FMC2_PATT_ATTHIZ(x)             (((x) & 0xff) << 24)
  97 #define FMC2_PATT_DEFAULT               0x0a0a0a0a
  98
  99 /* Register: FMC2_BCHISR */
 100 #define FMC2_BCHISR_DERF                BIT(1)
 101 #define FMC2_BCHISR_EPBRF               BIT(4)
 102
 103 /* Register: FMC2_BCHICR */
 104 #define FMC2_BCHICR_CLEAR_IRQ           GENMASK(4, 0)
 105
 106 /* Register: FMC2_BCHDSR0 */
 107 #define FMC2_BCHDSR0_DUE                BIT(0)
 108 #define FMC2_BCHDSR0_DEF                BIT(1)
 109 #define FMC2_BCHDSR0_DEN_MASK           GENMASK(7, 4)
 110 #define FMC2_BCHDSR0_DEN_SHIFT          4
 111
 112 /* Register: FMC2_BCHDSR1 */
 113 #define FMC2_BCHDSR1_EBP1_MASK          GENMASK(12, 0)
 114 #define FMC2_BCHDSR1_EBP2_MASK          GENMASK(28, 16)
 115 #define FMC2_BCHDSR1_EBP2_SHIFT         16
 116
 117 /* Register: FMC2_BCHDSR2 */
 118 #define FMC2_BCHDSR2_EBP3_MASK          GENMASK(12, 0)
 119 #define FMC2_BCHDSR2_EBP4_MASK          GENMASK(28, 16)
 120 #define FMC2_BCHDSR2_EBP4_SHIFT         16
 121
 122 /* Register: FMC2_BCHDSR3 */
 123 #define FMC2_BCHDSR3_EBP5_MASK          GENMASK(12, 0)
 124 #define FMC2_BCHDSR3_EBP6_MASK          GENMASK(28, 16)
 125 #define FMC2_BCHDSR3_EBP6_SHIFT         16
 126
 127 /* Register: FMC2_BCHDSR4 */
 128 #define FMC2_BCHDSR4_EBP7_MASK          GENMASK(12, 0)
 129 #define FMC2_BCHDSR4_EBP8_MASK          GENMASK(28, 16)
 130 #define FMC2_BCHDSR4_EBP8_SHIFT         16
 131
 132 #define FMC2_NSEC_PER_SEC               1000000000L
 133
 134 enum stm32_fmc2_ecc {
 135         FMC2_ECC_HAM = 1,
 136         FMC2_ECC_BCH4 = 4,
 137         FMC2_ECC_BCH8 = 8
 138 };
 139
 140 struct stm32_fmc2_timings {
 141         u8 tclr;
 142         u8 tar;
 143         u8 thiz;
 144         u8 twait;
 145         u8 thold_mem;
 146         u8 tset_mem;
 147         u8 thold_att;
 148         u8 tset_att;
 149 };
 150
 151 struct stm32_fmc2_nand {
 152         struct nand_chip chip;
 153         struct stm32_fmc2_timings timings;
 154         int ncs;
 155         int cs_used[FMC2_MAX_CE];
 156 };
 157
 158 static inline struct stm32_fmc2_nand *to_fmc2_nand(struct nand_chip *chip)
 159 {
 160         return container_of(chip, struct stm32_fmc2_nand, chip);
 161 }
 162
 163 struct stm32_fmc2_nfc {
 164         struct nand_hw_control base;
 165         struct stm32_fmc2_nand nand;
 166         struct nand_ecclayout ecclayout;
 167         void __iomem *io_base;
 168         void __iomem *data_base[FMC2_MAX_CE];
 169         void __iomem *cmd_base[FMC2_MAX_CE];
 170         void __iomem *addr_base[FMC2_MAX_CE];
 171         struct clk clk;
 172
 173         u8 cs_assigned;
 174         int cs_sel;
 175 };
 176
 177 static inline struct stm32_fmc2_nfc *to_stm32_nfc(struct nand_hw_control *base)
 178 {
 179         return container_of(base, struct stm32_fmc2_nfc, base);
 180 }
 181
 182 /* Timings configuration */
 183 static void stm32_fmc2_timings_init(struct nand_chip *chip)
 184 {
 185         struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
 186         struct stm32_fmc2_nand *nand = to_fmc2_nand(chip);
 187         struct stm32_fmc2_timings *timings = &nand->timings;
 188         u32 pcr = readl(fmc2->io_base + FMC2_PCR);
 189         u32 pmem, patt;
 190
 191         /* Set tclr/tar timings */
 192         pcr &= ~FMC2_PCR_TCLR_MASK;
 193         pcr |= FMC2_PCR_TCLR(timings->tclr);
 194         pcr &= ~FMC2_PCR_TAR_MASK;
 195         pcr |= FMC2_PCR_TAR(timings->tar);
 196
 197         /* Set tset/twait/thold/thiz timings in common bank */
 198         pmem = FMC2_PMEM_MEMSET(timings->tset_mem);
 199         pmem |= FMC2_PMEM_MEMWAIT(timings->twait);
 200         pmem |= FMC2_PMEM_MEMHOLD(timings->thold_mem);
 201         pmem |= FMC2_PMEM_MEMHIZ(timings->thiz);
 202
 203         /* Set tset/twait/thold/thiz timings in attribut bank */
 204         patt = FMC2_PATT_ATTSET(timings->tset_att);
 205         patt |= FMC2_PATT_ATTWAIT(timings->twait);
 206         patt |= FMC2_PATT_ATTHOLD(timings->thold_att);
 207         patt |= FMC2_PATT_ATTHIZ(timings->thiz);
 208
 209         writel(pcr, fmc2->io_base + FMC2_PCR);
 210         writel(pmem, fmc2->io_base + FMC2_PMEM);
 211         writel(patt, fmc2->io_base + FMC2_PATT);
 212 }
 213
 214 /* Controller configuration */
 215 static void stm32_fmc2_setup(struct nand_chip *chip)
 216 {
 217         struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
 218         u32 pcr = readl(fmc2->io_base + FMC2_PCR);
 219
 220         /* Configure ECC algorithm (default configuration is Hamming) */
 221         pcr &= ~FMC2_PCR_ECCALG;
 222         pcr &= ~FMC2_PCR_BCHECC;
 223         if (chip->ecc.strength == FMC2_ECC_BCH8) {
 224                 pcr |= FMC2_PCR_ECCALG;
 225                 pcr |= FMC2_PCR_BCHECC;
 226         } else if (chip->ecc.strength == FMC2_ECC_BCH4) {
 227                 pcr |= FMC2_PCR_ECCALG;
 228         }
 229
 230         /* Set buswidth */
 231         pcr &= ~FMC2_PCR_PWID_MASK;
 232         if (chip->options & NAND_BUSWIDTH_16)
 233                 pcr |= FMC2_PCR_PWID(FMC2_PCR_PWID_BUSWIDTH_16);
 234
 235         /* Set ECC sector size */
 236         pcr &= ~FMC2_PCR_ECCSS_MASK;
 237         pcr |= FMC2_PCR_ECCSS(FMC2_PCR_ECCSS_512);
 238
 239         writel(pcr, fmc2->io_base + FMC2_PCR);
 240 }
 241
 242 /* Select target */
 243 static void stm32_fmc2_select_chip(struct mtd_info *mtd, int chipnr)
 244 {
 245         struct nand_chip *chip = mtd_to_nand(mtd);
 246         struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
 247         struct stm32_fmc2_nand *nand = to_fmc2_nand(chip);
 248
 249         if (chipnr < 0 || chipnr >= nand->ncs)
 250                 return;
 251
 252         if (nand->cs_used[chipnr] == fmc2->cs_sel)
 253                 return;
 254
 255         fmc2->cs_sel = nand->cs_used[chipnr];
 256         chip->IO_ADDR_R = fmc2->data_base[fmc2->cs_sel];
 257         chip->IO_ADDR_W = fmc2->data_base[fmc2->cs_sel];
 258
 259         /* FMC2 setup routine */
 260         stm32_fmc2_setup(chip);
 261
 262         /* Apply timings */
 263         stm32_fmc2_timings_init(chip);
 264 }
 265
 266 /* Set bus width to 16-bit or 8-bit */
 267 static void stm32_fmc2_set_buswidth_16(struct stm32_fmc2_nfc *fmc2, bool set)
 268 {
 269         u32 pcr = readl(fmc2->io_base + FMC2_PCR);
 270
 271         pcr &= ~FMC2_PCR_PWID_MASK;
 272         if (set)
 273                 pcr |= FMC2_PCR_PWID(FMC2_PCR_PWID_BUSWIDTH_16);
 274         writel(pcr, fmc2->io_base + FMC2_PCR);
 275 }
 276
 277 /* Enable/disable ECC */
 278 static void stm32_fmc2_set_ecc(struct stm32_fmc2_nfc *fmc2, bool enable)
 279 {
 280         u32 pcr = readl(fmc2->io_base + FMC2_PCR);
 281
 282         pcr &= ~FMC2_PCR_ECCEN;
 283         if (enable)
 284                 pcr |= FMC2_PCR_ECCEN;
 285         writel(pcr, fmc2->io_base + FMC2_PCR);
 286 }
 287
 288 /* Clear irq sources in case of bch is used */
 289 static inline void stm32_fmc2_clear_bch_irq(struct stm32_fmc2_nfc *fmc2)
 290 {
 291         writel(FMC2_BCHICR_CLEAR_IRQ, fmc2->io_base + FMC2_BCHICR);
 292 }
 293
 294 /* Send command and address cycles */
 295 static void stm32_fmc2_cmd_ctrl(struct mtd_info *mtd, int cmd,
 296                                 unsigned int ctrl)
 297 {
 298         struct nand_chip *chip = mtd_to_nand(mtd);
 299         struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
 300
 301         if (cmd == NAND_CMD_NONE)
 302                 return;
 303
 304         if (ctrl & NAND_CLE) {
 305                 writeb(cmd, fmc2->cmd_base[fmc2->cs_sel]);
 306                 return;
 307         }
 308
 309         writeb(cmd, fmc2->addr_base[fmc2->cs_sel]);
 310 }
 311
 312 /*
 313  * Enable ECC logic and reset syndrome/parity bits previously calculated
 314  * Syndrome/parity bits is cleared by setting the ECCEN bit to 0
 315  */
 316 static void stm32_fmc2_hwctl(struct mtd_info *mtd, int mode)
 317 {
 318         struct nand_chip *chip = mtd_to_nand(mtd);
 319         struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
 320
 321         stm32_fmc2_set_ecc(fmc2, false);
 322
 323         if (chip->ecc.strength != FMC2_ECC_HAM) {
 324                 u32 pcr = readl(fmc2->io_base + FMC2_PCR);
 325
 326                 if (mode == NAND_ECC_WRITE)
 327                         pcr |= FMC2_PCR_WEN;
 328                 else
 329                         pcr &= ~FMC2_PCR_WEN;
 330                 writel(pcr, fmc2->io_base + FMC2_PCR);
 331
 332                 stm32_fmc2_clear_bch_irq(fmc2);
 333         }
 334
 335         stm32_fmc2_set_ecc(fmc2, true);
 336 }
 337
 338 /*
 339  * ECC Hamming calculation
 340  * ECC is 3 bytes for 512 bytes of data (supports error correction up to
 341  * max of 1-bit)
 342  */
 343 static int stm32_fmc2_ham_calculate(struct mtd_info *mtd, const u8 *data,
 344                                     u8 *ecc)
 345 {
 346         struct nand_chip *chip = mtd_to_nand(mtd);
 347         struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
 348         u32 heccr, sr;
 349         int ret;
 350
 351         ret = readl_poll_timeout(fmc2->io_base + FMC2_SR, sr,
 352                                  sr & FMC2_SR_NWRF, 10000);
 353         if (ret < 0) {
 354                 pr_err("Ham timeout\n");
 355                 return ret;
 356         }
 357
 358         heccr = readl(fmc2->io_base + FMC2_HECCR);
 359
 360         ecc[0] = heccr;
 361         ecc[1] = heccr >> 8;
 362         ecc[2] = heccr >> 16;
 363
 364         /* Disable ecc */
 365         stm32_fmc2_set_ecc(fmc2, false);
 366
 367         return 0;
 368 }
 369
 370 static int stm32_fmc2_ham_correct(struct mtd_info *mtd, u8 *dat,
 371                                   u8 *read_ecc, u8 *calc_ecc)
 372 {
 373         u8 bit_position = 0, b0, b1, b2;
 374         u32 byte_addr = 0, b;
 375         u32 i, shifting = 1;
 376
 377         /* Indicate which bit and byte is faulty (if any) */
 378         b0 = read_ecc[0] ^ calc_ecc[0];
 379         b1 = read_ecc[1] ^ calc_ecc[1];
 380         b2 = read_ecc[2] ^ calc_ecc[2];
 381         b = b0 | (b1 << 8) | (b2 << 16);
 382
 383         /* No errors */
 384         if (likely(!b))
 385                 return 0;
 386
 387         /* Calculate bit position */
 388         for (i = 0; i < 3; i++) {
 389                 switch (b % 4) {
 390                 case 2:
 391                         bit_position += shifting;
 392                 case 1:
 393                         break;
 394                 default:
 395                         return -EBADMSG;
 396                 }
 397                 shifting <<= 1;
 398                 b >>= 2;
 399         }
 400
 401         /* Calculate byte position */
 402         shifting = 1;
 403         for (i = 0; i < 9; i++) {
 404                 switch (b % 4) {
 405                 case 2:
 406                         byte_addr += shifting;
 407                 case 1:
 408                         break;
 409                 default:
 410                         return -EBADMSG;
 411                 }
 412                 shifting <<= 1;
 413                 b >>= 2;
 414         }
 415
 416         /* Flip the bit */
 417         dat[byte_addr] ^= (1 << bit_position);
 418
 419         return 1;
 420 }
 421
 422 /*
 423  * ECC BCH calculation and correction
 424  * ECC is 7/13 bytes for 512 bytes of data (supports error correction up to
 425  * max of 4-bit/8-bit)
 426  */
 427
 428 static int stm32_fmc2_bch_calculate(struct mtd_info *mtd, const u8 *data,
 429                                     u8 *ecc)
 430 {
 431         struct nand_chip *chip = mtd_to_nand(mtd);
 432         struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
 433         u32 bchpbr, bchisr;
 434         int ret;
 435
 436         /* Wait until the BCH code is ready */
 437         ret = readl_poll_timeout(fmc2->io_base + FMC2_BCHISR, bchisr,
 438                                  bchisr & FMC2_BCHISR_EPBRF, 10000);
 439         if (ret < 0) {
 440                 pr_err("Bch timeout\n");
 441                 return ret;
 442         }
 443
 444         /* Read parity bits */
 445         bchpbr = readl(fmc2->io_base + FMC2_BCHPBR1);
 446         ecc[0] = bchpbr;
 447         ecc[1] = bchpbr >> 8;
 448         ecc[2] = bchpbr >> 16;
 449         ecc[3] = bchpbr >> 24;
 450
 451         bchpbr = readl(fmc2->io_base + FMC2_BCHPBR2);
 452         ecc[4] = bchpbr;
 453         ecc[5] = bchpbr >> 8;
 454         ecc[6] = bchpbr >> 16;
 455
 456         if (chip->ecc.strength == FMC2_ECC_BCH8) {
 457                 ecc[7] = bchpbr >> 24;
 458
 459                 bchpbr = readl(fmc2->io_base + FMC2_BCHPBR3);
 460                 ecc[8] = bchpbr;
 461                 ecc[9] = bchpbr >> 8;
 462                 ecc[10] = bchpbr >> 16;
 463                 ecc[11] = bchpbr >> 24;
 464
 465                 bchpbr = readl(fmc2->io_base + FMC2_BCHPBR4);
 466                 ecc[12] = bchpbr;
 467         }
 468
 469         /* Disable ecc */
 470         stm32_fmc2_set_ecc(fmc2, false);
 471
 472         return 0;
 473 }
 474
 475 /* BCH algorithm correction */
 476 static int stm32_fmc2_bch_correct(struct mtd_info *mtd, u8 *dat,
 477                                   u8 *read_ecc, u8 *calc_ecc)
 478 {
 479         struct nand_chip *chip = mtd_to_nand(mtd);
 480         struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
 481         u32 bchdsr0, bchdsr1, bchdsr2, bchdsr3, bchdsr4, bchisr;
 482         u16 pos[8];
 483         int i, ret, den, eccsize = chip->ecc.size;
 484         unsigned int nb_errs = 0;
 485
 486         /* Wait until the decoding error is ready */
 487         ret = readl_poll_timeout(fmc2->io_base + FMC2_BCHISR, bchisr,
 488                                  bchisr & FMC2_BCHISR_DERF, 10000);
 489         if (ret < 0) {
 490                 pr_err("Bch timeout\n");
 491                 return ret;
 492         }
 493
 494         bchdsr0 = readl(fmc2->io_base + FMC2_BCHDSR0);
 495         bchdsr1 = readl(fmc2->io_base + FMC2_BCHDSR1);
 496         bchdsr2 = readl(fmc2->io_base + FMC2_BCHDSR2);
 497         bchdsr3 = readl(fmc2->io_base + FMC2_BCHDSR3);
 498         bchdsr4 = readl(fmc2->io_base + FMC2_BCHDSR4);
 499
 500         /* Disable ECC */
 501         stm32_fmc2_set_ecc(fmc2, false);
 502
 503         /* No errors found */
 504         if (likely(!(bchdsr0 & FMC2_BCHDSR0_DEF)))
 505                 return 0;
 506
 507         /* Too many errors detected */
 508         if (unlikely(bchdsr0 & FMC2_BCHDSR0_DUE))
 509                 return -EBADMSG;
 510
 511         pos[0] = bchdsr1 & FMC2_BCHDSR1_EBP1_MASK;
 512         pos[1] = (bchdsr1 & FMC2_BCHDSR1_EBP2_MASK) >> FMC2_BCHDSR1_EBP2_SHIFT;
 513         pos[2] = bchdsr2 & FMC2_BCHDSR2_EBP3_MASK;
 514         pos[3] = (bchdsr2 & FMC2_BCHDSR2_EBP4_MASK) >> FMC2_BCHDSR2_EBP4_SHIFT;
 515         pos[4] = bchdsr3 & FMC2_BCHDSR3_EBP5_MASK;
 516         pos[5] = (bchdsr3 & FMC2_BCHDSR3_EBP6_MASK) >> FMC2_BCHDSR3_EBP6_SHIFT;
 517         pos[6] = bchdsr4 & FMC2_BCHDSR4_EBP7_MASK;
 518         pos[7] = (bchdsr4 & FMC2_BCHDSR4_EBP8_MASK) >> FMC2_BCHDSR4_EBP8_SHIFT;
 519
 520         den = (bchdsr0 & FMC2_BCHDSR0_DEN_MASK) >> FMC2_BCHDSR0_DEN_SHIFT;
 521         for (i = 0; i < den; i++) {
 522                 if (pos[i] < eccsize * 8) {
 523                         __change_bit(pos[i], (unsigned long *)dat);
 524                         nb_errs++;
 525                 }
 526         }
 527
 528         return nb_errs;
 529 }
 530
 531 static int stm32_fmc2_read_page(struct mtd_info *mtd,
 532                                 struct nand_chip *chip, u8 *buf,
 533                                 int oob_required, int page)
 534 {
 535         int i, s, stat, eccsize = chip->ecc.size;
 536         int eccbytes = chip->ecc.bytes;
 537         int eccsteps = chip->ecc.steps;
 538         int eccstrength = chip->ecc.strength;
 539         u8 *p = buf;
 540         u8 *ecc_calc = chip->buffers->ecccalc;
 541         u8 *ecc_code = chip->buffers->ecccode;
 542         unsigned int max_bitflips = 0;
 543
 544         for (i = mtd->writesize + FMC2_BBM_LEN, s = 0; s < eccsteps;
 545              s++, i += eccbytes, p += eccsize) {
 546                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
 547
 548                 /* Read the nand page sector (512 bytes) */
 549                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, s * eccsize, -1);
 550                 chip->read_buf(mtd, p, eccsize);
 551
 552                 /* Read the corresponding ECC bytes */
 553                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, i, -1);
 554                 chip->read_buf(mtd, ecc_code, eccbytes);
 555
 556                 /* Correct the data */
 557                 stat = chip->ecc.correct(mtd, p, ecc_code, ecc_calc);
 558                 if (stat == -EBADMSG)
 559                         /* Check for empty pages with bitflips */
 560                         stat = nand_check_erased_ecc_chunk(p, eccsize,
 561                                                            ecc_code, eccbytes,
 562                                                            NULL, 0,
 563                                                            eccstrength);
 564
 565                 if (stat < 0) {
 566                         mtd->ecc_stats.failed++;
 567                 } else {
 568                         mtd->ecc_stats.corrected += stat;
 569                         max_bitflips = max_t(unsigned int, max_bitflips, stat);
 570                 }
 571         }
 572
 573         /* Read oob */
 574         if (oob_required) {
 575                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
 576                 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
 577         }
 578
 579         return max_bitflips;
 580 }
 581
 582 /* Controller initialization */
 583 static void stm32_fmc2_init(struct stm32_fmc2_nfc *fmc2)
 584 {
 585         u32 pcr = readl(fmc2->io_base + FMC2_PCR);
 586         u32 bcr1 = readl(fmc2->io_base + FMC2_BCR1);
 587
 588         /* Set CS used to undefined */
 589         fmc2->cs_sel = -1;
 590
 591         /* Enable wait feature and nand flash memory bank */
 592         pcr |= FMC2_PCR_PWAITEN;
 593         pcr |= FMC2_PCR_PBKEN;
 594
 595         /* Set buswidth to 8 bits mode for identification */
 596         pcr &= ~FMC2_PCR_PWID_MASK;
 597
 598         /* ECC logic is disabled */
 599         pcr &= ~FMC2_PCR_ECCEN;
 600
 601         /* Default mode */
 602         pcr &= ~FMC2_PCR_ECCALG;
 603         pcr &= ~FMC2_PCR_BCHECC;
 604         pcr &= ~FMC2_PCR_WEN;
 605
 606         /* Set default ECC sector size */
 607         pcr &= ~FMC2_PCR_ECCSS_MASK;
 608         pcr |= FMC2_PCR_ECCSS(FMC2_PCR_ECCSS_2048);
 609
 610         /* Set default tclr/tar timings */
 611         pcr &= ~FMC2_PCR_TCLR_MASK;
 612         pcr |= FMC2_PCR_TCLR(FMC2_PCR_TCLR_DEFAULT);
 613         pcr &= ~FMC2_PCR_TAR_MASK;
 614         pcr |= FMC2_PCR_TAR(FMC2_PCR_TAR_DEFAULT);
 615
 616         /* Enable FMC2 controller */
 617         bcr1 |= FMC2_BCR1_FMC2EN;
 618
 619         writel(bcr1, fmc2->io_base + FMC2_BCR1);
 620         writel(pcr, fmc2->io_base + FMC2_PCR);
 621         writel(FMC2_PMEM_DEFAULT, fmc2->io_base + FMC2_PMEM);
 622         writel(FMC2_PATT_DEFAULT, fmc2->io_base + FMC2_PATT);
 623 }
 624
 625 /* Controller timings */
 626 static void stm32_fmc2_calc_timings(struct nand_chip *chip,
 627                                     const struct nand_sdr_timings *sdrt)
 628 {
 629         struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
 630         struct stm32_fmc2_nand *nand = to_fmc2_nand(chip);
 631         struct stm32_fmc2_timings *tims = &nand->timings;
 632         unsigned long hclk = clk_get_rate(&fmc2->clk);
 633         unsigned long hclkp = FMC2_NSEC_PER_SEC / (hclk / 1000);
 634         unsigned long timing, tar, tclr, thiz, twait;
 635         unsigned long tset_mem, tset_att, thold_mem, thold_att;
 636
 637         tar = max_t(unsigned long, hclkp, sdrt->tAR_min);
 638         timing = DIV_ROUND_UP(tar, hclkp) - 1;
 639         tims->tar = min_t(unsigned long, timing, FMC2_PCR_TIMING_MASK);
 640
 641         tclr = max_t(unsigned long, hclkp, sdrt->tCLR_min);
 642         timing = DIV_ROUND_UP(tclr, hclkp) - 1;
 643         tims->tclr = min_t(unsigned long, timing, FMC2_PCR_TIMING_MASK);
 644
 645         tims->thiz = FMC2_THIZ;
 646         thiz = (tims->thiz + 1) * hclkp;
 647
 648         /*
 649          * tWAIT > tRP
 650          * tWAIT > tWP
 651          * tWAIT > tREA + tIO
 652          */
 653         twait = max_t(unsigned long, hclkp, sdrt->tRP_min);
 654         twait = max_t(unsigned long, twait, sdrt->tWP_min);
 655         twait = max_t(unsigned long, twait, sdrt->tREA_max + FMC2_TIO);
 656         timing = DIV_ROUND_UP(twait, hclkp);
 657         tims->twait = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK);
 658
 659         /*
 660          * tSETUP_MEM > tCS - tWAIT
 661          * tSETUP_MEM > tALS - tWAIT
 662          * tSETUP_MEM > tDS - (tWAIT - tHIZ)
 663          */
 664         tset_mem = hclkp;
 665         if (sdrt->tCS_min > twait && (tset_mem < sdrt->tCS_min - twait))
 666                 tset_mem = sdrt->tCS_min - twait;
 667         if (sdrt->tALS_min > twait && (tset_mem < sdrt->tALS_min - twait))
 668                 tset_mem = sdrt->tALS_min - twait;
 669         if (twait > thiz && (sdrt->tDS_min > twait - thiz) &&
 670             (tset_mem < sdrt->tDS_min - (twait - thiz)))
 671                 tset_mem = sdrt->tDS_min - (twait - thiz);
 672         timing = DIV_ROUND_UP(tset_mem, hclkp);
 673         tims->tset_mem = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK);
 674
 675         /*
 676          * tHOLD_MEM > tCH
 677          * tHOLD_MEM > tREH - tSETUP_MEM
 678          * tHOLD_MEM > max(tRC, tWC) - (tSETUP_MEM + tWAIT)
 679          */
 680         thold_mem = max_t(unsigned long, hclkp, sdrt->tCH_min);
 681         if (sdrt->tREH_min > tset_mem &&
 682             (thold_mem < sdrt->tREH_min - tset_mem))
 683                 thold_mem = sdrt->tREH_min - tset_mem;
 684         if ((sdrt->tRC_min > tset_mem + twait) &&
 685             (thold_mem < sdrt->tRC_min - (tset_mem + twait)))
 686                 thold_mem = sdrt->tRC_min - (tset_mem + twait);
 687         if ((sdrt->tWC_min > tset_mem + twait) &&
 688             (thold_mem < sdrt->tWC_min - (tset_mem + twait)))
 689                 thold_mem = sdrt->tWC_min - (tset_mem + twait);
 690         timing = DIV_ROUND_UP(thold_mem, hclkp);
 691         tims->thold_mem = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK);
 692
 693         /*
 694          * tSETUP_ATT > tCS - tWAIT
 695          * tSETUP_ATT > tCLS - tWAIT
 696          * tSETUP_ATT > tALS - tWAIT
 697          * tSETUP_ATT > tRHW - tHOLD_MEM
 698          * tSETUP_ATT > tDS - (tWAIT - tHIZ)
 699          */
 700         tset_att = hclkp;
 701         if (sdrt->tCS_min > twait && (tset_att < sdrt->tCS_min - twait))
 702                 tset_att = sdrt->tCS_min - twait;
 703         if (sdrt->tCLS_min > twait && (tset_att < sdrt->tCLS_min - twait))
 704                 tset_att = sdrt->tCLS_min - twait;
 705         if (sdrt->tALS_min > twait && (tset_att < sdrt->tALS_min - twait))
 706                 tset_att = sdrt->tALS_min - twait;
 707         if (sdrt->tRHW_min > thold_mem &&
 708             (tset_att < sdrt->tRHW_min - thold_mem))
 709                 tset_att = sdrt->tRHW_min - thold_mem;
 710         if (twait > thiz && (sdrt->tDS_min > twait - thiz) &&
 711             (tset_att < sdrt->tDS_min - (twait - thiz)))
 712                 tset_att = sdrt->tDS_min - (twait - thiz);
 713         timing = DIV_ROUND_UP(tset_att, hclkp);
 714         tims->tset_att = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK);
 715
 716         /*
 717          * tHOLD_ATT > tALH
 718          * tHOLD_ATT > tCH
 719          * tHOLD_ATT > tCLH
 720          * tHOLD_ATT > tCOH
 721          * tHOLD_ATT > tDH
 722          * tHOLD_ATT > tWB + tIO + tSYNC - tSETUP_MEM
 723          * tHOLD_ATT > tADL - tSETUP_MEM
 724          * tHOLD_ATT > tWH - tSETUP_MEM
 725          * tHOLD_ATT > tWHR - tSETUP_MEM
 726          * tHOLD_ATT > tRC - (tSETUP_ATT + tWAIT)
 727          * tHOLD_ATT > tWC - (tSETUP_ATT + tWAIT)
 728          */
 729         thold_att = max_t(unsigned long, hclkp, sdrt->tALH_min);
 730         thold_att = max_t(unsigned long, thold_att, sdrt->tCH_min);
 731         thold_att = max_t(unsigned long, thold_att, sdrt->tCLH_min);
 732         thold_att = max_t(unsigned long, thold_att, sdrt->tCOH_min);
 733         thold_att = max_t(unsigned long, thold_att, sdrt->tDH_min);
 734         if ((sdrt->tWB_max + FMC2_TIO + FMC2_TSYNC > tset_mem) &&
 735             (thold_att < sdrt->tWB_max + FMC2_TIO + FMC2_TSYNC - tset_mem))
 736                 thold_att = sdrt->tWB_max + FMC2_TIO + FMC2_TSYNC - tset_mem;
 737         if (sdrt->tADL_min > tset_mem &&
 738             (thold_att < sdrt->tADL_min - tset_mem))
 739                 thold_att = sdrt->tADL_min - tset_mem;
 740         if (sdrt->tWH_min > tset_mem &&
 741             (thold_att < sdrt->tWH_min - tset_mem))
 742                 thold_att = sdrt->tWH_min - tset_mem;
 743         if (sdrt->tWHR_min > tset_mem &&
 744             (thold_att < sdrt->tWHR_min - tset_mem))
 745                 thold_att = sdrt->tWHR_min - tset_mem;
 746         if ((sdrt->tRC_min > tset_att + twait) &&
 747             (thold_att < sdrt->tRC_min - (tset_att + twait)))
 748                 thold_att = sdrt->tRC_min - (tset_att + twait);
 749         if ((sdrt->tWC_min > tset_att + twait) &&
 750             (thold_att < sdrt->tWC_min - (tset_att + twait)))
 751                 thold_att = sdrt->tWC_min - (tset_att + twait);
 752         timing = DIV_ROUND_UP(thold_att, hclkp);
 753         tims->thold_att = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK);
 754 }
 755
 756 static int stm32_fmc2_setup_interface(struct mtd_info *mtd, int chipnr,
 757                                       const struct nand_data_interface *conf)
 758 {
 759         struct nand_chip *chip = mtd_to_nand(mtd);
 760         const struct nand_sdr_timings *sdrt;
 761
 762         sdrt = nand_get_sdr_timings(conf);
 763         if (IS_ERR(sdrt))
 764                 return PTR_ERR(sdrt);
 765
 766         if (chipnr == NAND_DATA_IFACE_CHECK_ONLY)
 767                 return 0;
 768
 769         stm32_fmc2_calc_timings(chip, sdrt);
 770
 771         /* Apply timings */
 772         stm32_fmc2_timings_init(chip);
 773
 774         return 0;
 775 }
 776
 777 /* NAND callbacks setup */
 778 static void stm32_fmc2_nand_callbacks_setup(struct nand_chip *chip)
 779 {
 780         chip->ecc.hwctl = stm32_fmc2_hwctl;
 781
 782         /*
 783          * Specific callbacks to read/write a page depending on
 784          * the algo used (Hamming, BCH).
 785          */
 786         if (chip->ecc.strength == FMC2_ECC_HAM) {
 787                 /* Hamming is used */
 788                 chip->ecc.calculate = stm32_fmc2_ham_calculate;
 789                 chip->ecc.correct = stm32_fmc2_ham_correct;
 790                 chip->ecc.bytes = chip->options & NAND_BUSWIDTH_16 ? 4 : 3;
 791                 chip->ecc.options |= NAND_ECC_GENERIC_ERASED_CHECK;
 792                 return;
 793         }
 794
 795         /* BCH is used */
 796         chip->ecc.read_page = stm32_fmc2_read_page;
 797         chip->ecc.calculate = stm32_fmc2_bch_calculate;
 798         chip->ecc.correct = stm32_fmc2_bch_correct;
 799
 800         if (chip->ecc.strength == FMC2_ECC_BCH8)
 801                 chip->ecc.bytes = chip->options & NAND_BUSWIDTH_16 ? 14 : 13;
 802         else
 803                 chip->ecc.bytes = chip->options & NAND_BUSWIDTH_16 ? 8 : 7;
 804 }
 805
 806 /* FMC2 caps */
 807 static int stm32_fmc2_calc_ecc_bytes(int step_size, int strength)
 808 {
 809         /* Hamming */
 810         if (strength == FMC2_ECC_HAM)
 811                 return 4;
 812
 813         /* BCH8 */
 814         if (strength == FMC2_ECC_BCH8)
 815                 return 14;
 816
 817         /* BCH4 */
 818         return 8;
 819 }
 820
 821 NAND_ECC_CAPS_SINGLE(stm32_fmc2_ecc_caps, stm32_fmc2_calc_ecc_bytes,
 822                      FMC2_ECC_STEP_SIZE,
 823                      FMC2_ECC_HAM, FMC2_ECC_BCH4, FMC2_ECC_BCH8);
 824
 825 /* FMC2 probe */
 826 static int stm32_fmc2_parse_child(struct stm32_fmc2_nfc *fmc2,
 827                                   ofnode node)
 828 {
 829         struct stm32_fmc2_nand *nand = &fmc2->nand;
 830         u32 cs[FMC2_MAX_CE];
 831         int ret, i;
 832
 833         if (!ofnode_get_property(node, "reg", &nand->ncs))
 834                 return -EINVAL;
 835
 836         nand->ncs /= sizeof(u32);
 837         if (!nand->ncs) {
 838                 pr_err("Invalid reg property size\n");
 839                 return -EINVAL;
 840         }
 841
 842         ret = ofnode_read_u32_array(node, "reg", cs, nand->ncs);
 843         if (ret < 0) {
 844                 pr_err("Could not retrieve reg property\n");
 845                 return -EINVAL;
 846         }
 847
 848         for (i = 0; i < nand->ncs; i++) {
 849                 if (cs[i] > FMC2_MAX_CE) {
 850                         pr_err("Invalid reg value: %d\n",
 851                                nand->cs_used[i]);
 852                         return -EINVAL;
 853                 }
 854
 855                 if (fmc2->cs_assigned & BIT(cs[i])) {
 856                         pr_err("Cs already assigned: %d\n",
 857                                nand->cs_used[i]);
 858                         return -EINVAL;
 859                 }
 860
 861                 fmc2->cs_assigned |= BIT(cs[i]);
 862                 nand->cs_used[i] = cs[i];
 863         }
 864
 865         nand->chip.flash_node = ofnode_to_offset(node);
 866
 867         return 0;
 868 }
 869
 870 static int stm32_fmc2_parse_dt(struct udevice *dev,
 871                                struct stm32_fmc2_nfc *fmc2)
 872 {
 873         ofnode child;
 874         int ret, nchips = 0;
 875
 876         dev_for_each_subnode(child, dev)
 877                 nchips++;
 878
 879         if (!nchips) {
 880                 pr_err("NAND chip not defined\n");
 881                 return -EINVAL;
 882         }
 883
 884         if (nchips > 1) {
 885                 pr_err("Too many NAND chips defined\n");
 886                 return -EINVAL;
 887         }
 888
 889         dev_for_each_subnode(child, dev) {
 890                 ret = stm32_fmc2_parse_child(fmc2, child);
 891                 if (ret)
 892                         return ret;
 893         }
 894
 895         return 0;
 896 }
 897
 898 static int stm32_fmc2_probe(struct udevice *dev)
 899 {
 900         struct stm32_fmc2_nfc *fmc2 = dev_get_priv(dev);
 901         struct stm32_fmc2_nand *nand = &fmc2->nand;
 902         struct nand_chip *chip = &nand->chip;
 903         struct mtd_info *mtd = &chip->mtd;
 904         struct nand_ecclayout *ecclayout;
 905         struct resource resource;
 906         struct reset_ctl reset;
 907         int oob_index, chip_cs, mem_region, ret;
 908         unsigned int i;
 909
 910         spin_lock_init(&fmc2->controller.lock);
 911         init_waitqueue_head(&fmc2->controller.wq);
 912
 913         ret = stm32_fmc2_parse_dt(dev, fmc2);
 914         if (ret)
 915                 return ret;
 916
 917         /* Get resources */
 918         ret = dev_read_resource(dev, 0, &resource);
 919         if (ret) {
 920                 pr_err("Resource io_base not found");
 921                 return ret;
 922         }
 923         fmc2->io_base = (void __iomem *)resource.start;
 924
 925         for (chip_cs = 0, mem_region = 1; chip_cs < FMC2_MAX_CE;
 926              chip_cs++, mem_region += 3) {
 927                 if (!(fmc2->cs_assigned & BIT(chip_cs)))
 928                         continue;
 929
 930                 ret = dev_read_resource(dev, mem_region, &resource);
 931                 if (ret) {
 932                         pr_err("Resource data_base not found for cs%d",
 933                                chip_cs);
 934                         return ret;
 935                 }
 936                 fmc2->data_base[chip_cs] = (void __iomem *)resource.start;
 937
 938                 ret = dev_read_resource(dev, mem_region + 1, &resource);
 939                 if (ret) {
 940                         pr_err("Resource cmd_base not found for cs%d",
 941                                chip_cs);
 942                         return ret;
 943                 }
 944                 fmc2->cmd_base[chip_cs] = (void __iomem *)resource.start;
 945
 946                 ret = dev_read_resource(dev, mem_region + 2, &resource);
 947                 if (ret) {
 948                         pr_err("Resource addr_base not found for cs%d",
 949                                chip_cs);
 950                         return ret;
 951                 }
 952                 fmc2->addr_base[chip_cs] = (void __iomem *)resource.start;
 953         }
 954
 955         /* Enable the clock */
 956         ret = clk_get_by_index(dev, 0, &fmc2->clk);
 957         if (ret)
 958                 return ret;
 959
 960         ret = clk_enable(&fmc2->clk);
 961         if (ret)
 962                 return ret;
 963
 964         /* Reset */
 965         ret = reset_get_by_index(dev, 0, &reset);
 966         if (!ret) {
 967                 reset_assert(&reset);
 968                 udelay(2);
 969                 reset_deassert(&reset);
 970         }
 971
 972         /* FMC2 init routine */
 973         stm32_fmc2_init(fmc2);
 974
 975         chip->controller = &fmc2->base;
 976         chip->select_chip = stm32_fmc2_select_chip;
 977         chip->setup_data_interface = stm32_fmc2_setup_interface;
 978         chip->cmd_ctrl = stm32_fmc2_cmd_ctrl;
 979         chip->chip_delay = FMC2_RB_DELAY_US;
 980         chip->options |= NAND_BUSWIDTH_AUTO | NAND_NO_SUBPAGE_WRITE |
 981                          NAND_USE_BOUNCE_BUFFER;
 982
 983         /* Default ECC settings */
 984         chip->ecc.mode = NAND_ECC_HW;
 985         chip->ecc.size = FMC2_ECC_STEP_SIZE;
 986         chip->ecc.strength = FMC2_ECC_BCH8;
 987
 988         /* Scan to find existence of the device */
 989         ret = nand_scan_ident(mtd, nand->ncs, NULL);
 990         if (ret)
 991                 return ret;
 992
 993         /*
 994          * Only NAND_ECC_HW mode is actually supported
 995          * Hamming => ecc.strength = 1
 996          * BCH4 => ecc.strength = 4
 997          * BCH8 => ecc.strength = 8
 998          * ECC sector size = 512
 999          */
1000         if (chip->ecc.mode != NAND_ECC_HW) {
1001                 pr_err("Nand_ecc_mode is not well defined in the DT\n");
1002                 return -EINVAL;
1003         }
1004
1005         ret = nand_check_ecc_caps(chip, &stm32_fmc2_ecc_caps,
1006                                   mtd->oobsize - FMC2_BBM_LEN);
1007         if (ret) {
1008                 pr_err("No valid ECC settings set\n");
1009                 return ret;
1010         }
1011
1012         if (chip->bbt_options & NAND_BBT_USE_FLASH)
1013                 chip->bbt_options |= NAND_BBT_NO_OOB;
1014
1015         /* NAND callbacks setup */
1016         stm32_fmc2_nand_callbacks_setup(chip);
1017
1018         /* Define ECC layout */
1019         ecclayout = &fmc2->ecclayout;
1020         ecclayout->eccbytes = chip->ecc.bytes *
1021                               (mtd->writesize / chip->ecc.size);
1022         oob_index = FMC2_BBM_LEN;
1023         for (i = 0; i < ecclayout->eccbytes; i++, oob_index++)
1024                 ecclayout->eccpos[i] = oob_index;
1025         ecclayout->oobfree->offset = oob_index;
1026         ecclayout->oobfree->length = mtd->oobsize - ecclayout->oobfree->offset;
1027         chip->ecc.layout = ecclayout;
1028
1029         /* Configure bus width to 16-bit */
1030         if (chip->options & NAND_BUSWIDTH_16)
1031                 stm32_fmc2_set_buswidth_16(fmc2, true);
1032
1033         /* Scan the device to fill MTD data-structures */
1034         ret = nand_scan_tail(mtd);
1035         if (ret)
1036                 return ret;
1037
1038         return nand_register(0, mtd);
1039 }
1040
1041 static const struct udevice_id stm32_fmc2_match[] = {
1042         { .compatible = "st,stm32mp15-fmc2" },
1043         { /* Sentinel */ }
1044 };
1045
1046 U_BOOT_DRIVER(stm32_fmc2_nand) = {
1047         .name = "stm32_fmc2_nand",
1048         .id = UCLASS_MTD,
1049         .of_match = stm32_fmc2_match,
1050         .probe = stm32_fmc2_probe,
1051         .priv_auto_alloc_size = sizeof(struct stm32_fmc2_nfc),
1052 };
1053
1054 void board_nand_init(void)
1055 {
1056         struct udevice *dev;
1057         int ret;
1058
1059         ret = uclass_get_device_by_driver(UCLASS_MTD,
1060                                           DM_GET_DRIVER(stm32_fmc2_nand),
1061                                           &dev);
1062         if (ret && ret != -ENODEV)
1063                 pr_err("Failed to initialize STM32 FMC2 NAND controller. (error %d)\n",
1064                        ret);
1065 }