1 // SPDX-License-Identifier: GPL-2.0
3 * drivers/mtd/nand/raw/pxa3xx_nand.c
5 * Copyright © 2005 Intel Corporation
6 * Copyright © 2006 Marvell International Ltd.
13 #include <linux/errno.h>
15 #include <asm/arch/cpu.h>
16 #include <linux/mtd/mtd.h>
17 #include <linux/mtd/rawnand.h>
18 #include <linux/types.h>
20 #include "pxa3xx_nand.h"
22 DECLARE_GLOBAL_DATA_PTR;
24 #define TIMEOUT_DRAIN_FIFO 5 /* in ms */
25 #define CHIP_DELAY_TIMEOUT 200
26 #define NAND_STOP_DELAY 40
29 * Define a buffer size for the initial command that detects the flash device:
30 * STATUS, READID and PARAM.
31 * ONFI param page is 256 bytes, and there are three redundant copies
32 * to be read. JEDEC param page is 512 bytes, and there are also three
33 * redundant copies to be read.
34 * Hence this buffer should be at least 512 x 3. Let's pick 2048.
36 #define INIT_BUFFER_SIZE 2048
38 /* registers and bit definitions */
39 #define NDCR (0x00) /* Control register */
40 #define NDTR0CS0 (0x04) /* Timing Parameter 0 for CS0 */
41 #define NDTR1CS0 (0x0C) /* Timing Parameter 1 for CS0 */
42 #define NDSR (0x14) /* Status Register */
43 #define NDPCR (0x18) /* Page Count Register */
44 #define NDBDR0 (0x1C) /* Bad Block Register 0 */
45 #define NDBDR1 (0x20) /* Bad Block Register 1 */
46 #define NDECCCTRL (0x28) /* ECC control */
47 #define NDDB (0x40) /* Data Buffer */
48 #define NDCB0 (0x48) /* Command Buffer0 */
49 #define NDCB1 (0x4C) /* Command Buffer1 */
50 #define NDCB2 (0x50) /* Command Buffer2 */
52 #define NDCR_SPARE_EN (0x1 << 31)
53 #define NDCR_ECC_EN (0x1 << 30)
54 #define NDCR_DMA_EN (0x1 << 29)
55 #define NDCR_ND_RUN (0x1 << 28)
56 #define NDCR_DWIDTH_C (0x1 << 27)
57 #define NDCR_DWIDTH_M (0x1 << 26)
58 #define NDCR_PAGE_SZ (0x1 << 24)
59 #define NDCR_NCSX (0x1 << 23)
60 #define NDCR_ND_MODE (0x3 << 21)
61 #define NDCR_NAND_MODE (0x0)
62 #define NDCR_CLR_PG_CNT (0x1 << 20)
63 #define NFCV1_NDCR_ARB_CNTL (0x1 << 19)
64 #define NDCR_RD_ID_CNT_MASK (0x7 << 16)
65 #define NDCR_RD_ID_CNT(x) (((x) << 16) & NDCR_RD_ID_CNT_MASK)
67 #define NDCR_RA_START (0x1 << 15)
68 #define NDCR_PG_PER_BLK (0x1 << 14)
69 #define NDCR_ND_ARB_EN (0x1 << 12)
70 #define NDCR_INT_MASK (0xFFF)
72 #define NDSR_MASK (0xfff)
73 #define NDSR_ERR_CNT_OFF (16)
74 #define NDSR_ERR_CNT_MASK (0x1f)
75 #define NDSR_ERR_CNT(sr) ((sr >> NDSR_ERR_CNT_OFF) & NDSR_ERR_CNT_MASK)
76 #define NDSR_RDY (0x1 << 12)
77 #define NDSR_FLASH_RDY (0x1 << 11)
78 #define NDSR_CS0_PAGED (0x1 << 10)
79 #define NDSR_CS1_PAGED (0x1 << 9)
80 #define NDSR_CS0_CMDD (0x1 << 8)
81 #define NDSR_CS1_CMDD (0x1 << 7)
82 #define NDSR_CS0_BBD (0x1 << 6)
83 #define NDSR_CS1_BBD (0x1 << 5)
84 #define NDSR_UNCORERR (0x1 << 4)
85 #define NDSR_CORERR (0x1 << 3)
86 #define NDSR_WRDREQ (0x1 << 2)
87 #define NDSR_RDDREQ (0x1 << 1)
88 #define NDSR_WRCMDREQ (0x1)
90 #define NDCB0_LEN_OVRD (0x1 << 28)
91 #define NDCB0_ST_ROW_EN (0x1 << 26)
92 #define NDCB0_AUTO_RS (0x1 << 25)
93 #define NDCB0_CSEL (0x1 << 24)
94 #define NDCB0_EXT_CMD_TYPE_MASK (0x7 << 29)
95 #define NDCB0_EXT_CMD_TYPE(x) (((x) << 29) & NDCB0_EXT_CMD_TYPE_MASK)
96 #define NDCB0_CMD_TYPE_MASK (0x7 << 21)
97 #define NDCB0_CMD_TYPE(x) (((x) << 21) & NDCB0_CMD_TYPE_MASK)
98 #define NDCB0_NC (0x1 << 20)
99 #define NDCB0_DBC (0x1 << 19)
100 #define NDCB0_ADDR_CYC_MASK (0x7 << 16)
101 #define NDCB0_ADDR_CYC(x) (((x) << 16) & NDCB0_ADDR_CYC_MASK)
102 #define NDCB0_CMD2_MASK (0xff << 8)
103 #define NDCB0_CMD1_MASK (0xff)
104 #define NDCB0_ADDR_CYC_SHIFT (16)
106 #define EXT_CMD_TYPE_DISPATCH 6 /* Command dispatch */
107 #define EXT_CMD_TYPE_NAKED_RW 5 /* Naked read or Naked write */
108 #define EXT_CMD_TYPE_READ 4 /* Read */
109 #define EXT_CMD_TYPE_DISP_WR 4 /* Command dispatch with write */
110 #define EXT_CMD_TYPE_FINAL 3 /* Final command */
111 #define EXT_CMD_TYPE_LAST_RW 1 /* Last naked read/write */
112 #define EXT_CMD_TYPE_MONO 0 /* Monolithic read/write */
115 * This should be large enough to read 'ONFI' and 'JEDEC'.
116 * Let's use 7 bytes, which is the maximum ID count supported
117 * by the controller (see NDCR_RD_ID_CNT_MASK).
119 #define READ_ID_BYTES 7
121 /* macros for registers read/write */
122 #define nand_writel(info, off, val) \
123 writel((val), (info)->mmio_base + (off))
125 #define nand_readl(info, off) \
126 readl((info)->mmio_base + (off))
128 /* error code and state */
151 enum pxa3xx_nand_variant {
152 PXA3XX_NAND_VARIANT_PXA,
153 PXA3XX_NAND_VARIANT_ARMADA370,
156 struct pxa3xx_nand_host {
157 struct nand_chip chip;
160 /* page size of attached chip */
164 /* calculated from pxa3xx_nand_flash data */
165 unsigned int col_addr_cycles;
166 unsigned int row_addr_cycles;
169 struct pxa3xx_nand_info {
170 struct nand_hw_control controller;
171 struct pxa3xx_nand_platform_data *pdata;
174 void __iomem *mmio_base;
175 unsigned long mmio_phys;
176 int cmd_complete, dev_ready;
178 unsigned int buf_start;
179 unsigned int buf_count;
180 unsigned int buf_size;
181 unsigned int data_buff_pos;
182 unsigned int oob_buff_pos;
184 unsigned char *data_buff;
185 unsigned char *oob_buff;
187 struct pxa3xx_nand_host *host[NUM_CHIP_SELECT];
191 * This driver supports NFCv1 (as found in PXA SoC)
192 * and NFCv2 (as found in Armada 370/XP SoC).
194 enum pxa3xx_nand_variant variant;
197 int use_ecc; /* use HW ECC ? */
198 int ecc_bch; /* using BCH ECC? */
199 int use_spare; /* use spare ? */
202 /* Amount of real data per full chunk */
203 unsigned int chunk_size;
205 /* Amount of spare data per full chunk */
206 unsigned int spare_size;
208 /* Number of full chunks (i.e chunk_size + spare_size) */
209 unsigned int nfullchunks;
212 * Total number of chunks. If equal to nfullchunks, then there
213 * are only full chunks. Otherwise, there is one last chunk of
214 * size (last_chunk_size + last_spare_size)
216 unsigned int ntotalchunks;
218 /* Amount of real data in the last chunk */
219 unsigned int last_chunk_size;
221 /* Amount of spare data in the last chunk */
222 unsigned int last_spare_size;
224 unsigned int ecc_size;
225 unsigned int ecc_err_cnt;
226 unsigned int max_bitflips;
230 * Variables only valid during command
231 * execution. step_chunk_size and step_spare_size is the
232 * amount of real data and spare data in the current
233 * chunk. cur_chunk is the current chunk being
236 unsigned int step_chunk_size;
237 unsigned int step_spare_size;
238 unsigned int cur_chunk;
240 /* cached register value */
245 /* generated NDCBx register values */
252 static struct pxa3xx_nand_timing timing[] = {
254 * tCH Enable signal hold time
255 * tCS Enable signal setup time
256 * tWH ND_nWE high duration
257 * tWP ND_nWE pulse time
258 * tRH ND_nRE high duration
259 * tRP ND_nRE pulse width
260 * tR ND_nWE high to ND_nRE low for read
261 * tWHR ND_nWE high to ND_nRE low for status read
262 * tAR ND_ALE low to ND_nRE low delay
264 /*ch cs wh wp rh rp r whr ar */
265 { 40, 80, 60, 100, 80, 100, 90000, 400, 40, },
266 { 10, 0, 20, 40, 30, 40, 11123, 110, 10, },
267 { 10, 25, 15, 25, 15, 30, 25000, 60, 10, },
268 { 10, 35, 15, 25, 15, 25, 25000, 60, 10, },
269 { 5, 20, 10, 12, 10, 12, 25000, 60, 10, },
272 static struct pxa3xx_nand_flash builtin_flash_types[] = {
275 * flash_width Width of Flash memory (DWIDTH_M)
276 * dfc_width Width of flash controller(DWIDTH_C)
278 * http://www.linux-mtd.infradead.org/nand-data/nanddata.html
280 { 0x46ec, 16, 16, &timing[1] },
281 { 0xdaec, 8, 8, &timing[1] },
282 { 0xd7ec, 8, 8, &timing[1] },
283 { 0xa12c, 8, 8, &timing[2] },
284 { 0xb12c, 16, 16, &timing[2] },
285 { 0xdc2c, 8, 8, &timing[2] },
286 { 0xcc2c, 16, 16, &timing[2] },
287 { 0xba20, 16, 16, &timing[3] },
288 { 0xda98, 8, 8, &timing[4] },
291 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
292 static u8 bbt_pattern[] = {'M', 'V', 'B', 'b', 't', '0' };
293 static u8 bbt_mirror_pattern[] = {'1', 't', 'b', 'B', 'V', 'M' };
295 static struct nand_bbt_descr bbt_main_descr = {
296 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
297 | NAND_BBT_2BIT | NAND_BBT_VERSION,
301 .maxblocks = 8, /* Last 8 blocks in each chip */
302 .pattern = bbt_pattern
305 static struct nand_bbt_descr bbt_mirror_descr = {
306 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
307 | NAND_BBT_2BIT | NAND_BBT_VERSION,
311 .maxblocks = 8, /* Last 8 blocks in each chip */
312 .pattern = bbt_mirror_pattern
316 static struct nand_ecclayout ecc_layout_2KB_bch4bit = {
319 32, 33, 34, 35, 36, 37, 38, 39,
320 40, 41, 42, 43, 44, 45, 46, 47,
321 48, 49, 50, 51, 52, 53, 54, 55,
322 56, 57, 58, 59, 60, 61, 62, 63},
323 .oobfree = { {2, 30} }
326 static struct nand_ecclayout ecc_layout_2KB_bch8bit = {
329 64, 65, 66, 67, 68, 69, 70, 71,
330 72, 73, 74, 75, 76, 77, 78, 79,
331 80, 81, 82, 83, 84, 85, 86, 87,
332 88, 89, 90, 91, 92, 93, 94, 95,
333 96, 97, 98, 99, 100, 101, 102, 103,
334 104, 105, 106, 107, 108, 109, 110, 111,
335 112, 113, 114, 115, 116, 117, 118, 119,
336 120, 121, 122, 123, 124, 125, 126, 127},
337 .oobfree = { {1, 4}, {6, 26} }
340 static struct nand_ecclayout ecc_layout_4KB_bch4bit = {
343 32, 33, 34, 35, 36, 37, 38, 39,
344 40, 41, 42, 43, 44, 45, 46, 47,
345 48, 49, 50, 51, 52, 53, 54, 55,
346 56, 57, 58, 59, 60, 61, 62, 63,
347 96, 97, 98, 99, 100, 101, 102, 103,
348 104, 105, 106, 107, 108, 109, 110, 111,
349 112, 113, 114, 115, 116, 117, 118, 119,
350 120, 121, 122, 123, 124, 125, 126, 127},
351 /* Bootrom looks in bytes 0 & 5 for bad blocks */
352 .oobfree = { {6, 26}, { 64, 32} }
355 static struct nand_ecclayout ecc_layout_8KB_bch4bit = {
358 32, 33, 34, 35, 36, 37, 38, 39,
359 40, 41, 42, 43, 44, 45, 46, 47,
360 48, 49, 50, 51, 52, 53, 54, 55,
361 56, 57, 58, 59, 60, 61, 62, 63,
363 96, 97, 98, 99, 100, 101, 102, 103,
364 104, 105, 106, 107, 108, 109, 110, 111,
365 112, 113, 114, 115, 116, 117, 118, 119,
366 120, 121, 122, 123, 124, 125, 126, 127,
368 160, 161, 162, 163, 164, 165, 166, 167,
369 168, 169, 170, 171, 172, 173, 174, 175,
370 176, 177, 178, 179, 180, 181, 182, 183,
371 184, 185, 186, 187, 188, 189, 190, 191,
373 224, 225, 226, 227, 228, 229, 230, 231,
374 232, 233, 234, 235, 236, 237, 238, 239,
375 240, 241, 242, 243, 244, 245, 246, 247,
376 248, 249, 250, 251, 252, 253, 254, 255},
378 /* Bootrom looks in bytes 0 & 5 for bad blocks */
379 .oobfree = { {1, 4}, {6, 26}, { 64, 32}, {128, 32}, {192, 32} }
382 static struct nand_ecclayout ecc_layout_4KB_bch8bit = {
385 32, 33, 34, 35, 36, 37, 38, 39,
386 40, 41, 42, 43, 44, 45, 46, 47,
387 48, 49, 50, 51, 52, 53, 54, 55,
388 56, 57, 58, 59, 60, 61, 62, 63},
392 static struct nand_ecclayout ecc_layout_8KB_bch8bit = {
395 /* HW ECC handles all ECC data and all spare area is free for OOB */
396 .oobfree = {{0, 160} }
399 #define NDTR0_tCH(c) (min((c), 7) << 19)
400 #define NDTR0_tCS(c) (min((c), 7) << 16)
401 #define NDTR0_tWH(c) (min((c), 7) << 11)
402 #define NDTR0_tWP(c) (min((c), 7) << 8)
403 #define NDTR0_tRH(c) (min((c), 7) << 3)
404 #define NDTR0_tRP(c) (min((c), 7) << 0)
406 #define NDTR1_tR(c) (min((c), 65535) << 16)
407 #define NDTR1_tWHR(c) (min((c), 15) << 4)
408 #define NDTR1_tAR(c) (min((c), 15) << 0)
410 /* convert nano-seconds to nand flash controller clock cycles */
411 #define ns2cycle(ns, clk) (int)((ns) * (clk / 1000000) / 1000)
413 static enum pxa3xx_nand_variant pxa3xx_nand_get_variant(void)
415 /* We only support the Armada 370/XP/38x for now */
416 return PXA3XX_NAND_VARIANT_ARMADA370;
419 static void pxa3xx_nand_set_timing(struct pxa3xx_nand_host *host,
420 const struct pxa3xx_nand_timing *t)
422 struct pxa3xx_nand_info *info = host->info_data;
423 unsigned long nand_clk = mvebu_get_nand_clock();
424 uint32_t ndtr0, ndtr1;
426 ndtr0 = NDTR0_tCH(ns2cycle(t->tCH, nand_clk)) |
427 NDTR0_tCS(ns2cycle(t->tCS, nand_clk)) |
428 NDTR0_tWH(ns2cycle(t->tWH, nand_clk)) |
429 NDTR0_tWP(ns2cycle(t->tWP, nand_clk)) |
430 NDTR0_tRH(ns2cycle(t->tRH, nand_clk)) |
431 NDTR0_tRP(ns2cycle(t->tRP, nand_clk));
433 ndtr1 = NDTR1_tR(ns2cycle(t->tR, nand_clk)) |
434 NDTR1_tWHR(ns2cycle(t->tWHR, nand_clk)) |
435 NDTR1_tAR(ns2cycle(t->tAR, nand_clk));
437 info->ndtr0cs0 = ndtr0;
438 info->ndtr1cs0 = ndtr1;
439 nand_writel(info, NDTR0CS0, ndtr0);
440 nand_writel(info, NDTR1CS0, ndtr1);
443 static void pxa3xx_nand_set_sdr_timing(struct pxa3xx_nand_host *host,
444 const struct nand_sdr_timings *t)
446 struct pxa3xx_nand_info *info = host->info_data;
447 struct nand_chip *chip = &host->chip;
448 unsigned long nand_clk = mvebu_get_nand_clock();
449 uint32_t ndtr0, ndtr1;
451 u32 tCH_min = DIV_ROUND_UP(t->tCH_min, 1000);
452 u32 tCS_min = DIV_ROUND_UP(t->tCS_min, 1000);
453 u32 tWH_min = DIV_ROUND_UP(t->tWH_min, 1000);
454 u32 tWP_min = DIV_ROUND_UP(t->tWC_min - t->tWH_min, 1000);
455 u32 tREH_min = DIV_ROUND_UP(t->tREH_min, 1000);
456 u32 tRP_min = DIV_ROUND_UP(t->tRC_min - t->tREH_min, 1000);
457 u32 tR = chip->chip_delay * 1000;
458 u32 tWHR_min = DIV_ROUND_UP(t->tWHR_min, 1000);
459 u32 tAR_min = DIV_ROUND_UP(t->tAR_min, 1000);
461 /* fallback to a default value if tR = 0 */
465 ndtr0 = NDTR0_tCH(ns2cycle(tCH_min, nand_clk)) |
466 NDTR0_tCS(ns2cycle(tCS_min, nand_clk)) |
467 NDTR0_tWH(ns2cycle(tWH_min, nand_clk)) |
468 NDTR0_tWP(ns2cycle(tWP_min, nand_clk)) |
469 NDTR0_tRH(ns2cycle(tREH_min, nand_clk)) |
470 NDTR0_tRP(ns2cycle(tRP_min, nand_clk));
472 ndtr1 = NDTR1_tR(ns2cycle(tR, nand_clk)) |
473 NDTR1_tWHR(ns2cycle(tWHR_min, nand_clk)) |
474 NDTR1_tAR(ns2cycle(tAR_min, nand_clk));
476 info->ndtr0cs0 = ndtr0;
477 info->ndtr1cs0 = ndtr1;
478 nand_writel(info, NDTR0CS0, ndtr0);
479 nand_writel(info, NDTR1CS0, ndtr1);
482 static int pxa3xx_nand_init_timings(struct pxa3xx_nand_host *host)
484 const struct nand_sdr_timings *timings;
485 struct nand_chip *chip = &host->chip;
486 struct pxa3xx_nand_info *info = host->info_data;
487 const struct pxa3xx_nand_flash *f = NULL;
488 struct mtd_info *mtd = nand_to_mtd(&host->chip);
489 int mode, id, ntypes, i;
491 mode = onfi_get_async_timing_mode(chip);
492 if (mode == ONFI_TIMING_MODE_UNKNOWN) {
493 ntypes = ARRAY_SIZE(builtin_flash_types);
495 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
497 id = chip->read_byte(mtd);
498 id |= chip->read_byte(mtd) << 0x8;
500 for (i = 0; i < ntypes; i++) {
501 f = &builtin_flash_types[i];
503 if (f->chip_id == id)
508 dev_err(&info->pdev->dev, "Error: timings not found\n");
512 pxa3xx_nand_set_timing(host, f->timing);
514 if (f->flash_width == 16) {
515 info->reg_ndcr |= NDCR_DWIDTH_M;
516 chip->options |= NAND_BUSWIDTH_16;
519 info->reg_ndcr |= (f->dfc_width == 16) ? NDCR_DWIDTH_C : 0;
521 mode = fls(mode) - 1;
525 timings = onfi_async_timing_mode_to_sdr_timings(mode);
527 return PTR_ERR(timings);
529 pxa3xx_nand_set_sdr_timing(host, timings);
536 * NOTE: it is a must to set ND_RUN first, then write
537 * command buffer, otherwise, it does not work.
538 * We enable all the interrupt at the same time, and
539 * let pxa3xx_nand_irq to handle all logic.
541 static void pxa3xx_nand_start(struct pxa3xx_nand_info *info)
545 ndcr = info->reg_ndcr;
550 nand_writel(info, NDECCCTRL, 0x1);
552 ndcr &= ~NDCR_ECC_EN;
554 nand_writel(info, NDECCCTRL, 0x0);
557 ndcr &= ~NDCR_DMA_EN;
560 ndcr |= NDCR_SPARE_EN;
562 ndcr &= ~NDCR_SPARE_EN;
566 /* clear status bits and run */
567 nand_writel(info, NDSR, NDSR_MASK);
568 nand_writel(info, NDCR, 0);
569 nand_writel(info, NDCR, ndcr);
572 static void disable_int(struct pxa3xx_nand_info *info, uint32_t int_mask)
576 ndcr = nand_readl(info, NDCR);
577 nand_writel(info, NDCR, ndcr | int_mask);
580 static void drain_fifo(struct pxa3xx_nand_info *info, void *data, int len)
586 * According to the datasheet, when reading from NDDB
587 * with BCH enabled, after each 32 bytes reads, we
588 * have to make sure that the NDSR.RDDREQ bit is set.
590 * Drain the FIFO 8 32 bits reads at a time, and skip
591 * the polling on the last read.
594 readsl(info->mmio_base + NDDB, data, 8);
597 while (!(nand_readl(info, NDSR) & NDSR_RDDREQ)) {
598 if (get_timer(ts) > TIMEOUT_DRAIN_FIFO) {
599 dev_err(&info->pdev->dev,
600 "Timeout on RDDREQ while draining the FIFO\n");
610 readsl(info->mmio_base + NDDB, data, len);
613 static void handle_data_pio(struct pxa3xx_nand_info *info)
615 switch (info->state) {
616 case STATE_PIO_WRITING:
617 if (info->step_chunk_size)
618 writesl(info->mmio_base + NDDB,
619 info->data_buff + info->data_buff_pos,
620 DIV_ROUND_UP(info->step_chunk_size, 4));
622 if (info->step_spare_size)
623 writesl(info->mmio_base + NDDB,
624 info->oob_buff + info->oob_buff_pos,
625 DIV_ROUND_UP(info->step_spare_size, 4));
627 case STATE_PIO_READING:
628 if (info->step_chunk_size)
630 info->data_buff + info->data_buff_pos,
631 DIV_ROUND_UP(info->step_chunk_size, 4));
633 if (info->step_spare_size)
635 info->oob_buff + info->oob_buff_pos,
636 DIV_ROUND_UP(info->step_spare_size, 4));
639 dev_err(&info->pdev->dev, "%s: invalid state %d\n", __func__,
644 /* Update buffer pointers for multi-page read/write */
645 info->data_buff_pos += info->step_chunk_size;
646 info->oob_buff_pos += info->step_spare_size;
649 static void pxa3xx_nand_irq_thread(struct pxa3xx_nand_info *info)
651 handle_data_pio(info);
653 info->state = STATE_CMD_DONE;
654 nand_writel(info, NDSR, NDSR_WRDREQ | NDSR_RDDREQ);
657 static irqreturn_t pxa3xx_nand_irq(struct pxa3xx_nand_info *info)
659 unsigned int status, is_completed = 0, is_ready = 0;
660 unsigned int ready, cmd_done;
661 irqreturn_t ret = IRQ_HANDLED;
664 ready = NDSR_FLASH_RDY;
665 cmd_done = NDSR_CS0_CMDD;
668 cmd_done = NDSR_CS1_CMDD;
671 /* TODO - find out why we need the delay during write operation. */
674 status = nand_readl(info, NDSR);
676 if (status & NDSR_UNCORERR)
677 info->retcode = ERR_UNCORERR;
678 if (status & NDSR_CORERR) {
679 info->retcode = ERR_CORERR;
680 if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370 &&
682 info->ecc_err_cnt = NDSR_ERR_CNT(status);
684 info->ecc_err_cnt = 1;
687 * Each chunk composing a page is corrected independently,
688 * and we need to store maximum number of corrected bitflips
689 * to return it to the MTD layer in ecc.read_page().
691 info->max_bitflips = max_t(unsigned int,
695 if (status & (NDSR_RDDREQ | NDSR_WRDREQ)) {
696 info->state = (status & NDSR_RDDREQ) ?
697 STATE_PIO_READING : STATE_PIO_WRITING;
698 /* Call the IRQ thread in U-Boot directly */
699 pxa3xx_nand_irq_thread(info);
702 if (status & cmd_done) {
703 info->state = STATE_CMD_DONE;
706 if (status & ready) {
707 info->state = STATE_READY;
712 * Clear all status bit before issuing the next command, which
713 * can and will alter the status bits and will deserve a new
714 * interrupt on its own. This lets the controller exit the IRQ
716 nand_writel(info, NDSR, status);
718 if (status & NDSR_WRCMDREQ) {
719 status &= ~NDSR_WRCMDREQ;
720 info->state = STATE_CMD_HANDLE;
723 * Command buffer registers NDCB{0-2} (and optionally NDCB3)
724 * must be loaded by writing directly either 12 or 16
725 * bytes directly to NDCB0, four bytes at a time.
727 * Direct write access to NDCB1, NDCB2 and NDCB3 is ignored
728 * but each NDCBx register can be read.
730 nand_writel(info, NDCB0, info->ndcb0);
731 nand_writel(info, NDCB0, info->ndcb1);
732 nand_writel(info, NDCB0, info->ndcb2);
734 /* NDCB3 register is available in NFCv2 (Armada 370/XP SoC) */
735 if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370)
736 nand_writel(info, NDCB0, info->ndcb3);
740 info->cmd_complete = 1;
747 static inline int is_buf_blank(uint8_t *buf, size_t len)
749 for (; len > 0; len--)
755 static void set_command_address(struct pxa3xx_nand_info *info,
756 unsigned int page_size, uint16_t column, int page_addr)
758 /* small page addr setting */
759 if (page_size < info->chunk_size) {
760 info->ndcb1 = ((page_addr & 0xFFFFFF) << 8)
765 info->ndcb1 = ((page_addr & 0xFFFF) << 16)
768 if (page_addr & 0xFF0000)
769 info->ndcb2 = (page_addr & 0xFF0000) >> 16;
775 static void prepare_start_command(struct pxa3xx_nand_info *info, int command)
777 struct pxa3xx_nand_host *host = info->host[info->cs];
778 struct mtd_info *mtd = nand_to_mtd(&host->chip);
780 /* reset data and oob column point to handle data */
783 info->data_buff_pos = 0;
784 info->oob_buff_pos = 0;
785 info->step_chunk_size = 0;
786 info->step_spare_size = 0;
790 info->retcode = ERR_NONE;
791 info->ecc_err_cnt = 0;
797 case NAND_CMD_READOOB:
798 case NAND_CMD_PAGEPROG:
811 * If we are about to issue a read command, or about to set
812 * the write address, then clean the data buffer.
814 if (command == NAND_CMD_READ0 ||
815 command == NAND_CMD_READOOB ||
816 command == NAND_CMD_SEQIN) {
817 info->buf_count = mtd->writesize + mtd->oobsize;
818 memset(info->data_buff, 0xFF, info->buf_count);
822 static int prepare_set_command(struct pxa3xx_nand_info *info, int command,
823 int ext_cmd_type, uint16_t column, int page_addr)
825 int addr_cycle, exec_cmd;
826 struct pxa3xx_nand_host *host;
827 struct mtd_info *mtd;
829 host = info->host[info->cs];
830 mtd = nand_to_mtd(&host->chip);
835 info->ndcb0 = NDCB0_CSEL;
839 if (command == NAND_CMD_SEQIN)
842 addr_cycle = NDCB0_ADDR_CYC(host->row_addr_cycles
843 + host->col_addr_cycles);
846 case NAND_CMD_READOOB:
848 info->buf_start = column;
849 info->ndcb0 |= NDCB0_CMD_TYPE(0)
853 if (command == NAND_CMD_READOOB)
854 info->buf_start += mtd->writesize;
856 if (info->cur_chunk < info->nfullchunks) {
857 info->step_chunk_size = info->chunk_size;
858 info->step_spare_size = info->spare_size;
860 info->step_chunk_size = info->last_chunk_size;
861 info->step_spare_size = info->last_spare_size;
865 * Multiple page read needs an 'extended command type' field,
866 * which is either naked-read or last-read according to the
869 if (mtd->writesize == info->chunk_size) {
870 info->ndcb0 |= NDCB0_DBC | (NAND_CMD_READSTART << 8);
871 } else if (mtd->writesize > info->chunk_size) {
872 info->ndcb0 |= NDCB0_DBC | (NAND_CMD_READSTART << 8)
874 | NDCB0_EXT_CMD_TYPE(ext_cmd_type);
875 info->ndcb3 = info->step_chunk_size +
876 info->step_spare_size;
879 set_command_address(info, mtd->writesize, column, page_addr);
884 info->buf_start = column;
885 set_command_address(info, mtd->writesize, 0, page_addr);
888 * Multiple page programming needs to execute the initial
889 * SEQIN command that sets the page address.
891 if (mtd->writesize > info->chunk_size) {
892 info->ndcb0 |= NDCB0_CMD_TYPE(0x1)
893 | NDCB0_EXT_CMD_TYPE(ext_cmd_type)
900 case NAND_CMD_PAGEPROG:
901 if (is_buf_blank(info->data_buff,
902 (mtd->writesize + mtd->oobsize))) {
907 if (info->cur_chunk < info->nfullchunks) {
908 info->step_chunk_size = info->chunk_size;
909 info->step_spare_size = info->spare_size;
911 info->step_chunk_size = info->last_chunk_size;
912 info->step_spare_size = info->last_spare_size;
915 /* Second command setting for large pages */
916 if (mtd->writesize > info->chunk_size) {
918 * Multiple page write uses the 'extended command'
919 * field. This can be used to issue a command dispatch
920 * or a naked-write depending on the current stage.
922 info->ndcb0 |= NDCB0_CMD_TYPE(0x1)
924 | NDCB0_EXT_CMD_TYPE(ext_cmd_type);
925 info->ndcb3 = info->step_chunk_size +
926 info->step_spare_size;
929 * This is the command dispatch that completes a chunked
930 * page program operation.
932 if (info->cur_chunk == info->ntotalchunks) {
933 info->ndcb0 = NDCB0_CMD_TYPE(0x1)
934 | NDCB0_EXT_CMD_TYPE(ext_cmd_type)
941 info->ndcb0 |= NDCB0_CMD_TYPE(0x1)
945 | (NAND_CMD_PAGEPROG << 8)
952 info->buf_count = INIT_BUFFER_SIZE;
953 info->ndcb0 |= NDCB0_CMD_TYPE(0)
957 info->ndcb1 = (column & 0xFF);
958 info->ndcb3 = INIT_BUFFER_SIZE;
959 info->step_chunk_size = INIT_BUFFER_SIZE;
962 case NAND_CMD_READID:
963 info->buf_count = READ_ID_BYTES;
964 info->ndcb0 |= NDCB0_CMD_TYPE(3)
967 info->ndcb1 = (column & 0xFF);
969 info->step_chunk_size = 8;
971 case NAND_CMD_STATUS:
973 info->ndcb0 |= NDCB0_CMD_TYPE(4)
977 info->step_chunk_size = 8;
980 case NAND_CMD_ERASE1:
981 info->ndcb0 |= NDCB0_CMD_TYPE(2)
985 | (NAND_CMD_ERASE2 << 8)
987 info->ndcb1 = page_addr;
992 info->ndcb0 |= NDCB0_CMD_TYPE(5)
997 case NAND_CMD_ERASE2:
1003 dev_err(&info->pdev->dev, "non-supported command %x\n",
1011 static void nand_cmdfunc(struct mtd_info *mtd, unsigned command,
1012 int column, int page_addr)
1014 struct nand_chip *chip = mtd_to_nand(mtd);
1015 struct pxa3xx_nand_host *host = nand_get_controller_data(chip);
1016 struct pxa3xx_nand_info *info = host->info_data;
1020 * if this is a x16 device ,then convert the input
1021 * "byte" address into a "word" address appropriate
1022 * for indexing a word-oriented device
1024 if (info->reg_ndcr & NDCR_DWIDTH_M)
1028 * There may be different NAND chip hooked to
1029 * different chip select, so check whether
1030 * chip select has been changed, if yes, reset the timing
1032 if (info->cs != host->cs) {
1033 info->cs = host->cs;
1034 nand_writel(info, NDTR0CS0, info->ndtr0cs0);
1035 nand_writel(info, NDTR1CS0, info->ndtr1cs0);
1038 prepare_start_command(info, command);
1040 info->state = STATE_PREPARED;
1041 exec_cmd = prepare_set_command(info, command, 0, column, page_addr);
1046 info->cmd_complete = 0;
1047 info->dev_ready = 0;
1048 info->need_wait = 1;
1049 pxa3xx_nand_start(info);
1055 status = nand_readl(info, NDSR);
1057 pxa3xx_nand_irq(info);
1059 if (info->cmd_complete)
1062 if (get_timer(ts) > CHIP_DELAY_TIMEOUT) {
1063 dev_err(&info->pdev->dev, "Wait timeout!!!\n");
1068 info->state = STATE_IDLE;
1071 static void nand_cmdfunc_extended(struct mtd_info *mtd,
1072 const unsigned command,
1073 int column, int page_addr)
1075 struct nand_chip *chip = mtd_to_nand(mtd);
1076 struct pxa3xx_nand_host *host = nand_get_controller_data(chip);
1077 struct pxa3xx_nand_info *info = host->info_data;
1078 int exec_cmd, ext_cmd_type;
1081 * if this is a x16 device then convert the input
1082 * "byte" address into a "word" address appropriate
1083 * for indexing a word-oriented device
1085 if (info->reg_ndcr & NDCR_DWIDTH_M)
1089 * There may be different NAND chip hooked to
1090 * different chip select, so check whether
1091 * chip select has been changed, if yes, reset the timing
1093 if (info->cs != host->cs) {
1094 info->cs = host->cs;
1095 nand_writel(info, NDTR0CS0, info->ndtr0cs0);
1096 nand_writel(info, NDTR1CS0, info->ndtr1cs0);
1099 /* Select the extended command for the first command */
1101 case NAND_CMD_READ0:
1102 case NAND_CMD_READOOB:
1103 ext_cmd_type = EXT_CMD_TYPE_MONO;
1105 case NAND_CMD_SEQIN:
1106 ext_cmd_type = EXT_CMD_TYPE_DISPATCH;
1108 case NAND_CMD_PAGEPROG:
1109 ext_cmd_type = EXT_CMD_TYPE_NAKED_RW;
1116 prepare_start_command(info, command);
1119 * Prepare the "is ready" completion before starting a command
1120 * transaction sequence. If the command is not executed the
1121 * completion will be completed, see below.
1123 * We can do that inside the loop because the command variable
1124 * is invariant and thus so is the exec_cmd.
1126 info->need_wait = 1;
1127 info->dev_ready = 0;
1132 info->state = STATE_PREPARED;
1133 exec_cmd = prepare_set_command(info, command, ext_cmd_type,
1136 info->need_wait = 0;
1137 info->dev_ready = 1;
1141 info->cmd_complete = 0;
1142 pxa3xx_nand_start(info);
1148 status = nand_readl(info, NDSR);
1150 pxa3xx_nand_irq(info);
1152 if (info->cmd_complete)
1155 if (get_timer(ts) > CHIP_DELAY_TIMEOUT) {
1156 dev_err(&info->pdev->dev, "Wait timeout!!!\n");
1161 /* Only a few commands need several steps */
1162 if (command != NAND_CMD_PAGEPROG &&
1163 command != NAND_CMD_READ0 &&
1164 command != NAND_CMD_READOOB)
1169 /* Check if the sequence is complete */
1170 if (info->cur_chunk == info->ntotalchunks &&
1171 command != NAND_CMD_PAGEPROG)
1175 * After a splitted program command sequence has issued
1176 * the command dispatch, the command sequence is complete.
1178 if (info->cur_chunk == (info->ntotalchunks + 1) &&
1179 command == NAND_CMD_PAGEPROG &&
1180 ext_cmd_type == EXT_CMD_TYPE_DISPATCH)
1183 if (command == NAND_CMD_READ0 || command == NAND_CMD_READOOB) {
1184 /* Last read: issue a 'last naked read' */
1185 if (info->cur_chunk == info->ntotalchunks - 1)
1186 ext_cmd_type = EXT_CMD_TYPE_LAST_RW;
1188 ext_cmd_type = EXT_CMD_TYPE_NAKED_RW;
1191 * If a splitted program command has no more data to transfer,
1192 * the command dispatch must be issued to complete.
1194 } else if (command == NAND_CMD_PAGEPROG &&
1195 info->cur_chunk == info->ntotalchunks) {
1196 ext_cmd_type = EXT_CMD_TYPE_DISPATCH;
1200 info->state = STATE_IDLE;
1203 static int pxa3xx_nand_write_page_hwecc(struct mtd_info *mtd,
1204 struct nand_chip *chip, const uint8_t *buf, int oob_required,
1207 chip->write_buf(mtd, buf, mtd->writesize);
1208 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1213 static int pxa3xx_nand_read_page_hwecc(struct mtd_info *mtd,
1214 struct nand_chip *chip, uint8_t *buf, int oob_required,
1217 struct pxa3xx_nand_host *host = nand_get_controller_data(chip);
1218 struct pxa3xx_nand_info *info = host->info_data;
1220 chip->read_buf(mtd, buf, mtd->writesize);
1221 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1223 if (info->retcode == ERR_CORERR && info->use_ecc) {
1224 mtd->ecc_stats.corrected += info->ecc_err_cnt;
1226 } else if (info->retcode == ERR_UNCORERR) {
1228 * for blank page (all 0xff), HW will calculate its ECC as
1229 * 0, which is different from the ECC information within
1230 * OOB, ignore such uncorrectable errors
1232 if (is_buf_blank(buf, mtd->writesize))
1233 info->retcode = ERR_NONE;
1235 mtd->ecc_stats.failed++;
1238 return info->max_bitflips;
1241 static uint8_t pxa3xx_nand_read_byte(struct mtd_info *mtd)
1243 struct nand_chip *chip = mtd_to_nand(mtd);
1244 struct pxa3xx_nand_host *host = nand_get_controller_data(chip);
1245 struct pxa3xx_nand_info *info = host->info_data;
1248 if (info->buf_start < info->buf_count)
1249 /* Has just send a new command? */
1250 retval = info->data_buff[info->buf_start++];
1255 static u16 pxa3xx_nand_read_word(struct mtd_info *mtd)
1257 struct nand_chip *chip = mtd_to_nand(mtd);
1258 struct pxa3xx_nand_host *host = nand_get_controller_data(chip);
1259 struct pxa3xx_nand_info *info = host->info_data;
1260 u16 retval = 0xFFFF;
1262 if (!(info->buf_start & 0x01) && info->buf_start < info->buf_count) {
1263 retval = *((u16 *)(info->data_buff+info->buf_start));
1264 info->buf_start += 2;
1269 static void pxa3xx_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
1271 struct nand_chip *chip = mtd_to_nand(mtd);
1272 struct pxa3xx_nand_host *host = nand_get_controller_data(chip);
1273 struct pxa3xx_nand_info *info = host->info_data;
1274 int real_len = min_t(size_t, len, info->buf_count - info->buf_start);
1276 memcpy(buf, info->data_buff + info->buf_start, real_len);
1277 info->buf_start += real_len;
1280 static void pxa3xx_nand_write_buf(struct mtd_info *mtd,
1281 const uint8_t *buf, int len)
1283 struct nand_chip *chip = mtd_to_nand(mtd);
1284 struct pxa3xx_nand_host *host = nand_get_controller_data(chip);
1285 struct pxa3xx_nand_info *info = host->info_data;
1286 int real_len = min_t(size_t, len, info->buf_count - info->buf_start);
1288 memcpy(info->data_buff + info->buf_start, buf, real_len);
1289 info->buf_start += real_len;
1292 static void pxa3xx_nand_select_chip(struct mtd_info *mtd, int chip)
1297 static int pxa3xx_nand_waitfunc(struct mtd_info *mtd, struct nand_chip *this)
1299 struct nand_chip *chip = mtd_to_nand(mtd);
1300 struct pxa3xx_nand_host *host = nand_get_controller_data(chip);
1301 struct pxa3xx_nand_info *info = host->info_data;
1303 if (info->need_wait) {
1306 info->need_wait = 0;
1312 status = nand_readl(info, NDSR);
1314 pxa3xx_nand_irq(info);
1316 if (info->dev_ready)
1319 if (get_timer(ts) > CHIP_DELAY_TIMEOUT) {
1320 dev_err(&info->pdev->dev, "Ready timeout!!!\n");
1321 return NAND_STATUS_FAIL;
1326 /* pxa3xx_nand_send_command has waited for command complete */
1327 if (this->state == FL_WRITING || this->state == FL_ERASING) {
1328 if (info->retcode == ERR_NONE)
1331 return NAND_STATUS_FAIL;
1334 return NAND_STATUS_READY;
1337 static int pxa3xx_nand_config_ident(struct pxa3xx_nand_info *info)
1339 struct pxa3xx_nand_platform_data *pdata = info->pdata;
1341 /* Configure default flash values */
1342 info->reg_ndcr = 0x0; /* enable all interrupts */
1343 info->reg_ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN : 0;
1344 info->reg_ndcr |= NDCR_RD_ID_CNT(READ_ID_BYTES);
1345 info->reg_ndcr |= NDCR_SPARE_EN;
1350 static void pxa3xx_nand_config_tail(struct pxa3xx_nand_info *info)
1352 struct pxa3xx_nand_host *host = info->host[info->cs];
1353 struct mtd_info *mtd = nand_to_mtd(&info->host[info->cs]->chip);
1354 struct nand_chip *chip = mtd_to_nand(mtd);
1356 info->reg_ndcr |= (host->col_addr_cycles == 2) ? NDCR_RA_START : 0;
1357 info->reg_ndcr |= (chip->page_shift == 6) ? NDCR_PG_PER_BLK : 0;
1358 info->reg_ndcr |= (mtd->writesize == 2048) ? NDCR_PAGE_SZ : 0;
1361 static void pxa3xx_nand_detect_config(struct pxa3xx_nand_info *info)
1363 struct pxa3xx_nand_platform_data *pdata = info->pdata;
1364 uint32_t ndcr = nand_readl(info, NDCR);
1366 /* Set an initial chunk size */
1367 info->chunk_size = ndcr & NDCR_PAGE_SZ ? 2048 : 512;
1368 info->reg_ndcr = ndcr &
1369 ~(NDCR_INT_MASK | NDCR_ND_ARB_EN | NFCV1_NDCR_ARB_CNTL);
1370 info->reg_ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN : 0;
1371 info->ndtr0cs0 = nand_readl(info, NDTR0CS0);
1372 info->ndtr1cs0 = nand_readl(info, NDTR1CS0);
1375 static int pxa3xx_nand_init_buff(struct pxa3xx_nand_info *info)
1377 info->data_buff = kmalloc(info->buf_size, GFP_KERNEL);
1378 if (info->data_buff == NULL)
1383 static int pxa3xx_nand_sensing(struct pxa3xx_nand_host *host)
1385 struct pxa3xx_nand_info *info = host->info_data;
1386 struct pxa3xx_nand_platform_data *pdata = info->pdata;
1387 struct mtd_info *mtd;
1388 struct nand_chip *chip;
1389 const struct nand_sdr_timings *timings;
1392 mtd = nand_to_mtd(&info->host[info->cs]->chip);
1393 chip = mtd_to_nand(mtd);
1395 /* configure default flash values */
1396 info->reg_ndcr = 0x0; /* enable all interrupts */
1397 info->reg_ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN : 0;
1398 info->reg_ndcr |= NDCR_RD_ID_CNT(READ_ID_BYTES);
1399 info->reg_ndcr |= NDCR_SPARE_EN; /* enable spare by default */
1401 /* use the common timing to make a try */
1402 timings = onfi_async_timing_mode_to_sdr_timings(0);
1403 if (IS_ERR(timings))
1404 return PTR_ERR(timings);
1406 pxa3xx_nand_set_sdr_timing(host, timings);
1408 chip->cmdfunc(mtd, NAND_CMD_RESET, 0, 0);
1409 ret = chip->waitfunc(mtd, chip);
1410 if (ret & NAND_STATUS_FAIL)
1416 static int pxa_ecc_init(struct pxa3xx_nand_info *info,
1417 struct nand_ecc_ctrl *ecc,
1418 int strength, int ecc_stepsize, int page_size)
1420 if (strength == 1 && ecc_stepsize == 512 && page_size == 2048) {
1421 info->nfullchunks = 1;
1422 info->ntotalchunks = 1;
1423 info->chunk_size = 2048;
1424 info->spare_size = 40;
1425 info->ecc_size = 24;
1426 ecc->mode = NAND_ECC_HW;
1430 } else if (strength == 1 && ecc_stepsize == 512 && page_size == 512) {
1431 info->nfullchunks = 1;
1432 info->ntotalchunks = 1;
1433 info->chunk_size = 512;
1434 info->spare_size = 8;
1436 ecc->mode = NAND_ECC_HW;
1441 * Required ECC: 4-bit correction per 512 bytes
1442 * Select: 16-bit correction per 2048 bytes
1444 } else if (strength == 4 && ecc_stepsize == 512 && page_size == 2048) {
1446 info->nfullchunks = 1;
1447 info->ntotalchunks = 1;
1448 info->chunk_size = 2048;
1449 info->spare_size = 32;
1450 info->ecc_size = 32;
1451 ecc->mode = NAND_ECC_HW;
1452 ecc->size = info->chunk_size;
1453 ecc->layout = &ecc_layout_2KB_bch4bit;
1456 } else if (strength == 4 && ecc_stepsize == 512 && page_size == 4096) {
1458 info->nfullchunks = 2;
1459 info->ntotalchunks = 2;
1460 info->chunk_size = 2048;
1461 info->spare_size = 32;
1462 info->ecc_size = 32;
1463 ecc->mode = NAND_ECC_HW;
1464 ecc->size = info->chunk_size;
1465 ecc->layout = &ecc_layout_4KB_bch4bit;
1468 } else if (strength == 4 && ecc_stepsize == 512 && page_size == 8192) {
1470 info->nfullchunks = 4;
1471 info->ntotalchunks = 4;
1472 info->chunk_size = 2048;
1473 info->spare_size = 32;
1474 info->ecc_size = 32;
1475 ecc->mode = NAND_ECC_HW;
1476 ecc->size = info->chunk_size;
1477 ecc->layout = &ecc_layout_8KB_bch4bit;
1481 * Required ECC: 8-bit correction per 512 bytes
1482 * Select: 16-bit correction per 1024 bytes
1484 } else if (strength == 8 && ecc_stepsize == 512 && page_size == 2048) {
1486 info->nfullchunks = 1;
1487 info->ntotalchunks = 2;
1488 info->chunk_size = 1024;
1489 info->spare_size = 0;
1490 info->last_chunk_size = 1024;
1491 info->last_spare_size = 64;
1492 info->ecc_size = 32;
1493 ecc->mode = NAND_ECC_HW;
1494 ecc->size = info->chunk_size;
1495 ecc->layout = &ecc_layout_2KB_bch8bit;
1498 } else if (strength == 8 && ecc_stepsize == 512 && page_size == 4096) {
1500 info->nfullchunks = 4;
1501 info->ntotalchunks = 5;
1502 info->chunk_size = 1024;
1503 info->spare_size = 0;
1504 info->last_chunk_size = 0;
1505 info->last_spare_size = 64;
1506 info->ecc_size = 32;
1507 ecc->mode = NAND_ECC_HW;
1508 ecc->size = info->chunk_size;
1509 ecc->layout = &ecc_layout_4KB_bch8bit;
1512 } else if (strength == 8 && ecc_stepsize == 512 && page_size == 8192) {
1514 info->nfullchunks = 8;
1515 info->ntotalchunks = 9;
1516 info->chunk_size = 1024;
1517 info->spare_size = 0;
1518 info->last_chunk_size = 0;
1519 info->last_spare_size = 160;
1520 info->ecc_size = 32;
1521 ecc->mode = NAND_ECC_HW;
1522 ecc->size = info->chunk_size;
1523 ecc->layout = &ecc_layout_8KB_bch8bit;
1527 dev_err(&info->pdev->dev,
1528 "ECC strength %d at page size %d is not supported\n",
1529 strength, page_size);
1536 static int pxa3xx_nand_scan(struct mtd_info *mtd)
1538 struct nand_chip *chip = mtd_to_nand(mtd);
1539 struct pxa3xx_nand_host *host = nand_get_controller_data(chip);
1540 struct pxa3xx_nand_info *info = host->info_data;
1541 struct pxa3xx_nand_platform_data *pdata = info->pdata;
1543 uint16_t ecc_strength, ecc_step;
1545 if (pdata->keep_config) {
1546 pxa3xx_nand_detect_config(info);
1548 ret = pxa3xx_nand_config_ident(info);
1551 ret = pxa3xx_nand_sensing(host);
1553 dev_info(&info->pdev->dev,
1554 "There is no chip on cs %d!\n",
1560 /* Device detection must be done with ECC disabled */
1561 if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370)
1562 nand_writel(info, NDECCCTRL, 0x0);
1564 if (nand_scan_ident(mtd, 1, NULL))
1567 if (!pdata->keep_config) {
1568 ret = pxa3xx_nand_init_timings(host);
1570 dev_err(&info->pdev->dev,
1571 "Failed to set timings: %d\n", ret);
1576 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
1578 * We'll use a bad block table stored in-flash and don't
1579 * allow writing the bad block marker to the flash.
1581 chip->bbt_options |= NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB_BBM;
1582 chip->bbt_td = &bbt_main_descr;
1583 chip->bbt_md = &bbt_mirror_descr;
1586 if (pdata->ecc_strength && pdata->ecc_step_size) {
1587 ecc_strength = pdata->ecc_strength;
1588 ecc_step = pdata->ecc_step_size;
1590 ecc_strength = chip->ecc_strength_ds;
1591 ecc_step = chip->ecc_step_ds;
1594 /* Set default ECC strength requirements on non-ONFI devices */
1595 if (ecc_strength < 1 && ecc_step < 1) {
1600 ret = pxa_ecc_init(info, &chip->ecc, ecc_strength,
1601 ecc_step, mtd->writesize);
1606 * If the page size is bigger than the FIFO size, let's check
1607 * we are given the right variant and then switch to the extended
1608 * (aka split) command handling,
1610 if (mtd->writesize > info->chunk_size) {
1611 if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370) {
1612 chip->cmdfunc = nand_cmdfunc_extended;
1614 dev_err(&info->pdev->dev,
1615 "unsupported page size on this variant\n");
1620 /* calculate addressing information */
1621 if (mtd->writesize >= 2048)
1622 host->col_addr_cycles = 2;
1624 host->col_addr_cycles = 1;
1626 /* release the initial buffer */
1627 kfree(info->data_buff);
1629 /* allocate the real data + oob buffer */
1630 info->buf_size = mtd->writesize + mtd->oobsize;
1631 ret = pxa3xx_nand_init_buff(info);
1634 info->oob_buff = info->data_buff + mtd->writesize;
1636 if ((mtd->size >> chip->page_shift) > 65536)
1637 host->row_addr_cycles = 3;
1639 host->row_addr_cycles = 2;
1641 if (!pdata->keep_config)
1642 pxa3xx_nand_config_tail(info);
1644 return nand_scan_tail(mtd);
1647 static int alloc_nand_resource(struct pxa3xx_nand_info *info)
1649 struct pxa3xx_nand_platform_data *pdata;
1650 struct pxa3xx_nand_host *host;
1651 struct nand_chip *chip = NULL;
1652 struct mtd_info *mtd;
1655 pdata = info->pdata;
1656 if (pdata->num_cs <= 0)
1659 info->variant = pxa3xx_nand_get_variant();
1660 for (cs = 0; cs < pdata->num_cs; cs++) {
1661 chip = (struct nand_chip *)
1662 ((u8 *)&info[1] + sizeof(*host) * cs);
1663 mtd = nand_to_mtd(chip);
1664 host = (struct pxa3xx_nand_host *)chip;
1665 info->host[cs] = host;
1667 host->info_data = info;
1668 mtd->owner = THIS_MODULE;
1670 nand_set_controller_data(chip, host);
1671 chip->ecc.read_page = pxa3xx_nand_read_page_hwecc;
1672 chip->ecc.write_page = pxa3xx_nand_write_page_hwecc;
1673 chip->controller = &info->controller;
1674 chip->waitfunc = pxa3xx_nand_waitfunc;
1675 chip->select_chip = pxa3xx_nand_select_chip;
1676 chip->read_word = pxa3xx_nand_read_word;
1677 chip->read_byte = pxa3xx_nand_read_byte;
1678 chip->read_buf = pxa3xx_nand_read_buf;
1679 chip->write_buf = pxa3xx_nand_write_buf;
1680 chip->options |= NAND_NO_SUBPAGE_WRITE;
1681 chip->cmdfunc = nand_cmdfunc;
1684 /* Allocate a buffer to allow flash detection */
1685 info->buf_size = INIT_BUFFER_SIZE;
1686 info->data_buff = kmalloc(info->buf_size, GFP_KERNEL);
1687 if (info->data_buff == NULL) {
1689 goto fail_disable_clk;
1692 /* initialize all interrupts to be disabled */
1693 disable_int(info, NDSR_MASK);
1697 kfree(info->data_buff);
1702 static int pxa3xx_nand_probe_dt(struct pxa3xx_nand_info *info)
1704 struct pxa3xx_nand_platform_data *pdata;
1705 const void *blob = gd->fdt_blob;
1708 pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
1712 /* Get address decoding nodes from the FDT blob */
1714 node = fdt_node_offset_by_compatible(blob, node,
1715 "marvell,mvebu-pxa3xx-nand");
1719 /* Bypass disabeld nodes */
1720 if (!fdtdec_get_is_enabled(blob, node))
1723 /* Get the first enabled NAND controler base address */
1725 (void __iomem *)fdtdec_get_addr_size_auto_noparent(
1726 blob, node, "reg", 0, NULL, true);
1728 pdata->num_cs = fdtdec_get_int(blob, node, "num-cs", 1);
1729 if (pdata->num_cs != 1) {
1730 pr_err("pxa3xx driver supports single CS only\n");
1734 if (fdtdec_get_bool(blob, node, "nand-enable-arbiter"))
1735 pdata->enable_arbiter = 1;
1737 if (fdtdec_get_bool(blob, node, "nand-keep-config"))
1738 pdata->keep_config = 1;
1742 * If these are not set, they will be selected according
1743 * to the detected flash type.
1746 pdata->ecc_strength = fdtdec_get_int(blob, node,
1747 "nand-ecc-strength", 0);
1750 pdata->ecc_step_size = fdtdec_get_int(blob, node,
1751 "nand-ecc-step-size", 0);
1753 info->pdata = pdata;
1755 /* Currently support only a single NAND controller */
1758 } while (node >= 0);
1763 static int pxa3xx_nand_probe(struct pxa3xx_nand_info *info)
1765 struct pxa3xx_nand_platform_data *pdata;
1766 int ret, cs, probe_success;
1768 ret = pxa3xx_nand_probe_dt(info);
1772 pdata = info->pdata;
1774 ret = alloc_nand_resource(info);
1776 dev_err(&pdev->dev, "alloc nand resource failed\n");
1781 for (cs = 0; cs < pdata->num_cs; cs++) {
1782 struct mtd_info *mtd = nand_to_mtd(&info->host[cs]->chip);
1785 * The mtd name matches the one used in 'mtdparts' kernel
1786 * parameter. This name cannot be changed or otherwise
1787 * user's mtd partitions configuration would get broken.
1789 mtd->name = "pxa3xx_nand-0";
1791 ret = pxa3xx_nand_scan(mtd);
1793 dev_info(&pdev->dev, "failed to scan nand at cs %d\n",
1798 if (nand_register(cs, mtd))
1811 * Main initialization routine
1813 void board_nand_init(void)
1815 struct pxa3xx_nand_info *info;
1816 struct pxa3xx_nand_host *host;
1819 info = kzalloc(sizeof(*info) +
1820 sizeof(*host) * CONFIG_SYS_MAX_NAND_DEVICE,
1825 ret = pxa3xx_nand_probe(info);