drivers/mtd/nand/raw/nuc900_nand.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright © 2009 Nuvoton technology corporation.
   4  *
   5  * Wan ZongShun <mcuos.com@gmail.com>
   6  */
   7
   8 #include <linux/slab.h>
   9 #include <linux/module.h>
  10 #include <linux/interrupt.h>
  11 #include <linux/io.h>
  12 #include <linux/platform_device.h>
  13 #include <linux/delay.h>
  14 #include <linux/clk.h>
  15 #include <linux/err.h>
  16
  17 #include <linux/mtd/mtd.h>
  18 #include <linux/mtd/rawnand.h>
  19 #include <linux/mtd/partitions.h>
  20
  21 #define REG_FMICSR      0x00
  22 #define REG_SMCSR       0xa0
  23 #define REG_SMISR       0xac
  24 #define REG_SMCMD       0xb0
  25 #define REG_SMADDR      0xb4
  26 #define REG_SMDATA      0xb8
  27
  28 #define RESET_FMI       0x01
  29 #define NAND_EN         0x08
  30 #define READYBUSY       (0x01 << 18)
  31
  32 #define SWRST           0x01
  33 #define PSIZE           (0x01 << 3)
  34 #define DMARWEN         (0x03 << 1)
  35 #define BUSWID          (0x01 << 4)
  36 #define ECC4EN          (0x01 << 5)
  37 #define WP              (0x01 << 24)
  38 #define NANDCS          (0x01 << 25)
  39 #define ENDADDR         (0x01 << 31)
  40
  41 #define read_data_reg(dev)              \
  42         __raw_readl((dev)->reg + REG_SMDATA)
  43
  44 #define write_data_reg(dev, val)        \
  45         __raw_writel((val), (dev)->reg + REG_SMDATA)
  46
  47 #define write_cmd_reg(dev, val)         \
  48         __raw_writel((val), (dev)->reg + REG_SMCMD)
  49
  50 #define write_addr_reg(dev, val)        \
  51         __raw_writel((val), (dev)->reg + REG_SMADDR)
  52
  53 struct nuc900_nand {
  54         struct nand_chip chip;
  55         void __iomem *reg;
  56         struct clk *clk;
  57         spinlock_t lock;
  58 };
  59
  60 static inline struct nuc900_nand *mtd_to_nuc900(struct mtd_info *mtd)
  61 {
  62         return container_of(mtd_to_nand(mtd), struct nuc900_nand, chip);
  63 }
  64
  65 static const struct mtd_partition partitions[] = {
  66         {
  67          .name = "NAND FS 0",
  68          .offset = 0,
  69          .size = 8 * 1024 * 1024
  70         },
  71         {
  72          .name = "NAND FS 1",
  73          .offset = MTDPART_OFS_APPEND,
  74          .size = MTDPART_SIZ_FULL
  75         }
  76 };
  77
  78 static unsigned char nuc900_nand_read_byte(struct nand_chip *chip)
  79 {
  80         unsigned char ret;
  81         struct nuc900_nand *nand = mtd_to_nuc900(nand_to_mtd(chip));
  82
  83         ret = (unsigned char)read_data_reg(nand);
  84
  85         return ret;
  86 }
  87
  88 static void nuc900_nand_read_buf(struct nand_chip *chip,
  89                                  unsigned char *buf, int len)
  90 {
  91         int i;
  92         struct nuc900_nand *nand = mtd_to_nuc900(nand_to_mtd(chip));
  93
  94         for (i = 0; i < len; i++)
  95                 buf[i] = (unsigned char)read_data_reg(nand);
  96 }
  97
  98 static void nuc900_nand_write_buf(struct nand_chip *chip,
  99                                   const unsigned char *buf, int len)
 100 {
 101         int i;
 102         struct nuc900_nand *nand = mtd_to_nuc900(nand_to_mtd(chip));
 103
 104         for (i = 0; i < len; i++)
 105                 write_data_reg(nand, buf[i]);
 106 }
 107
 108 static int nuc900_check_rb(struct nuc900_nand *nand)
 109 {
 110         unsigned int val;
 111         spin_lock(&nand->lock);
 112         val = __raw_readl(nand->reg + REG_SMISR);
 113         val &= READYBUSY;
 114         spin_unlock(&nand->lock);
 115
 116         return val;
 117 }
 118
 119 static int nuc900_nand_devready(struct nand_chip *chip)
 120 {
 121         struct nuc900_nand *nand = mtd_to_nuc900(nand_to_mtd(chip));
 122         int ready;
 123
 124         ready = (nuc900_check_rb(nand)) ? 1 : 0;
 125         return ready;
 126 }
 127
 128 static void nuc900_nand_command_lp(struct nand_chip *chip,
 129                                    unsigned int command,
 130                                    int column, int page_addr)
 131 {
 132         struct mtd_info *mtd = nand_to_mtd(chip);
 133         struct nuc900_nand *nand = mtd_to_nuc900(mtd);
 134
 135         if (command == NAND_CMD_READOOB) {
 136                 column += mtd->writesize;
 137                 command = NAND_CMD_READ0;
 138         }
 139
 140         write_cmd_reg(nand, command & 0xff);
 141
 142         if (column != -1 || page_addr != -1) {
 143
 144                 if (column != -1) {
 145                         if (chip->options & NAND_BUSWIDTH_16 &&
 146                                         !nand_opcode_8bits(command))
 147                                 column >>= 1;
 148                         write_addr_reg(nand, column);
 149                         write_addr_reg(nand, column >> 8 | ENDADDR);
 150                 }
 151                 if (page_addr != -1) {
 152                         write_addr_reg(nand, page_addr);
 153
 154                         if (chip->options & NAND_ROW_ADDR_3) {
 155                                 write_addr_reg(nand, page_addr >> 8);
 156                                 write_addr_reg(nand, page_addr >> 16 | ENDADDR);
 157                         } else {
 158                                 write_addr_reg(nand, page_addr >> 8 | ENDADDR);
 159                         }
 160                 }
 161         }
 162
 163         switch (command) {
 164         case NAND_CMD_CACHEDPROG:
 165         case NAND_CMD_PAGEPROG:
 166         case NAND_CMD_ERASE1:
 167         case NAND_CMD_ERASE2:
 168         case NAND_CMD_SEQIN:
 169         case NAND_CMD_RNDIN:
 170         case NAND_CMD_STATUS:
 171                 return;
 172
 173         case NAND_CMD_RESET:
 174                 if (chip->legacy.dev_ready)
 175                         break;
 176                 udelay(chip->legacy.chip_delay);
 177
 178                 write_cmd_reg(nand, NAND_CMD_STATUS);
 179                 write_cmd_reg(nand, command);
 180
 181                 while (!nuc900_check_rb(nand))
 182                         ;
 183
 184                 return;
 185
 186         case NAND_CMD_RNDOUT:
 187                 write_cmd_reg(nand, NAND_CMD_RNDOUTSTART);
 188                 return;
 189
 190         case NAND_CMD_READ0:
 191                 write_cmd_reg(nand, NAND_CMD_READSTART);
 192                 /* fall through */
 193
 194         default:
 195
 196                 if (!chip->legacy.dev_ready) {
 197                         udelay(chip->legacy.chip_delay);
 198                         return;
 199                 }
 200         }
 201
 202         /* Apply this short delay always to ensure that we do wait tWB in
 203          * any case on any machine. */
 204         ndelay(100);
 205
 206         while (!chip->legacy.dev_ready(chip))
 207                 ;
 208 }
 209
 210
 211 static void nuc900_nand_enable(struct nuc900_nand *nand)
 212 {
 213         unsigned int val;
 214         spin_lock(&nand->lock);
 215         __raw_writel(RESET_FMI, (nand->reg + REG_FMICSR));
 216
 217         val = __raw_readl(nand->reg + REG_FMICSR);
 218
 219         if (!(val & NAND_EN))
 220                 __raw_writel(val | NAND_EN, nand->reg + REG_FMICSR);
 221
 222         val = __raw_readl(nand->reg + REG_SMCSR);
 223
 224         val &= ~(SWRST|PSIZE|DMARWEN|BUSWID|ECC4EN|NANDCS);
 225         val |= WP;
 226
 227         __raw_writel(val, nand->reg + REG_SMCSR);
 228
 229         spin_unlock(&nand->lock);
 230 }
 231
 232 static int nuc900_nand_probe(struct platform_device *pdev)
 233 {
 234         struct nuc900_nand *nuc900_nand;
 235         struct nand_chip *chip;
 236         struct mtd_info *mtd;
 237         struct resource *res;
 238
 239         nuc900_nand = devm_kzalloc(&pdev->dev, sizeof(struct nuc900_nand),
 240                                    GFP_KERNEL);
 241         if (!nuc900_nand)
 242                 return -ENOMEM;
 243         chip = &(nuc900_nand->chip);
 244         mtd = nand_to_mtd(chip);
 245
 246         mtd->dev.parent         = &pdev->dev;
 247         spin_lock_init(&nuc900_nand->lock);
 248
 249         nuc900_nand->clk = devm_clk_get(&pdev->dev, NULL);
 250         if (IS_ERR(nuc900_nand->clk))
 251                 return -ENOENT;
 252         clk_enable(nuc900_nand->clk);
 253
 254         chip->legacy.cmdfunc    = nuc900_nand_command_lp;
 255         chip->legacy.dev_ready  = nuc900_nand_devready;
 256         chip->legacy.read_byte  = nuc900_nand_read_byte;
 257         chip->legacy.write_buf  = nuc900_nand_write_buf;
 258         chip->legacy.read_buf   = nuc900_nand_read_buf;
 259         chip->legacy.chip_delay = 50;
 260         chip->options           = 0;
 261         chip->ecc.mode          = NAND_ECC_SOFT;
 262         chip->ecc.algo          = NAND_ECC_HAMMING;
 263
 264         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 265         nuc900_nand->reg = devm_ioremap_resource(&pdev->dev, res);
 266         if (IS_ERR(nuc900_nand->reg))
 267                 return PTR_ERR(nuc900_nand->reg);
 268
 269         nuc900_nand_enable(nuc900_nand);
 270
 271         if (nand_scan(chip, 1))
 272                 return -ENXIO;
 273
 274         mtd_device_register(mtd, partitions, ARRAY_SIZE(partitions));
 275
 276         platform_set_drvdata(pdev, nuc900_nand);
 277
 278         return 0;
 279 }
 280
 281 static int nuc900_nand_remove(struct platform_device *pdev)
 282 {
 283         struct nuc900_nand *nuc900_nand = platform_get_drvdata(pdev);
 284
 285         nand_release(&nuc900_nand->chip);
 286         clk_disable(nuc900_nand->clk);
 287
 288         return 0;
 289 }
 290
 291 static struct platform_driver nuc900_nand_driver = {
 292         .probe          = nuc900_nand_probe,
 293         .remove         = nuc900_nand_remove,
 294         .driver         = {
 295                 .name   = "nuc900-fmi",
 296         },
 297 };
 298
 299 module_platform_driver(nuc900_nand_driver);
 300
 301 MODULE_AUTHOR("Wan ZongShun <mcuos.com@gmail.com>");
 302 MODULE_DESCRIPTION("w90p910/NUC9xx nand driver!");
 303 MODULE_LICENSE("GPL");
 304 MODULE_ALIAS("platform:nuc900-fmi");