1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
4 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
7 * David Woodhouse for adding multichip support
9 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
10 * rework for 2K page size chips
12 * This file contains all legacy helpers/code that should be removed
16 #include <linux/delay.h>
18 #include <linux/nmi.h>
20 #include "internals.h"
23 * nand_read_byte - [DEFAULT] read one byte from the chip
24 * @chip: NAND chip object
26 * Default read function for 8bit buswidth
28 static uint8_t nand_read_byte(struct nand_chip *chip)
30 return readb(chip->legacy.IO_ADDR_R);
34 * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
35 * @chip: NAND chip object
37 * Default read function for 16bit buswidth with endianness conversion.
40 static uint8_t nand_read_byte16(struct nand_chip *chip)
42 return (uint8_t) cpu_to_le16(readw(chip->legacy.IO_ADDR_R));
46 * nand_select_chip - [DEFAULT] control CE line
47 * @chip: NAND chip object
48 * @chipnr: chipnumber to select, -1 for deselect
50 * Default select function for 1 chip devices.
52 static void nand_select_chip(struct nand_chip *chip, int chipnr)
56 chip->legacy.cmd_ctrl(chip, NAND_CMD_NONE,
57 0 | NAND_CTRL_CHANGE);
68 * nand_write_byte - [DEFAULT] write single byte to chip
69 * @chip: NAND chip object
70 * @byte: value to write
72 * Default function to write a byte to I/O[7:0]
74 static void nand_write_byte(struct nand_chip *chip, uint8_t byte)
76 chip->legacy.write_buf(chip, &byte, 1);
80 * nand_write_byte16 - [DEFAULT] write single byte to a chip with width 16
81 * @chip: NAND chip object
82 * @byte: value to write
84 * Default function to write a byte to I/O[7:0] on a 16-bit wide chip.
86 static void nand_write_byte16(struct nand_chip *chip, uint8_t byte)
91 * It's not entirely clear what should happen to I/O[15:8] when writing
92 * a byte. The ONFi spec (Revision 3.1; 2012-09-19, Section 2.16) reads:
94 * When the host supports a 16-bit bus width, only data is
95 * transferred at the 16-bit width. All address and command line
96 * transfers shall use only the lower 8-bits of the data bus. During
97 * command transfers, the host may place any value on the upper
98 * 8-bits of the data bus. During address transfers, the host shall
99 * set the upper 8-bits of the data bus to 00h.
101 * One user of the write_byte callback is nand_set_features. The
102 * four parameters are specified to be written to I/O[7:0], but this is
103 * neither an address nor a command transfer. Let's assume a 0 on the
104 * upper I/O lines is OK.
106 chip->legacy.write_buf(chip, (uint8_t *)&word, 2);
110 * nand_write_buf - [DEFAULT] write buffer to chip
111 * @chip: NAND chip object
113 * @len: number of bytes to write
115 * Default write function for 8bit buswidth.
117 static void nand_write_buf(struct nand_chip *chip, const uint8_t *buf, int len)
119 iowrite8_rep(chip->legacy.IO_ADDR_W, buf, len);
123 * nand_read_buf - [DEFAULT] read chip data into buffer
124 * @chip: NAND chip object
125 * @buf: buffer to store date
126 * @len: number of bytes to read
128 * Default read function for 8bit buswidth.
130 static void nand_read_buf(struct nand_chip *chip, uint8_t *buf, int len)
132 ioread8_rep(chip->legacy.IO_ADDR_R, buf, len);
136 * nand_write_buf16 - [DEFAULT] write buffer to chip
137 * @chip: NAND chip object
139 * @len: number of bytes to write
141 * Default write function for 16bit buswidth.
143 static void nand_write_buf16(struct nand_chip *chip, const uint8_t *buf,
146 u16 *p = (u16 *) buf;
148 iowrite16_rep(chip->legacy.IO_ADDR_W, p, len >> 1);
152 * nand_read_buf16 - [DEFAULT] read chip data into buffer
153 * @chip: NAND chip object
154 * @buf: buffer to store date
155 * @len: number of bytes to read
157 * Default read function for 16bit buswidth.
159 static void nand_read_buf16(struct nand_chip *chip, uint8_t *buf, int len)
161 u16 *p = (u16 *) buf;
163 ioread16_rep(chip->legacy.IO_ADDR_R, p, len >> 1);
167 * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
168 * @chip: NAND chip object
171 * Helper function for nand_wait_ready used when needing to wait in interrupt
174 static void panic_nand_wait_ready(struct nand_chip *chip, unsigned long timeo)
178 /* Wait for the device to get ready */
179 for (i = 0; i < timeo; i++) {
180 if (chip->legacy.dev_ready(chip))
182 touch_softlockup_watchdog();
188 * nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
189 * @chip: NAND chip object
191 * Wait for the ready pin after a command, and warn if a timeout occurs.
193 void nand_wait_ready(struct nand_chip *chip)
195 unsigned long timeo = 400;
197 if (in_interrupt() || oops_in_progress)
198 return panic_nand_wait_ready(chip, timeo);
200 /* Wait until command is processed or timeout occurs */
201 timeo = jiffies + msecs_to_jiffies(timeo);
203 if (chip->legacy.dev_ready(chip))
206 } while (time_before(jiffies, timeo));
208 if (!chip->legacy.dev_ready(chip))
209 pr_warn_ratelimited("timeout while waiting for chip to become ready\n");
211 EXPORT_SYMBOL_GPL(nand_wait_ready);
214 * nand_wait_status_ready - [GENERIC] Wait for the ready status after commands.
215 * @chip: NAND chip object
216 * @timeo: Timeout in ms
218 * Wait for status ready (i.e. command done) or timeout.
220 static void nand_wait_status_ready(struct nand_chip *chip, unsigned long timeo)
224 timeo = jiffies + msecs_to_jiffies(timeo);
228 ret = nand_read_data_op(chip, &status, sizeof(status), true);
232 if (status & NAND_STATUS_READY)
234 touch_softlockup_watchdog();
235 } while (time_before(jiffies, timeo));
239 * nand_command - [DEFAULT] Send command to NAND device
240 * @chip: NAND chip object
241 * @command: the command to be sent
242 * @column: the column address for this command, -1 if none
243 * @page_addr: the page address for this command, -1 if none
245 * Send command to NAND device. This function is used for small page devices
246 * (512 Bytes per page).
248 static void nand_command(struct nand_chip *chip, unsigned int command,
249 int column, int page_addr)
251 struct mtd_info *mtd = nand_to_mtd(chip);
252 int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
254 /* Write out the command to the device */
255 if (command == NAND_CMD_SEQIN) {
258 if (column >= mtd->writesize) {
260 column -= mtd->writesize;
261 readcmd = NAND_CMD_READOOB;
262 } else if (column < 256) {
263 /* First 256 bytes --> READ0 */
264 readcmd = NAND_CMD_READ0;
267 readcmd = NAND_CMD_READ1;
269 chip->legacy.cmd_ctrl(chip, readcmd, ctrl);
270 ctrl &= ~NAND_CTRL_CHANGE;
272 if (command != NAND_CMD_NONE)
273 chip->legacy.cmd_ctrl(chip, command, ctrl);
275 /* Address cycle, when necessary */
276 ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
277 /* Serially input address */
279 /* Adjust columns for 16 bit buswidth */
280 if (chip->options & NAND_BUSWIDTH_16 &&
281 !nand_opcode_8bits(command))
283 chip->legacy.cmd_ctrl(chip, column, ctrl);
284 ctrl &= ~NAND_CTRL_CHANGE;
286 if (page_addr != -1) {
287 chip->legacy.cmd_ctrl(chip, page_addr, ctrl);
288 ctrl &= ~NAND_CTRL_CHANGE;
289 chip->legacy.cmd_ctrl(chip, page_addr >> 8, ctrl);
290 if (chip->options & NAND_ROW_ADDR_3)
291 chip->legacy.cmd_ctrl(chip, page_addr >> 16, ctrl);
293 chip->legacy.cmd_ctrl(chip, NAND_CMD_NONE,
294 NAND_NCE | NAND_CTRL_CHANGE);
297 * Program and erase have their own busy handlers status and sequential
303 case NAND_CMD_PAGEPROG:
304 case NAND_CMD_ERASE1:
305 case NAND_CMD_ERASE2:
307 case NAND_CMD_STATUS:
308 case NAND_CMD_READID:
309 case NAND_CMD_SET_FEATURES:
313 if (chip->legacy.dev_ready)
315 udelay(chip->legacy.chip_delay);
316 chip->legacy.cmd_ctrl(chip, NAND_CMD_STATUS,
317 NAND_CTRL_CLE | NAND_CTRL_CHANGE);
318 chip->legacy.cmd_ctrl(chip, NAND_CMD_NONE,
319 NAND_NCE | NAND_CTRL_CHANGE);
320 /* EZ-NAND can take upto 250ms as per ONFi v4.0 */
321 nand_wait_status_ready(chip, 250);
324 /* This applies to read commands */
327 * READ0 is sometimes used to exit GET STATUS mode. When this
328 * is the case no address cycles are requested, and we can use
329 * this information to detect that we should not wait for the
330 * device to be ready.
332 if (column == -1 && page_addr == -1)
338 * If we don't have access to the busy pin, we apply the given
341 if (!chip->legacy.dev_ready) {
342 udelay(chip->legacy.chip_delay);
347 * Apply this short delay always to ensure that we do wait tWB in
348 * any case on any machine.
352 nand_wait_ready(chip);
355 static void nand_ccs_delay(struct nand_chip *chip)
358 * The controller already takes care of waiting for tCCS when the RNDIN
359 * or RNDOUT command is sent, return directly.
361 if (!(chip->options & NAND_WAIT_TCCS))
365 * Wait tCCS_min if it is correctly defined, otherwise wait 500ns
366 * (which should be safe for all NANDs).
368 if (nand_has_setup_data_iface(chip))
369 ndelay(chip->data_interface.timings.sdr.tCCS_min / 1000);
375 * nand_command_lp - [DEFAULT] Send command to NAND large page device
376 * @chip: NAND chip object
377 * @command: the command to be sent
378 * @column: the column address for this command, -1 if none
379 * @page_addr: the page address for this command, -1 if none
381 * Send command to NAND device. This is the version for the new large page
382 * devices. We don't have the separate regions as we have in the small page
383 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
385 static void nand_command_lp(struct nand_chip *chip, unsigned int command,
386 int column, int page_addr)
388 struct mtd_info *mtd = nand_to_mtd(chip);
390 /* Emulate NAND_CMD_READOOB */
391 if (command == NAND_CMD_READOOB) {
392 column += mtd->writesize;
393 command = NAND_CMD_READ0;
396 /* Command latch cycle */
397 if (command != NAND_CMD_NONE)
398 chip->legacy.cmd_ctrl(chip, command,
399 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
401 if (column != -1 || page_addr != -1) {
402 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
404 /* Serially input address */
406 /* Adjust columns for 16 bit buswidth */
407 if (chip->options & NAND_BUSWIDTH_16 &&
408 !nand_opcode_8bits(command))
410 chip->legacy.cmd_ctrl(chip, column, ctrl);
411 ctrl &= ~NAND_CTRL_CHANGE;
413 /* Only output a single addr cycle for 8bits opcodes. */
414 if (!nand_opcode_8bits(command))
415 chip->legacy.cmd_ctrl(chip, column >> 8, ctrl);
417 if (page_addr != -1) {
418 chip->legacy.cmd_ctrl(chip, page_addr, ctrl);
419 chip->legacy.cmd_ctrl(chip, page_addr >> 8,
420 NAND_NCE | NAND_ALE);
421 if (chip->options & NAND_ROW_ADDR_3)
422 chip->legacy.cmd_ctrl(chip, page_addr >> 16,
423 NAND_NCE | NAND_ALE);
426 chip->legacy.cmd_ctrl(chip, NAND_CMD_NONE,
427 NAND_NCE | NAND_CTRL_CHANGE);
430 * Program and erase have their own busy handlers status, sequential
431 * in and status need no delay.
436 case NAND_CMD_CACHEDPROG:
437 case NAND_CMD_PAGEPROG:
438 case NAND_CMD_ERASE1:
439 case NAND_CMD_ERASE2:
441 case NAND_CMD_STATUS:
442 case NAND_CMD_READID:
443 case NAND_CMD_SET_FEATURES:
447 nand_ccs_delay(chip);
451 if (chip->legacy.dev_ready)
453 udelay(chip->legacy.chip_delay);
454 chip->legacy.cmd_ctrl(chip, NAND_CMD_STATUS,
455 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
456 chip->legacy.cmd_ctrl(chip, NAND_CMD_NONE,
457 NAND_NCE | NAND_CTRL_CHANGE);
458 /* EZ-NAND can take upto 250ms as per ONFi v4.0 */
459 nand_wait_status_ready(chip, 250);
462 case NAND_CMD_RNDOUT:
463 /* No ready / busy check necessary */
464 chip->legacy.cmd_ctrl(chip, NAND_CMD_RNDOUTSTART,
465 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
466 chip->legacy.cmd_ctrl(chip, NAND_CMD_NONE,
467 NAND_NCE | NAND_CTRL_CHANGE);
469 nand_ccs_delay(chip);
474 * READ0 is sometimes used to exit GET STATUS mode. When this
475 * is the case no address cycles are requested, and we can use
476 * this information to detect that READSTART should not be
479 if (column == -1 && page_addr == -1)
482 chip->legacy.cmd_ctrl(chip, NAND_CMD_READSTART,
483 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
484 chip->legacy.cmd_ctrl(chip, NAND_CMD_NONE,
485 NAND_NCE | NAND_CTRL_CHANGE);
487 /* fall through - This applies to read commands */
490 * If we don't have access to the busy pin, we apply the given
493 if (!chip->legacy.dev_ready) {
494 udelay(chip->legacy.chip_delay);
500 * Apply this short delay always to ensure that we do wait tWB in
501 * any case on any machine.
505 nand_wait_ready(chip);
509 * nand_get_set_features_notsupp - set/get features stub returning -ENOTSUPP
510 * @chip: nand chip info structure
511 * @addr: feature address.
512 * @subfeature_param: the subfeature parameters, a four bytes array.
514 * Should be used by NAND controller drivers that do not support the SET/GET
515 * FEATURES operations.
517 int nand_get_set_features_notsupp(struct nand_chip *chip, int addr,
518 u8 *subfeature_param)
522 EXPORT_SYMBOL(nand_get_set_features_notsupp);
525 * nand_wait - [DEFAULT] wait until the command is done
526 * @chip: NAND chip structure
528 * Wait for command done. This applies to erase and program only.
530 static int nand_wait(struct nand_chip *chip)
533 unsigned long timeo = 400;
538 * Apply this short delay always to ensure that we do wait tWB in any
539 * case on any machine.
543 ret = nand_status_op(chip, NULL);
547 if (in_interrupt() || oops_in_progress)
548 panic_nand_wait(chip, timeo);
550 timeo = jiffies + msecs_to_jiffies(timeo);
552 if (chip->legacy.dev_ready) {
553 if (chip->legacy.dev_ready(chip))
556 ret = nand_read_data_op(chip, &status,
557 sizeof(status), true);
561 if (status & NAND_STATUS_READY)
565 } while (time_before(jiffies, timeo));
568 ret = nand_read_data_op(chip, &status, sizeof(status), true);
572 /* This can happen if in case of timeout or buggy dev_ready */
573 WARN_ON(!(status & NAND_STATUS_READY));
577 void nand_legacy_set_defaults(struct nand_chip *chip)
579 unsigned int busw = chip->options & NAND_BUSWIDTH_16;
581 if (nand_has_exec_op(chip))
584 /* check for proper chip_delay setup, set 20us if not */
585 if (!chip->legacy.chip_delay)
586 chip->legacy.chip_delay = 20;
588 /* check, if a user supplied command function given */
589 if (!chip->legacy.cmdfunc)
590 chip->legacy.cmdfunc = nand_command;
592 /* check, if a user supplied wait function given */
593 if (chip->legacy.waitfunc == NULL)
594 chip->legacy.waitfunc = nand_wait;
596 if (!chip->legacy.select_chip)
597 chip->legacy.select_chip = nand_select_chip;
599 /* If called twice, pointers that depend on busw may need to be reset */
600 if (!chip->legacy.read_byte || chip->legacy.read_byte == nand_read_byte)
601 chip->legacy.read_byte = busw ? nand_read_byte16 : nand_read_byte;
602 if (!chip->legacy.write_buf || chip->legacy.write_buf == nand_write_buf)
603 chip->legacy.write_buf = busw ? nand_write_buf16 : nand_write_buf;
604 if (!chip->legacy.write_byte || chip->legacy.write_byte == nand_write_byte)
605 chip->legacy.write_byte = busw ? nand_write_byte16 : nand_write_byte;
606 if (!chip->legacy.read_buf || chip->legacy.read_buf == nand_read_buf)
607 chip->legacy.read_buf = busw ? nand_read_buf16 : nand_read_buf;
610 void nand_legacy_adjust_cmdfunc(struct nand_chip *chip)
612 struct mtd_info *mtd = nand_to_mtd(chip);
614 /* Do not replace user supplied command function! */
615 if (mtd->writesize > 512 && chip->legacy.cmdfunc == nand_command)
616 chip->legacy.cmdfunc = nand_command_lp;
619 int nand_legacy_check_hooks(struct nand_chip *chip)
622 * ->legacy.cmdfunc() is legacy and will only be used if ->exec_op() is
625 if (nand_has_exec_op(chip))
629 * Default functions assigned for ->legacy.cmdfunc() and
630 * ->legacy.select_chip() both expect ->legacy.cmd_ctrl() to be
633 if ((!chip->legacy.cmdfunc || !chip->legacy.select_chip) &&
634 !chip->legacy.cmd_ctrl) {
635 pr_err("->legacy.cmd_ctrl() should be provided\n");