3 * This is the generic MTD driver for NAND flash devices. It should be
4 * capable of working with almost all NAND chips currently available.
6 * Additional technical information is available on
7 * http://www.linux-mtd.infradead.org/doc/nand.html
9 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
10 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
13 * David Woodhouse for adding multichip support
15 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
16 * rework for 2K page size chips
19 * Enable cached programming for 2k page size chips
20 * Check, if mtd->ecctype should be set to MTD_ECC_HW
21 * if we have HW ECC support.
22 * BBT table is not serialized, has to be fixed
24 * This program is free software; you can redistribute it and/or modify
25 * it under the terms of the GNU General Public License version 2 as
26 * published by the Free Software Foundation.
30 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
32 #if CONFIG_IS_ENABLED(OF_CONTROL)
37 #include <linux/err.h>
38 #include <linux/compat.h>
39 #include <linux/mtd/mtd.h>
40 #include <linux/mtd/rawnand.h>
41 #include <linux/mtd/nand_ecc.h>
42 #include <linux/mtd/nand_bch.h>
43 #ifdef CONFIG_MTD_PARTITIONS
44 #include <linux/mtd/partitions.h>
47 #include <linux/errno.h>
49 /* Define default oob placement schemes for large and small page devices */
50 static struct nand_ecclayout nand_oob_8 = {
60 static struct nand_ecclayout nand_oob_16 = {
62 .eccpos = {0, 1, 2, 3, 6, 7},
68 static struct nand_ecclayout nand_oob_64 = {
71 40, 41, 42, 43, 44, 45, 46, 47,
72 48, 49, 50, 51, 52, 53, 54, 55,
73 56, 57, 58, 59, 60, 61, 62, 63},
79 static struct nand_ecclayout nand_oob_128 = {
82 80, 81, 82, 83, 84, 85, 86, 87,
83 88, 89, 90, 91, 92, 93, 94, 95,
84 96, 97, 98, 99, 100, 101, 102, 103,
85 104, 105, 106, 107, 108, 109, 110, 111,
86 112, 113, 114, 115, 116, 117, 118, 119,
87 120, 121, 122, 123, 124, 125, 126, 127},
93 static int nand_get_device(struct mtd_info *mtd, int new_state);
95 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
96 struct mtd_oob_ops *ops);
99 * For devices which display every fart in the system on a separate LED. Is
100 * compiled away when LED support is disabled.
102 DEFINE_LED_TRIGGER(nand_led_trigger);
104 static int check_offs_len(struct mtd_info *mtd,
105 loff_t ofs, uint64_t len)
107 struct nand_chip *chip = mtd_to_nand(mtd);
110 /* Start address must align on block boundary */
111 if (ofs & ((1ULL << chip->phys_erase_shift) - 1)) {
112 pr_debug("%s: unaligned address\n", __func__);
116 /* Length must align on block boundary */
117 if (len & ((1ULL << chip->phys_erase_shift) - 1)) {
118 pr_debug("%s: length not block aligned\n", __func__);
126 * nand_release_device - [GENERIC] release chip
127 * @mtd: MTD device structure
129 * Release chip lock and wake up anyone waiting on the device.
131 static void nand_release_device(struct mtd_info *mtd)
133 struct nand_chip *chip = mtd_to_nand(mtd);
135 /* De-select the NAND device */
136 chip->select_chip(mtd, -1);
140 * nand_read_byte - [DEFAULT] read one byte from the chip
141 * @mtd: MTD device structure
143 * Default read function for 8bit buswidth
145 uint8_t nand_read_byte(struct mtd_info *mtd)
147 struct nand_chip *chip = mtd_to_nand(mtd);
148 return readb(chip->IO_ADDR_R);
152 * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
153 * @mtd: MTD device structure
155 * Default read function for 16bit buswidth with endianness conversion.
158 static uint8_t nand_read_byte16(struct mtd_info *mtd)
160 struct nand_chip *chip = mtd_to_nand(mtd);
161 return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
165 * nand_read_word - [DEFAULT] read one word from the chip
166 * @mtd: MTD device structure
168 * Default read function for 16bit buswidth without endianness conversion.
170 static u16 nand_read_word(struct mtd_info *mtd)
172 struct nand_chip *chip = mtd_to_nand(mtd);
173 return readw(chip->IO_ADDR_R);
177 * nand_select_chip - [DEFAULT] control CE line
178 * @mtd: MTD device structure
179 * @chipnr: chipnumber to select, -1 for deselect
181 * Default select function for 1 chip devices.
183 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
185 struct nand_chip *chip = mtd_to_nand(mtd);
189 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
200 * nand_write_byte - [DEFAULT] write single byte to chip
201 * @mtd: MTD device structure
202 * @byte: value to write
204 * Default function to write a byte to I/O[7:0]
206 static void nand_write_byte(struct mtd_info *mtd, uint8_t byte)
208 struct nand_chip *chip = mtd_to_nand(mtd);
210 chip->write_buf(mtd, &byte, 1);
214 * nand_write_byte16 - [DEFAULT] write single byte to a chip with width 16
215 * @mtd: MTD device structure
216 * @byte: value to write
218 * Default function to write a byte to I/O[7:0] on a 16-bit wide chip.
220 static void nand_write_byte16(struct mtd_info *mtd, uint8_t byte)
222 struct nand_chip *chip = mtd_to_nand(mtd);
223 uint16_t word = byte;
226 * It's not entirely clear what should happen to I/O[15:8] when writing
227 * a byte. The ONFi spec (Revision 3.1; 2012-09-19, Section 2.16) reads:
229 * When the host supports a 16-bit bus width, only data is
230 * transferred at the 16-bit width. All address and command line
231 * transfers shall use only the lower 8-bits of the data bus. During
232 * command transfers, the host may place any value on the upper
233 * 8-bits of the data bus. During address transfers, the host shall
234 * set the upper 8-bits of the data bus to 00h.
236 * One user of the write_byte callback is nand_onfi_set_features. The
237 * four parameters are specified to be written to I/O[7:0], but this is
238 * neither an address nor a command transfer. Let's assume a 0 on the
239 * upper I/O lines is OK.
241 chip->write_buf(mtd, (uint8_t *)&word, 2);
244 static void iowrite8_rep(void *addr, const uint8_t *buf, int len)
248 for (i = 0; i < len; i++)
249 writeb(buf[i], addr);
251 static void ioread8_rep(void *addr, uint8_t *buf, int len)
255 for (i = 0; i < len; i++)
256 buf[i] = readb(addr);
259 static void ioread16_rep(void *addr, void *buf, int len)
262 u16 *p = (u16 *) buf;
264 for (i = 0; i < len; i++)
268 static void iowrite16_rep(void *addr, void *buf, int len)
271 u16 *p = (u16 *) buf;
273 for (i = 0; i < len; i++)
278 * nand_write_buf - [DEFAULT] write buffer to chip
279 * @mtd: MTD device structure
281 * @len: number of bytes to write
283 * Default write function for 8bit buswidth.
285 void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
287 struct nand_chip *chip = mtd_to_nand(mtd);
289 iowrite8_rep(chip->IO_ADDR_W, buf, len);
293 * nand_read_buf - [DEFAULT] read chip data into buffer
294 * @mtd: MTD device structure
295 * @buf: buffer to store date
296 * @len: number of bytes to read
298 * Default read function for 8bit buswidth.
300 void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
302 struct nand_chip *chip = mtd_to_nand(mtd);
304 ioread8_rep(chip->IO_ADDR_R, buf, len);
308 * nand_write_buf16 - [DEFAULT] write buffer to chip
309 * @mtd: MTD device structure
311 * @len: number of bytes to write
313 * Default write function for 16bit buswidth.
315 void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
317 struct nand_chip *chip = mtd_to_nand(mtd);
318 u16 *p = (u16 *) buf;
320 iowrite16_rep(chip->IO_ADDR_W, p, len >> 1);
324 * nand_read_buf16 - [DEFAULT] read chip data into buffer
325 * @mtd: MTD device structure
326 * @buf: buffer to store date
327 * @len: number of bytes to read
329 * Default read function for 16bit buswidth.
331 void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
333 struct nand_chip *chip = mtd_to_nand(mtd);
334 u16 *p = (u16 *) buf;
336 ioread16_rep(chip->IO_ADDR_R, p, len >> 1);
340 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
341 * @mtd: MTD device structure
342 * @ofs: offset from device start
344 * Check, if the block is bad.
346 static int nand_block_bad(struct mtd_info *mtd, loff_t ofs)
348 int page, res = 0, i = 0;
349 struct nand_chip *chip = mtd_to_nand(mtd);
352 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
353 ofs += mtd->erasesize - mtd->writesize;
355 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
358 if (chip->options & NAND_BUSWIDTH_16) {
359 chip->cmdfunc(mtd, NAND_CMD_READOOB,
360 chip->badblockpos & 0xFE, page);
361 bad = cpu_to_le16(chip->read_word(mtd));
362 if (chip->badblockpos & 0x1)
367 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos,
369 bad = chip->read_byte(mtd);
372 if (likely(chip->badblockbits == 8))
375 res = hweight8(bad) < chip->badblockbits;
376 ofs += mtd->writesize;
377 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
379 } while (!res && i < 2 && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE));
385 * nand_default_block_markbad - [DEFAULT] mark a block bad via bad block marker
386 * @mtd: MTD device structure
387 * @ofs: offset from device start
389 * This is the default implementation, which can be overridden by a hardware
390 * specific driver. It provides the details for writing a bad block marker to a
393 static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
395 struct nand_chip *chip = mtd_to_nand(mtd);
396 struct mtd_oob_ops ops;
397 uint8_t buf[2] = { 0, 0 };
398 int ret = 0, res, i = 0;
400 memset(&ops, 0, sizeof(ops));
402 ops.ooboffs = chip->badblockpos;
403 if (chip->options & NAND_BUSWIDTH_16) {
404 ops.ooboffs &= ~0x01;
405 ops.len = ops.ooblen = 2;
407 ops.len = ops.ooblen = 1;
409 ops.mode = MTD_OPS_PLACE_OOB;
411 /* Write to first/last page(s) if necessary */
412 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
413 ofs += mtd->erasesize - mtd->writesize;
415 res = nand_do_write_oob(mtd, ofs, &ops);
420 ofs += mtd->writesize;
421 } while ((chip->bbt_options & NAND_BBT_SCAN2NDPAGE) && i < 2);
427 * nand_block_markbad_lowlevel - mark a block bad
428 * @mtd: MTD device structure
429 * @ofs: offset from device start
431 * This function performs the generic NAND bad block marking steps (i.e., bad
432 * block table(s) and/or marker(s)). We only allow the hardware driver to
433 * specify how to write bad block markers to OOB (chip->block_markbad).
435 * We try operations in the following order:
436 * (1) erase the affected block, to allow OOB marker to be written cleanly
437 * (2) write bad block marker to OOB area of affected block (unless flag
438 * NAND_BBT_NO_OOB_BBM is present)
440 * Note that we retain the first error encountered in (2) or (3), finish the
441 * procedures, and dump the error in the end.
443 static int nand_block_markbad_lowlevel(struct mtd_info *mtd, loff_t ofs)
445 struct nand_chip *chip = mtd_to_nand(mtd);
448 if (!(chip->bbt_options & NAND_BBT_NO_OOB_BBM)) {
449 struct erase_info einfo;
451 /* Attempt erase before marking OOB */
452 memset(&einfo, 0, sizeof(einfo));
455 einfo.len = 1ULL << chip->phys_erase_shift;
456 nand_erase_nand(mtd, &einfo, 0);
458 /* Write bad block marker to OOB */
459 nand_get_device(mtd, FL_WRITING);
460 ret = chip->block_markbad(mtd, ofs);
461 nand_release_device(mtd);
464 /* Mark block bad in BBT */
466 res = nand_markbad_bbt(mtd, ofs);
472 mtd->ecc_stats.badblocks++;
478 * nand_check_wp - [GENERIC] check if the chip is write protected
479 * @mtd: MTD device structure
481 * Check, if the device is write protected. The function expects, that the
482 * device is already selected.
484 static int nand_check_wp(struct mtd_info *mtd)
486 struct nand_chip *chip = mtd_to_nand(mtd);
488 /* Broken xD cards report WP despite being writable */
489 if (chip->options & NAND_BROKEN_XD)
492 /* Check the WP bit */
493 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
494 return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
498 * nand_block_isreserved - [GENERIC] Check if a block is marked reserved.
499 * @mtd: MTD device structure
500 * @ofs: offset from device start
502 * Check if the block is marked as reserved.
504 static int nand_block_isreserved(struct mtd_info *mtd, loff_t ofs)
506 struct nand_chip *chip = mtd_to_nand(mtd);
510 /* Return info from the table */
511 return nand_isreserved_bbt(mtd, ofs);
515 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
516 * @mtd: MTD device structure
517 * @ofs: offset from device start
518 * @allowbbt: 1, if its allowed to access the bbt area
520 * Check, if the block is bad. Either by reading the bad block table or
521 * calling of the scan function.
523 static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int allowbbt)
525 struct nand_chip *chip = mtd_to_nand(mtd);
527 if (!(chip->options & NAND_SKIP_BBTSCAN) &&
528 !(chip->options & NAND_BBT_SCANNED)) {
529 chip->options |= NAND_BBT_SCANNED;
534 return chip->block_bad(mtd, ofs);
536 /* Return info from the table */
537 return nand_isbad_bbt(mtd, ofs, allowbbt);
541 * nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
542 * @mtd: MTD device structure
544 * Wait for the ready pin after a command, and warn if a timeout occurs.
546 void nand_wait_ready(struct mtd_info *mtd)
548 struct nand_chip *chip = mtd_to_nand(mtd);
549 u32 timeo = (CONFIG_SYS_HZ * 400) / 1000;
552 time_start = get_timer(0);
553 /* Wait until command is processed or timeout occurs */
554 while (get_timer(time_start) < timeo) {
556 if (chip->dev_ready(mtd))
560 if (!chip->dev_ready(mtd))
561 pr_warn("timeout while waiting for chip to become ready\n");
563 EXPORT_SYMBOL_GPL(nand_wait_ready);
566 * nand_wait_status_ready - [GENERIC] Wait for the ready status after commands.
567 * @mtd: MTD device structure
568 * @timeo: Timeout in ms
570 * Wait for status ready (i.e. command done) or timeout.
572 static void nand_wait_status_ready(struct mtd_info *mtd, unsigned long timeo)
574 register struct nand_chip *chip = mtd_to_nand(mtd);
577 timeo = (CONFIG_SYS_HZ * timeo) / 1000;
578 time_start = get_timer(0);
579 while (get_timer(time_start) < timeo) {
580 if ((chip->read_byte(mtd) & NAND_STATUS_READY))
587 * nand_command - [DEFAULT] Send command to NAND device
588 * @mtd: MTD device structure
589 * @command: the command to be sent
590 * @column: the column address for this command, -1 if none
591 * @page_addr: the page address for this command, -1 if none
593 * Send command to NAND device. This function is used for small page devices
594 * (512 Bytes per page).
596 static void nand_command(struct mtd_info *mtd, unsigned int command,
597 int column, int page_addr)
599 register struct nand_chip *chip = mtd_to_nand(mtd);
600 int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
602 /* Write out the command to the device */
603 if (command == NAND_CMD_SEQIN) {
606 if (column >= mtd->writesize) {
608 column -= mtd->writesize;
609 readcmd = NAND_CMD_READOOB;
610 } else if (column < 256) {
611 /* First 256 bytes --> READ0 */
612 readcmd = NAND_CMD_READ0;
615 readcmd = NAND_CMD_READ1;
617 chip->cmd_ctrl(mtd, readcmd, ctrl);
618 ctrl &= ~NAND_CTRL_CHANGE;
620 chip->cmd_ctrl(mtd, command, ctrl);
622 /* Address cycle, when necessary */
623 ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
624 /* Serially input address */
626 /* Adjust columns for 16 bit buswidth */
627 if (chip->options & NAND_BUSWIDTH_16 &&
628 !nand_opcode_8bits(command))
630 chip->cmd_ctrl(mtd, column, ctrl);
631 ctrl &= ~NAND_CTRL_CHANGE;
633 if (page_addr != -1) {
634 chip->cmd_ctrl(mtd, page_addr, ctrl);
635 ctrl &= ~NAND_CTRL_CHANGE;
636 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
637 if (chip->options & NAND_ROW_ADDR_3)
638 chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
640 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
643 * Program and erase have their own busy handlers status and sequential
648 case NAND_CMD_PAGEPROG:
649 case NAND_CMD_ERASE1:
650 case NAND_CMD_ERASE2:
652 case NAND_CMD_STATUS:
653 case NAND_CMD_READID:
654 case NAND_CMD_SET_FEATURES:
660 udelay(chip->chip_delay);
661 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
662 NAND_CTRL_CLE | NAND_CTRL_CHANGE);
664 NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
665 /* EZ-NAND can take upto 250ms as per ONFi v4.0 */
666 nand_wait_status_ready(mtd, 250);
669 /* This applies to read commands */
672 * If we don't have access to the busy pin, we apply the given
675 if (!chip->dev_ready) {
676 udelay(chip->chip_delay);
681 * Apply this short delay always to ensure that we do wait tWB in
682 * any case on any machine.
686 nand_wait_ready(mtd);
690 * nand_command_lp - [DEFAULT] Send command to NAND large page device
691 * @mtd: MTD device structure
692 * @command: the command to be sent
693 * @column: the column address for this command, -1 if none
694 * @page_addr: the page address for this command, -1 if none
696 * Send command to NAND device. This is the version for the new large page
697 * devices. We don't have the separate regions as we have in the small page
698 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
700 static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
701 int column, int page_addr)
703 register struct nand_chip *chip = mtd_to_nand(mtd);
705 /* Emulate NAND_CMD_READOOB */
706 if (command == NAND_CMD_READOOB) {
707 column += mtd->writesize;
708 command = NAND_CMD_READ0;
711 /* Command latch cycle */
712 chip->cmd_ctrl(mtd, command, NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
714 if (column != -1 || page_addr != -1) {
715 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
717 /* Serially input address */
719 /* Adjust columns for 16 bit buswidth */
720 if (chip->options & NAND_BUSWIDTH_16 &&
721 !nand_opcode_8bits(command))
723 chip->cmd_ctrl(mtd, column, ctrl);
724 ctrl &= ~NAND_CTRL_CHANGE;
725 chip->cmd_ctrl(mtd, column >> 8, ctrl);
727 if (page_addr != -1) {
728 chip->cmd_ctrl(mtd, page_addr, ctrl);
729 chip->cmd_ctrl(mtd, page_addr >> 8,
730 NAND_NCE | NAND_ALE);
731 if (chip->options & NAND_ROW_ADDR_3)
732 chip->cmd_ctrl(mtd, page_addr >> 16,
733 NAND_NCE | NAND_ALE);
736 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
739 * Program and erase have their own busy handlers status, sequential
740 * in and status need no delay.
744 case NAND_CMD_CACHEDPROG:
745 case NAND_CMD_PAGEPROG:
746 case NAND_CMD_ERASE1:
747 case NAND_CMD_ERASE2:
750 case NAND_CMD_STATUS:
751 case NAND_CMD_READID:
752 case NAND_CMD_SET_FEATURES:
758 udelay(chip->chip_delay);
759 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
760 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
761 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
762 NAND_NCE | NAND_CTRL_CHANGE);
763 /* EZ-NAND can take upto 250ms as per ONFi v4.0 */
764 nand_wait_status_ready(mtd, 250);
767 case NAND_CMD_RNDOUT:
768 /* No ready / busy check necessary */
769 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
770 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
771 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
772 NAND_NCE | NAND_CTRL_CHANGE);
776 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
777 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
778 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
779 NAND_NCE | NAND_CTRL_CHANGE);
781 /* This applies to read commands */
784 * If we don't have access to the busy pin, we apply the given
787 if (!chip->dev_ready) {
788 udelay(chip->chip_delay);
794 * Apply this short delay always to ensure that we do wait tWB in
795 * any case on any machine.
799 nand_wait_ready(mtd);
803 * panic_nand_get_device - [GENERIC] Get chip for selected access
804 * @chip: the nand chip descriptor
805 * @mtd: MTD device structure
806 * @new_state: the state which is requested
808 * Used when in panic, no locks are taken.
810 static void panic_nand_get_device(struct nand_chip *chip,
811 struct mtd_info *mtd, int new_state)
813 /* Hardware controller shared among independent devices */
814 chip->controller->active = chip;
815 chip->state = new_state;
819 * nand_get_device - [GENERIC] Get chip for selected access
820 * @mtd: MTD device structure
821 * @new_state: the state which is requested
823 * Get the device and lock it for exclusive access
826 nand_get_device(struct mtd_info *mtd, int new_state)
828 struct nand_chip *chip = mtd_to_nand(mtd);
829 chip->state = new_state;
834 * panic_nand_wait - [GENERIC] wait until the command is done
835 * @mtd: MTD device structure
836 * @chip: NAND chip structure
839 * Wait for command done. This is a helper function for nand_wait used when
840 * we are in interrupt context. May happen when in panic and trying to write
841 * an oops through mtdoops.
843 static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip,
847 for (i = 0; i < timeo; i++) {
848 if (chip->dev_ready) {
849 if (chip->dev_ready(mtd))
852 if (chip->read_byte(mtd) & NAND_STATUS_READY)
860 * nand_wait - [DEFAULT] wait until the command is done
861 * @mtd: MTD device structure
862 * @chip: NAND chip structure
864 * Wait for command done. This applies to erase and program only.
866 static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
869 unsigned long timeo = 400;
871 led_trigger_event(nand_led_trigger, LED_FULL);
874 * Apply this short delay always to ensure that we do wait tWB in any
875 * case on any machine.
879 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
881 u32 timer = (CONFIG_SYS_HZ * timeo) / 1000;
884 time_start = get_timer(0);
885 while (get_timer(time_start) < timer) {
886 if (chip->dev_ready) {
887 if (chip->dev_ready(mtd))
890 if (chip->read_byte(mtd) & NAND_STATUS_READY)
894 led_trigger_event(nand_led_trigger, LED_OFF);
896 status = (int)chip->read_byte(mtd);
897 /* This can happen if in case of timeout or buggy dev_ready */
898 WARN_ON(!(status & NAND_STATUS_READY));
903 * nand_reset_data_interface - Reset data interface and timings
904 * @chip: The NAND chip
905 * @chipnr: Internal die id
907 * Reset the Data interface and timings to ONFI mode 0.
909 * Returns 0 for success or negative error code otherwise.
911 static int nand_reset_data_interface(struct nand_chip *chip, int chipnr)
913 struct mtd_info *mtd = nand_to_mtd(chip);
914 const struct nand_data_interface *conf;
917 if (!chip->setup_data_interface)
921 * The ONFI specification says:
923 * To transition from NV-DDR or NV-DDR2 to the SDR data
924 * interface, the host shall use the Reset (FFh) command
925 * using SDR timing mode 0. A device in any timing mode is
926 * required to recognize Reset (FFh) command issued in SDR
930 * Configure the data interface in SDR mode and set the
931 * timings to timing mode 0.
934 conf = nand_get_default_data_interface();
935 ret = chip->setup_data_interface(mtd, chipnr, conf);
937 pr_err("Failed to configure data interface to SDR timing mode 0\n");
943 * nand_setup_data_interface - Setup the best data interface and timings
944 * @chip: The NAND chip
945 * @chipnr: Internal die id
947 * Find and configure the best data interface and NAND timings supported by
948 * the chip and the driver.
949 * First tries to retrieve supported timing modes from ONFI information,
950 * and if the NAND chip does not support ONFI, relies on the
951 * ->onfi_timing_mode_default specified in the nand_ids table.
953 * Returns 0 for success or negative error code otherwise.
955 static int nand_setup_data_interface(struct nand_chip *chip, int chipnr)
957 struct mtd_info *mtd = nand_to_mtd(chip);
960 if (!chip->setup_data_interface || !chip->data_interface)
964 * Ensure the timing mode has been changed on the chip side
965 * before changing timings on the controller side.
967 if (chip->onfi_version) {
968 u8 tmode_param[ONFI_SUBFEATURE_PARAM_LEN] = {
969 chip->onfi_timing_mode_default,
972 ret = chip->onfi_set_features(mtd, chip,
973 ONFI_FEATURE_ADDR_TIMING_MODE,
979 ret = chip->setup_data_interface(mtd, chipnr, chip->data_interface);
985 * nand_init_data_interface - find the best data interface and timings
986 * @chip: The NAND chip
988 * Find the best data interface and NAND timings supported by the chip
990 * First tries to retrieve supported timing modes from ONFI information,
991 * and if the NAND chip does not support ONFI, relies on the
992 * ->onfi_timing_mode_default specified in the nand_ids table. After this
993 * function nand_chip->data_interface is initialized with the best timing mode
996 * Returns 0 for success or negative error code otherwise.
998 static int nand_init_data_interface(struct nand_chip *chip)
1000 struct mtd_info *mtd = nand_to_mtd(chip);
1001 int modes, mode, ret;
1003 if (!chip->setup_data_interface)
1007 * First try to identify the best timings from ONFI parameters and
1008 * if the NAND does not support ONFI, fallback to the default ONFI
1011 modes = onfi_get_async_timing_mode(chip);
1012 if (modes == ONFI_TIMING_MODE_UNKNOWN) {
1013 if (!chip->onfi_timing_mode_default)
1016 modes = GENMASK(chip->onfi_timing_mode_default, 0);
1019 chip->data_interface = kzalloc(sizeof(*chip->data_interface),
1021 if (!chip->data_interface)
1024 for (mode = fls(modes) - 1; mode >= 0; mode--) {
1025 ret = onfi_init_data_interface(chip, chip->data_interface,
1026 NAND_SDR_IFACE, mode);
1030 /* Pass -1 to only */
1031 ret = chip->setup_data_interface(mtd,
1032 NAND_DATA_IFACE_CHECK_ONLY,
1033 chip->data_interface);
1035 chip->onfi_timing_mode_default = mode;
1043 static void __maybe_unused nand_release_data_interface(struct nand_chip *chip)
1045 kfree(chip->data_interface);
1049 * nand_reset - Reset and initialize a NAND device
1050 * @chip: The NAND chip
1051 * @chipnr: Internal die id
1053 * Returns 0 for success or negative error code otherwise
1055 int nand_reset(struct nand_chip *chip, int chipnr)
1057 struct mtd_info *mtd = nand_to_mtd(chip);
1060 ret = nand_reset_data_interface(chip, chipnr);
1065 * The CS line has to be released before we can apply the new NAND
1066 * interface settings, hence this weird ->select_chip() dance.
1068 chip->select_chip(mtd, chipnr);
1069 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1070 chip->select_chip(mtd, -1);
1072 chip->select_chip(mtd, chipnr);
1073 ret = nand_setup_data_interface(chip, chipnr);
1074 chip->select_chip(mtd, -1);
1082 * nand_check_erased_buf - check if a buffer contains (almost) only 0xff data
1083 * @buf: buffer to test
1084 * @len: buffer length
1085 * @bitflips_threshold: maximum number of bitflips
1087 * Check if a buffer contains only 0xff, which means the underlying region
1088 * has been erased and is ready to be programmed.
1089 * The bitflips_threshold specify the maximum number of bitflips before
1090 * considering the region is not erased.
1091 * Note: The logic of this function has been extracted from the memweight
1092 * implementation, except that nand_check_erased_buf function exit before
1093 * testing the whole buffer if the number of bitflips exceed the
1094 * bitflips_threshold value.
1096 * Returns a positive number of bitflips less than or equal to
1097 * bitflips_threshold, or -ERROR_CODE for bitflips in excess of the
1100 static int nand_check_erased_buf(void *buf, int len, int bitflips_threshold)
1102 const unsigned char *bitmap = buf;
1106 for (; len && ((uintptr_t)bitmap) % sizeof(long);
1108 weight = hweight8(*bitmap);
1109 bitflips += BITS_PER_BYTE - weight;
1110 if (unlikely(bitflips > bitflips_threshold))
1114 for (; len >= 4; len -= 4, bitmap += 4) {
1115 weight = hweight32(*((u32 *)bitmap));
1116 bitflips += 32 - weight;
1117 if (unlikely(bitflips > bitflips_threshold))
1121 for (; len > 0; len--, bitmap++) {
1122 weight = hweight8(*bitmap);
1123 bitflips += BITS_PER_BYTE - weight;
1124 if (unlikely(bitflips > bitflips_threshold))
1132 * nand_check_erased_ecc_chunk - check if an ECC chunk contains (almost) only
1134 * @data: data buffer to test
1135 * @datalen: data length
1137 * @ecclen: ECC length
1138 * @extraoob: extra OOB buffer
1139 * @extraooblen: extra OOB length
1140 * @bitflips_threshold: maximum number of bitflips
1142 * Check if a data buffer and its associated ECC and OOB data contains only
1143 * 0xff pattern, which means the underlying region has been erased and is
1144 * ready to be programmed.
1145 * The bitflips_threshold specify the maximum number of bitflips before
1146 * considering the region as not erased.
1149 * 1/ ECC algorithms are working on pre-defined block sizes which are usually
1150 * different from the NAND page size. When fixing bitflips, ECC engines will
1151 * report the number of errors per chunk, and the NAND core infrastructure
1152 * expect you to return the maximum number of bitflips for the whole page.
1153 * This is why you should always use this function on a single chunk and
1154 * not on the whole page. After checking each chunk you should update your
1155 * max_bitflips value accordingly.
1156 * 2/ When checking for bitflips in erased pages you should not only check
1157 * the payload data but also their associated ECC data, because a user might
1158 * have programmed almost all bits to 1 but a few. In this case, we
1159 * shouldn't consider the chunk as erased, and checking ECC bytes prevent
1161 * 3/ The extraoob argument is optional, and should be used if some of your OOB
1162 * data are protected by the ECC engine.
1163 * It could also be used if you support subpages and want to attach some
1164 * extra OOB data to an ECC chunk.
1166 * Returns a positive number of bitflips less than or equal to
1167 * bitflips_threshold, or -ERROR_CODE for bitflips in excess of the
1168 * threshold. In case of success, the passed buffers are filled with 0xff.
1170 int nand_check_erased_ecc_chunk(void *data, int datalen,
1171 void *ecc, int ecclen,
1172 void *extraoob, int extraooblen,
1173 int bitflips_threshold)
1175 int data_bitflips = 0, ecc_bitflips = 0, extraoob_bitflips = 0;
1177 data_bitflips = nand_check_erased_buf(data, datalen,
1178 bitflips_threshold);
1179 if (data_bitflips < 0)
1180 return data_bitflips;
1182 bitflips_threshold -= data_bitflips;
1184 ecc_bitflips = nand_check_erased_buf(ecc, ecclen, bitflips_threshold);
1185 if (ecc_bitflips < 0)
1186 return ecc_bitflips;
1188 bitflips_threshold -= ecc_bitflips;
1190 extraoob_bitflips = nand_check_erased_buf(extraoob, extraooblen,
1191 bitflips_threshold);
1192 if (extraoob_bitflips < 0)
1193 return extraoob_bitflips;
1196 memset(data, 0xff, datalen);
1199 memset(ecc, 0xff, ecclen);
1201 if (extraoob_bitflips)
1202 memset(extraoob, 0xff, extraooblen);
1204 return data_bitflips + ecc_bitflips + extraoob_bitflips;
1206 EXPORT_SYMBOL(nand_check_erased_ecc_chunk);
1209 * nand_read_page_raw - [INTERN] read raw page data without ecc
1210 * @mtd: mtd info structure
1211 * @chip: nand chip info structure
1212 * @buf: buffer to store read data
1213 * @oob_required: caller requires OOB data read to chip->oob_poi
1214 * @page: page number to read
1216 * Not for syndrome calculating ECC controllers, which use a special oob layout.
1218 static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1219 uint8_t *buf, int oob_required, int page)
1221 chip->read_buf(mtd, buf, mtd->writesize);
1223 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1228 * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc
1229 * @mtd: mtd info structure
1230 * @chip: nand chip info structure
1231 * @buf: buffer to store read data
1232 * @oob_required: caller requires OOB data read to chip->oob_poi
1233 * @page: page number to read
1235 * We need a special oob layout and handling even when OOB isn't used.
1237 static int nand_read_page_raw_syndrome(struct mtd_info *mtd,
1238 struct nand_chip *chip, uint8_t *buf,
1239 int oob_required, int page)
1241 int eccsize = chip->ecc.size;
1242 int eccbytes = chip->ecc.bytes;
1243 uint8_t *oob = chip->oob_poi;
1246 for (steps = chip->ecc.steps; steps > 0; steps--) {
1247 chip->read_buf(mtd, buf, eccsize);
1250 if (chip->ecc.prepad) {
1251 chip->read_buf(mtd, oob, chip->ecc.prepad);
1252 oob += chip->ecc.prepad;
1255 chip->read_buf(mtd, oob, eccbytes);
1258 if (chip->ecc.postpad) {
1259 chip->read_buf(mtd, oob, chip->ecc.postpad);
1260 oob += chip->ecc.postpad;
1264 size = mtd->oobsize - (oob - chip->oob_poi);
1266 chip->read_buf(mtd, oob, size);
1272 * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function
1273 * @mtd: mtd info structure
1274 * @chip: nand chip info structure
1275 * @buf: buffer to store read data
1276 * @oob_required: caller requires OOB data read to chip->oob_poi
1277 * @page: page number to read
1279 static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1280 uint8_t *buf, int oob_required, int page)
1282 int i, eccsize = chip->ecc.size;
1283 int eccbytes = chip->ecc.bytes;
1284 int eccsteps = chip->ecc.steps;
1286 uint8_t *ecc_calc = chip->buffers->ecccalc;
1287 uint8_t *ecc_code = chip->buffers->ecccode;
1288 uint32_t *eccpos = chip->ecc.layout->eccpos;
1289 unsigned int max_bitflips = 0;
1291 chip->ecc.read_page_raw(mtd, chip, buf, 1, page);
1293 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1294 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1296 for (i = 0; i < chip->ecc.total; i++)
1297 ecc_code[i] = chip->oob_poi[eccpos[i]];
1299 eccsteps = chip->ecc.steps;
1302 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1305 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1307 mtd->ecc_stats.failed++;
1309 mtd->ecc_stats.corrected += stat;
1310 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1313 return max_bitflips;
1317 * nand_read_subpage - [REPLACEABLE] ECC based sub-page read function
1318 * @mtd: mtd info structure
1319 * @chip: nand chip info structure
1320 * @data_offs: offset of requested data within the page
1321 * @readlen: data length
1322 * @bufpoi: buffer to store read data
1323 * @page: page number to read
1325 static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
1326 uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi,
1329 int start_step, end_step, num_steps;
1330 uint32_t *eccpos = chip->ecc.layout->eccpos;
1332 int data_col_addr, i, gaps = 0;
1333 int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
1334 int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
1336 unsigned int max_bitflips = 0;
1338 /* Column address within the page aligned to ECC size (256bytes) */
1339 start_step = data_offs / chip->ecc.size;
1340 end_step = (data_offs + readlen - 1) / chip->ecc.size;
1341 num_steps = end_step - start_step + 1;
1342 index = start_step * chip->ecc.bytes;
1344 /* Data size aligned to ECC ecc.size */
1345 datafrag_len = num_steps * chip->ecc.size;
1346 eccfrag_len = num_steps * chip->ecc.bytes;
1348 data_col_addr = start_step * chip->ecc.size;
1349 /* If we read not a page aligned data */
1350 if (data_col_addr != 0)
1351 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
1353 p = bufpoi + data_col_addr;
1354 chip->read_buf(mtd, p, datafrag_len);
1357 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
1358 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
1361 * The performance is faster if we position offsets according to
1362 * ecc.pos. Let's make sure that there are no gaps in ECC positions.
1364 for (i = 0; i < eccfrag_len - 1; i++) {
1365 if (eccpos[i + index] + 1 != eccpos[i + index + 1]) {
1371 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1372 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1375 * Send the command to read the particular ECC bytes take care
1376 * about buswidth alignment in read_buf.
1378 aligned_pos = eccpos[index] & ~(busw - 1);
1379 aligned_len = eccfrag_len;
1380 if (eccpos[index] & (busw - 1))
1382 if (eccpos[index + (num_steps * chip->ecc.bytes)] & (busw - 1))
1385 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
1386 mtd->writesize + aligned_pos, -1);
1387 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
1390 for (i = 0; i < eccfrag_len; i++)
1391 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + index]];
1393 p = bufpoi + data_col_addr;
1394 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
1397 stat = chip->ecc.correct(mtd, p,
1398 &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
1399 if (stat == -EBADMSG &&
1400 (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {
1401 /* check for empty pages with bitflips */
1402 stat = nand_check_erased_ecc_chunk(p, chip->ecc.size,
1403 &chip->buffers->ecccode[i],
1406 chip->ecc.strength);
1410 mtd->ecc_stats.failed++;
1412 mtd->ecc_stats.corrected += stat;
1413 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1416 return max_bitflips;
1420 * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function
1421 * @mtd: mtd info structure
1422 * @chip: nand chip info structure
1423 * @buf: buffer to store read data
1424 * @oob_required: caller requires OOB data read to chip->oob_poi
1425 * @page: page number to read
1427 * Not for syndrome calculating ECC controllers which need a special oob layout.
1429 static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1430 uint8_t *buf, int oob_required, int page)
1432 int i, eccsize = chip->ecc.size;
1433 int eccbytes = chip->ecc.bytes;
1434 int eccsteps = chip->ecc.steps;
1436 uint8_t *ecc_calc = chip->buffers->ecccalc;
1437 uint8_t *ecc_code = chip->buffers->ecccode;
1438 uint32_t *eccpos = chip->ecc.layout->eccpos;
1439 unsigned int max_bitflips = 0;
1441 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1442 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1443 chip->read_buf(mtd, p, eccsize);
1444 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1446 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1448 for (i = 0; i < chip->ecc.total; i++)
1449 ecc_code[i] = chip->oob_poi[eccpos[i]];
1451 eccsteps = chip->ecc.steps;
1454 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1457 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1458 if (stat == -EBADMSG &&
1459 (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {
1460 /* check for empty pages with bitflips */
1461 stat = nand_check_erased_ecc_chunk(p, eccsize,
1462 &ecc_code[i], eccbytes,
1464 chip->ecc.strength);
1468 mtd->ecc_stats.failed++;
1470 mtd->ecc_stats.corrected += stat;
1471 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1474 return max_bitflips;
1478 * nand_read_page_hwecc_oob_first - [REPLACEABLE] hw ecc, read oob first
1479 * @mtd: mtd info structure
1480 * @chip: nand chip info structure
1481 * @buf: buffer to store read data
1482 * @oob_required: caller requires OOB data read to chip->oob_poi
1483 * @page: page number to read
1485 * Hardware ECC for large page chips, require OOB to be read first. For this
1486 * ECC mode, the write_page method is re-used from ECC_HW. These methods
1487 * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with
1488 * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from
1489 * the data area, by overwriting the NAND manufacturer bad block markings.
1491 static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
1492 struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
1494 int i, eccsize = chip->ecc.size;
1495 int eccbytes = chip->ecc.bytes;
1496 int eccsteps = chip->ecc.steps;
1498 uint8_t *ecc_code = chip->buffers->ecccode;
1499 uint32_t *eccpos = chip->ecc.layout->eccpos;
1500 uint8_t *ecc_calc = chip->buffers->ecccalc;
1501 unsigned int max_bitflips = 0;
1503 /* Read the OOB area first */
1504 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1505 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1506 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1508 for (i = 0; i < chip->ecc.total; i++)
1509 ecc_code[i] = chip->oob_poi[eccpos[i]];
1511 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1514 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1515 chip->read_buf(mtd, p, eccsize);
1516 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1518 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
1519 if (stat == -EBADMSG &&
1520 (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {
1521 /* check for empty pages with bitflips */
1522 stat = nand_check_erased_ecc_chunk(p, eccsize,
1523 &ecc_code[i], eccbytes,
1525 chip->ecc.strength);
1529 mtd->ecc_stats.failed++;
1531 mtd->ecc_stats.corrected += stat;
1532 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1535 return max_bitflips;
1539 * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read
1540 * @mtd: mtd info structure
1541 * @chip: nand chip info structure
1542 * @buf: buffer to store read data
1543 * @oob_required: caller requires OOB data read to chip->oob_poi
1544 * @page: page number to read
1546 * The hw generator calculates the error syndrome automatically. Therefore we
1547 * need a special oob layout and handling.
1549 static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1550 uint8_t *buf, int oob_required, int page)
1552 int i, eccsize = chip->ecc.size;
1553 int eccbytes = chip->ecc.bytes;
1554 int eccsteps = chip->ecc.steps;
1555 int eccpadbytes = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
1557 uint8_t *oob = chip->oob_poi;
1558 unsigned int max_bitflips = 0;
1560 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1563 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1564 chip->read_buf(mtd, p, eccsize);
1566 if (chip->ecc.prepad) {
1567 chip->read_buf(mtd, oob, chip->ecc.prepad);
1568 oob += chip->ecc.prepad;
1571 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
1572 chip->read_buf(mtd, oob, eccbytes);
1573 stat = chip->ecc.correct(mtd, p, oob, NULL);
1577 if (chip->ecc.postpad) {
1578 chip->read_buf(mtd, oob, chip->ecc.postpad);
1579 oob += chip->ecc.postpad;
1582 if (stat == -EBADMSG &&
1583 (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {
1584 /* check for empty pages with bitflips */
1585 stat = nand_check_erased_ecc_chunk(p, chip->ecc.size,
1589 chip->ecc.strength);
1593 mtd->ecc_stats.failed++;
1595 mtd->ecc_stats.corrected += stat;
1596 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1600 /* Calculate remaining oob bytes */
1601 i = mtd->oobsize - (oob - chip->oob_poi);
1603 chip->read_buf(mtd, oob, i);
1605 return max_bitflips;
1609 * nand_transfer_oob - [INTERN] Transfer oob to client buffer
1610 * @chip: nand chip structure
1611 * @oob: oob destination address
1612 * @ops: oob ops structure
1613 * @len: size of oob to transfer
1615 static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
1616 struct mtd_oob_ops *ops, size_t len)
1618 switch (ops->mode) {
1620 case MTD_OPS_PLACE_OOB:
1622 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1625 case MTD_OPS_AUTO_OOB: {
1626 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1627 uint32_t boffs = 0, roffs = ops->ooboffs;
1630 for (; free->length && len; free++, len -= bytes) {
1631 /* Read request not from offset 0? */
1632 if (unlikely(roffs)) {
1633 if (roffs >= free->length) {
1634 roffs -= free->length;
1637 boffs = free->offset + roffs;
1638 bytes = min_t(size_t, len,
1639 (free->length - roffs));
1642 bytes = min_t(size_t, len, free->length);
1643 boffs = free->offset;
1645 memcpy(oob, chip->oob_poi + boffs, bytes);
1657 * nand_setup_read_retry - [INTERN] Set the READ RETRY mode
1658 * @mtd: MTD device structure
1659 * @retry_mode: the retry mode to use
1661 * Some vendors supply a special command to shift the Vt threshold, to be used
1662 * when there are too many bitflips in a page (i.e., ECC error). After setting
1663 * a new threshold, the host should retry reading the page.
1665 static int nand_setup_read_retry(struct mtd_info *mtd, int retry_mode)
1667 struct nand_chip *chip = mtd_to_nand(mtd);
1669 pr_debug("setting READ RETRY mode %d\n", retry_mode);
1671 if (retry_mode >= chip->read_retries)
1674 if (!chip->setup_read_retry)
1677 return chip->setup_read_retry(mtd, retry_mode);
1681 * nand_do_read_ops - [INTERN] Read data with ECC
1682 * @mtd: MTD device structure
1683 * @from: offset to read from
1684 * @ops: oob ops structure
1686 * Internal function. Called with chip held.
1688 static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1689 struct mtd_oob_ops *ops)
1691 int chipnr, page, realpage, col, bytes, aligned, oob_required;
1692 struct nand_chip *chip = mtd_to_nand(mtd);
1694 uint32_t readlen = ops->len;
1695 uint32_t oobreadlen = ops->ooblen;
1696 uint32_t max_oobsize = mtd_oobavail(mtd, ops);
1698 uint8_t *bufpoi, *oob, *buf;
1700 unsigned int max_bitflips = 0;
1702 bool ecc_fail = false;
1704 chipnr = (int)(from >> chip->chip_shift);
1705 chip->select_chip(mtd, chipnr);
1707 realpage = (int)(from >> chip->page_shift);
1708 page = realpage & chip->pagemask;
1710 col = (int)(from & (mtd->writesize - 1));
1714 oob_required = oob ? 1 : 0;
1717 unsigned int ecc_failures = mtd->ecc_stats.failed;
1720 bytes = min(mtd->writesize - col, readlen);
1721 aligned = (bytes == mtd->writesize);
1725 else if (chip->options & NAND_USE_BOUNCE_BUFFER)
1726 use_bufpoi = !IS_ALIGNED((unsigned long)buf,
1731 /* Is the current page in the buffer? */
1732 if (realpage != chip->pagebuf || oob) {
1733 bufpoi = use_bufpoi ? chip->buffers->databuf : buf;
1735 if (use_bufpoi && aligned)
1736 pr_debug("%s: using read bounce buffer for buf@%p\n",
1740 if (nand_standard_page_accessors(&chip->ecc))
1741 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1744 * Now read the page into the buffer. Absent an error,
1745 * the read methods return max bitflips per ecc step.
1747 if (unlikely(ops->mode == MTD_OPS_RAW))
1748 ret = chip->ecc.read_page_raw(mtd, chip, bufpoi,
1751 else if (!aligned && NAND_HAS_SUBPAGE_READ(chip) &&
1753 ret = chip->ecc.read_subpage(mtd, chip,
1757 ret = chip->ecc.read_page(mtd, chip, bufpoi,
1758 oob_required, page);
1761 /* Invalidate page cache */
1766 max_bitflips = max_t(unsigned int, max_bitflips, ret);
1768 /* Transfer not aligned data */
1770 if (!NAND_HAS_SUBPAGE_READ(chip) && !oob &&
1771 !(mtd->ecc_stats.failed - ecc_failures) &&
1772 (ops->mode != MTD_OPS_RAW)) {
1773 chip->pagebuf = realpage;
1774 chip->pagebuf_bitflips = ret;
1776 /* Invalidate page cache */
1779 memcpy(buf, chip->buffers->databuf + col, bytes);
1782 if (unlikely(oob)) {
1783 int toread = min(oobreadlen, max_oobsize);
1786 oob = nand_transfer_oob(chip,
1788 oobreadlen -= toread;
1792 if (chip->options & NAND_NEED_READRDY) {
1793 /* Apply delay or wait for ready/busy pin */
1794 if (!chip->dev_ready)
1795 udelay(chip->chip_delay);
1797 nand_wait_ready(mtd);
1800 if (mtd->ecc_stats.failed - ecc_failures) {
1801 if (retry_mode + 1 < chip->read_retries) {
1803 ret = nand_setup_read_retry(mtd,
1808 /* Reset failures; retry */
1809 mtd->ecc_stats.failed = ecc_failures;
1812 /* No more retry modes; real failure */
1819 memcpy(buf, chip->buffers->databuf + col, bytes);
1821 max_bitflips = max_t(unsigned int, max_bitflips,
1822 chip->pagebuf_bitflips);
1827 /* Reset to retry mode 0 */
1829 ret = nand_setup_read_retry(mtd, 0);
1838 /* For subsequent reads align to page boundary */
1840 /* Increment page address */
1843 page = realpage & chip->pagemask;
1844 /* Check, if we cross a chip boundary */
1847 chip->select_chip(mtd, -1);
1848 chip->select_chip(mtd, chipnr);
1851 chip->select_chip(mtd, -1);
1853 ops->retlen = ops->len - (size_t) readlen;
1855 ops->oobretlen = ops->ooblen - oobreadlen;
1863 return max_bitflips;
1867 * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function
1868 * @mtd: mtd info structure
1869 * @chip: nand chip info structure
1870 * @page: page number to read
1872 static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1875 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1876 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1881 * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC
1883 * @mtd: mtd info structure
1884 * @chip: nand chip info structure
1885 * @page: page number to read
1887 static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1890 int length = mtd->oobsize;
1891 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1892 int eccsize = chip->ecc.size;
1893 uint8_t *bufpoi = chip->oob_poi;
1894 int i, toread, sndrnd = 0, pos;
1896 chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1897 for (i = 0; i < chip->ecc.steps; i++) {
1899 pos = eccsize + i * (eccsize + chunk);
1900 if (mtd->writesize > 512)
1901 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1903 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1906 toread = min_t(int, length, chunk);
1907 chip->read_buf(mtd, bufpoi, toread);
1912 chip->read_buf(mtd, bufpoi, length);
1918 * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function
1919 * @mtd: mtd info structure
1920 * @chip: nand chip info structure
1921 * @page: page number to write
1923 static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1927 const uint8_t *buf = chip->oob_poi;
1928 int length = mtd->oobsize;
1930 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1931 chip->write_buf(mtd, buf, length);
1932 /* Send command to program the OOB data */
1933 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1935 status = chip->waitfunc(mtd, chip);
1937 return status & NAND_STATUS_FAIL ? -EIO : 0;
1941 * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC
1942 * with syndrome - only for large page flash
1943 * @mtd: mtd info structure
1944 * @chip: nand chip info structure
1945 * @page: page number to write
1947 static int nand_write_oob_syndrome(struct mtd_info *mtd,
1948 struct nand_chip *chip, int page)
1950 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1951 int eccsize = chip->ecc.size, length = mtd->oobsize;
1952 int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1953 const uint8_t *bufpoi = chip->oob_poi;
1956 * data-ecc-data-ecc ... ecc-oob
1958 * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1960 if (!chip->ecc.prepad && !chip->ecc.postpad) {
1961 pos = steps * (eccsize + chunk);
1966 chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1967 for (i = 0; i < steps; i++) {
1969 if (mtd->writesize <= 512) {
1970 uint32_t fill = 0xFFFFFFFF;
1974 int num = min_t(int, len, 4);
1975 chip->write_buf(mtd, (uint8_t *)&fill,
1980 pos = eccsize + i * (eccsize + chunk);
1981 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
1985 len = min_t(int, length, chunk);
1986 chip->write_buf(mtd, bufpoi, len);
1991 chip->write_buf(mtd, bufpoi, length);
1993 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1994 status = chip->waitfunc(mtd, chip);
1996 return status & NAND_STATUS_FAIL ? -EIO : 0;
2000 * nand_do_read_oob - [INTERN] NAND read out-of-band
2001 * @mtd: MTD device structure
2002 * @from: offset to read from
2003 * @ops: oob operations description structure
2005 * NAND read out-of-band data from the spare area.
2007 static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
2008 struct mtd_oob_ops *ops)
2010 int page, realpage, chipnr;
2011 struct nand_chip *chip = mtd_to_nand(mtd);
2012 struct mtd_ecc_stats stats;
2013 int readlen = ops->ooblen;
2015 uint8_t *buf = ops->oobbuf;
2018 pr_debug("%s: from = 0x%08Lx, len = %i\n",
2019 __func__, (unsigned long long)from, readlen);
2021 stats = mtd->ecc_stats;
2023 len = mtd_oobavail(mtd, ops);
2025 if (unlikely(ops->ooboffs >= len)) {
2026 pr_debug("%s: attempt to start read outside oob\n",
2031 /* Do not allow reads past end of device */
2032 if (unlikely(from >= mtd->size ||
2033 ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
2034 (from >> chip->page_shift)) * len)) {
2035 pr_debug("%s: attempt to read beyond end of device\n",
2040 chipnr = (int)(from >> chip->chip_shift);
2041 chip->select_chip(mtd, chipnr);
2043 /* Shift to get page */
2044 realpage = (int)(from >> chip->page_shift);
2045 page = realpage & chip->pagemask;
2050 if (ops->mode == MTD_OPS_RAW)
2051 ret = chip->ecc.read_oob_raw(mtd, chip, page);
2053 ret = chip->ecc.read_oob(mtd, chip, page);
2058 len = min(len, readlen);
2059 buf = nand_transfer_oob(chip, buf, ops, len);
2061 if (chip->options & NAND_NEED_READRDY) {
2062 /* Apply delay or wait for ready/busy pin */
2063 if (!chip->dev_ready)
2064 udelay(chip->chip_delay);
2066 nand_wait_ready(mtd);
2073 /* Increment page address */
2076 page = realpage & chip->pagemask;
2077 /* Check, if we cross a chip boundary */
2080 chip->select_chip(mtd, -1);
2081 chip->select_chip(mtd, chipnr);
2084 chip->select_chip(mtd, -1);
2086 ops->oobretlen = ops->ooblen - readlen;
2091 if (mtd->ecc_stats.failed - stats.failed)
2094 return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
2098 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
2099 * @mtd: MTD device structure
2100 * @from: offset to read from
2101 * @ops: oob operation description structure
2103 * NAND read data and/or out-of-band data.
2105 static int nand_read_oob(struct mtd_info *mtd, loff_t from,
2106 struct mtd_oob_ops *ops)
2108 int ret = -ENOTSUPP;
2112 /* Do not allow reads past end of device */
2113 if (ops->datbuf && (from + ops->len) > mtd->size) {
2114 pr_debug("%s: attempt to read beyond end of device\n",
2119 nand_get_device(mtd, FL_READING);
2121 switch (ops->mode) {
2122 case MTD_OPS_PLACE_OOB:
2123 case MTD_OPS_AUTO_OOB:
2132 ret = nand_do_read_oob(mtd, from, ops);
2134 ret = nand_do_read_ops(mtd, from, ops);
2137 nand_release_device(mtd);
2143 * nand_write_page_raw - [INTERN] raw page write function
2144 * @mtd: mtd info structure
2145 * @chip: nand chip info structure
2147 * @oob_required: must write chip->oob_poi to OOB
2148 * @page: page number to write
2150 * Not for syndrome calculating ECC controllers, which use a special oob layout.
2152 static int nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
2153 const uint8_t *buf, int oob_required, int page)
2155 chip->write_buf(mtd, buf, mtd->writesize);
2157 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
2163 * nand_write_page_raw_syndrome - [INTERN] raw page write function
2164 * @mtd: mtd info structure
2165 * @chip: nand chip info structure
2167 * @oob_required: must write chip->oob_poi to OOB
2168 * @page: page number to write
2170 * We need a special oob layout and handling even when ECC isn't checked.
2172 static int nand_write_page_raw_syndrome(struct mtd_info *mtd,
2173 struct nand_chip *chip,
2174 const uint8_t *buf, int oob_required,
2177 int eccsize = chip->ecc.size;
2178 int eccbytes = chip->ecc.bytes;
2179 uint8_t *oob = chip->oob_poi;
2182 for (steps = chip->ecc.steps; steps > 0; steps--) {
2183 chip->write_buf(mtd, buf, eccsize);
2186 if (chip->ecc.prepad) {
2187 chip->write_buf(mtd, oob, chip->ecc.prepad);
2188 oob += chip->ecc.prepad;
2191 chip->write_buf(mtd, oob, eccbytes);
2194 if (chip->ecc.postpad) {
2195 chip->write_buf(mtd, oob, chip->ecc.postpad);
2196 oob += chip->ecc.postpad;
2200 size = mtd->oobsize - (oob - chip->oob_poi);
2202 chip->write_buf(mtd, oob, size);
2207 * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function
2208 * @mtd: mtd info structure
2209 * @chip: nand chip info structure
2211 * @oob_required: must write chip->oob_poi to OOB
2212 * @page: page number to write
2214 static int nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
2215 const uint8_t *buf, int oob_required,
2218 int i, eccsize = chip->ecc.size;
2219 int eccbytes = chip->ecc.bytes;
2220 int eccsteps = chip->ecc.steps;
2221 uint8_t *ecc_calc = chip->buffers->ecccalc;
2222 const uint8_t *p = buf;
2223 uint32_t *eccpos = chip->ecc.layout->eccpos;
2225 /* Software ECC calculation */
2226 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
2227 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
2229 for (i = 0; i < chip->ecc.total; i++)
2230 chip->oob_poi[eccpos[i]] = ecc_calc[i];
2232 return chip->ecc.write_page_raw(mtd, chip, buf, 1, page);
2236 * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function
2237 * @mtd: mtd info structure
2238 * @chip: nand chip info structure
2240 * @oob_required: must write chip->oob_poi to OOB
2241 * @page: page number to write
2243 static int nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
2244 const uint8_t *buf, int oob_required,
2247 int i, eccsize = chip->ecc.size;
2248 int eccbytes = chip->ecc.bytes;
2249 int eccsteps = chip->ecc.steps;
2250 uint8_t *ecc_calc = chip->buffers->ecccalc;
2251 const uint8_t *p = buf;
2252 uint32_t *eccpos = chip->ecc.layout->eccpos;
2254 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
2255 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2256 chip->write_buf(mtd, p, eccsize);
2257 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
2260 for (i = 0; i < chip->ecc.total; i++)
2261 chip->oob_poi[eccpos[i]] = ecc_calc[i];
2263 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
2270 * nand_write_subpage_hwecc - [REPLACEABLE] hardware ECC based subpage write
2271 * @mtd: mtd info structure
2272 * @chip: nand chip info structure
2273 * @offset: column address of subpage within the page
2274 * @data_len: data length
2276 * @oob_required: must write chip->oob_poi to OOB
2277 * @page: page number to write
2279 static int nand_write_subpage_hwecc(struct mtd_info *mtd,
2280 struct nand_chip *chip, uint32_t offset,
2281 uint32_t data_len, const uint8_t *buf,
2282 int oob_required, int page)
2284 uint8_t *oob_buf = chip->oob_poi;
2285 uint8_t *ecc_calc = chip->buffers->ecccalc;
2286 int ecc_size = chip->ecc.size;
2287 int ecc_bytes = chip->ecc.bytes;
2288 int ecc_steps = chip->ecc.steps;
2289 uint32_t *eccpos = chip->ecc.layout->eccpos;
2290 uint32_t start_step = offset / ecc_size;
2291 uint32_t end_step = (offset + data_len - 1) / ecc_size;
2292 int oob_bytes = mtd->oobsize / ecc_steps;
2295 for (step = 0; step < ecc_steps; step++) {
2296 /* configure controller for WRITE access */
2297 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2299 /* write data (untouched subpages already masked by 0xFF) */
2300 chip->write_buf(mtd, buf, ecc_size);
2302 /* mask ECC of un-touched subpages by padding 0xFF */
2303 if ((step < start_step) || (step > end_step))
2304 memset(ecc_calc, 0xff, ecc_bytes);
2306 chip->ecc.calculate(mtd, buf, ecc_calc);
2308 /* mask OOB of un-touched subpages by padding 0xFF */
2309 /* if oob_required, preserve OOB metadata of written subpage */
2310 if (!oob_required || (step < start_step) || (step > end_step))
2311 memset(oob_buf, 0xff, oob_bytes);
2314 ecc_calc += ecc_bytes;
2315 oob_buf += oob_bytes;
2318 /* copy calculated ECC for whole page to chip->buffer->oob */
2319 /* this include masked-value(0xFF) for unwritten subpages */
2320 ecc_calc = chip->buffers->ecccalc;
2321 for (i = 0; i < chip->ecc.total; i++)
2322 chip->oob_poi[eccpos[i]] = ecc_calc[i];
2324 /* write OOB buffer to NAND device */
2325 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
2332 * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write
2333 * @mtd: mtd info structure
2334 * @chip: nand chip info structure
2336 * @oob_required: must write chip->oob_poi to OOB
2337 * @page: page number to write
2339 * The hw generator calculates the error syndrome automatically. Therefore we
2340 * need a special oob layout and handling.
2342 static int nand_write_page_syndrome(struct mtd_info *mtd,
2343 struct nand_chip *chip,
2344 const uint8_t *buf, int oob_required,
2347 int i, eccsize = chip->ecc.size;
2348 int eccbytes = chip->ecc.bytes;
2349 int eccsteps = chip->ecc.steps;
2350 const uint8_t *p = buf;
2351 uint8_t *oob = chip->oob_poi;
2353 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
2355 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2356 chip->write_buf(mtd, p, eccsize);
2358 if (chip->ecc.prepad) {
2359 chip->write_buf(mtd, oob, chip->ecc.prepad);
2360 oob += chip->ecc.prepad;
2363 chip->ecc.calculate(mtd, p, oob);
2364 chip->write_buf(mtd, oob, eccbytes);
2367 if (chip->ecc.postpad) {
2368 chip->write_buf(mtd, oob, chip->ecc.postpad);
2369 oob += chip->ecc.postpad;
2373 /* Calculate remaining oob bytes */
2374 i = mtd->oobsize - (oob - chip->oob_poi);
2376 chip->write_buf(mtd, oob, i);
2382 * nand_write_page - [REPLACEABLE] write one page
2383 * @mtd: MTD device structure
2384 * @chip: NAND chip descriptor
2385 * @offset: address offset within the page
2386 * @data_len: length of actual data to be written
2387 * @buf: the data to write
2388 * @oob_required: must write chip->oob_poi to OOB
2389 * @page: page number to write
2390 * @raw: use _raw version of write_page
2392 static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
2393 uint32_t offset, int data_len, const uint8_t *buf,
2394 int oob_required, int page, int raw)
2396 int status, subpage;
2398 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
2399 chip->ecc.write_subpage)
2400 subpage = offset || (data_len < mtd->writesize);
2404 if (nand_standard_page_accessors(&chip->ecc))
2405 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
2408 status = chip->ecc.write_page_raw(mtd, chip, buf,
2409 oob_required, page);
2411 status = chip->ecc.write_subpage(mtd, chip, offset, data_len,
2412 buf, oob_required, page);
2414 status = chip->ecc.write_page(mtd, chip, buf, oob_required,
2420 if (nand_standard_page_accessors(&chip->ecc)) {
2421 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
2423 status = chip->waitfunc(mtd, chip);
2424 if (status & NAND_STATUS_FAIL)
2432 * nand_fill_oob - [INTERN] Transfer client buffer to oob
2433 * @mtd: MTD device structure
2434 * @oob: oob data buffer
2435 * @len: oob data write length
2436 * @ops: oob ops structure
2438 static uint8_t *nand_fill_oob(struct mtd_info *mtd, uint8_t *oob, size_t len,
2439 struct mtd_oob_ops *ops)
2441 struct nand_chip *chip = mtd_to_nand(mtd);
2444 * Initialise to all 0xFF, to avoid the possibility of left over OOB
2445 * data from a previous OOB read.
2447 memset(chip->oob_poi, 0xff, mtd->oobsize);
2449 switch (ops->mode) {
2451 case MTD_OPS_PLACE_OOB:
2453 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
2456 case MTD_OPS_AUTO_OOB: {
2457 struct nand_oobfree *free = chip->ecc.layout->oobfree;
2458 uint32_t boffs = 0, woffs = ops->ooboffs;
2461 for (; free->length && len; free++, len -= bytes) {
2462 /* Write request not from offset 0? */
2463 if (unlikely(woffs)) {
2464 if (woffs >= free->length) {
2465 woffs -= free->length;
2468 boffs = free->offset + woffs;
2469 bytes = min_t(size_t, len,
2470 (free->length - woffs));
2473 bytes = min_t(size_t, len, free->length);
2474 boffs = free->offset;
2476 memcpy(chip->oob_poi + boffs, oob, bytes);
2487 #define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0)
2490 * nand_do_write_ops - [INTERN] NAND write with ECC
2491 * @mtd: MTD device structure
2492 * @to: offset to write to
2493 * @ops: oob operations description structure
2495 * NAND write with ECC.
2497 static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
2498 struct mtd_oob_ops *ops)
2500 int chipnr, realpage, page, column;
2501 struct nand_chip *chip = mtd_to_nand(mtd);
2502 uint32_t writelen = ops->len;
2504 uint32_t oobwritelen = ops->ooblen;
2505 uint32_t oobmaxlen = mtd_oobavail(mtd, ops);
2507 uint8_t *oob = ops->oobbuf;
2508 uint8_t *buf = ops->datbuf;
2510 int oob_required = oob ? 1 : 0;
2516 /* Reject writes, which are not page aligned */
2517 if (NOTALIGNED(to)) {
2518 pr_notice("%s: attempt to write non page aligned data\n",
2523 column = to & (mtd->writesize - 1);
2525 chipnr = (int)(to >> chip->chip_shift);
2526 chip->select_chip(mtd, chipnr);
2528 /* Check, if it is write protected */
2529 if (nand_check_wp(mtd)) {
2534 realpage = (int)(to >> chip->page_shift);
2535 page = realpage & chip->pagemask;
2537 /* Invalidate the page cache, when we write to the cached page */
2538 if (to <= ((loff_t)chip->pagebuf << chip->page_shift) &&
2539 ((loff_t)chip->pagebuf << chip->page_shift) < (to + ops->len))
2542 /* Don't allow multipage oob writes with offset */
2543 if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen)) {
2549 int bytes = mtd->writesize;
2550 uint8_t *wbuf = buf;
2552 int part_pagewr = (column || writelen < mtd->writesize);
2556 else if (chip->options & NAND_USE_BOUNCE_BUFFER)
2557 use_bufpoi = !IS_ALIGNED((unsigned long)buf,
2563 /* Partial page write?, or need to use bounce buffer */
2565 pr_debug("%s: using write bounce buffer for buf@%p\n",
2568 bytes = min_t(int, bytes - column, writelen);
2570 memset(chip->buffers->databuf, 0xff, mtd->writesize);
2571 memcpy(&chip->buffers->databuf[column], buf, bytes);
2572 wbuf = chip->buffers->databuf;
2575 if (unlikely(oob)) {
2576 size_t len = min(oobwritelen, oobmaxlen);
2577 oob = nand_fill_oob(mtd, oob, len, ops);
2580 /* We still need to erase leftover OOB data */
2581 memset(chip->oob_poi, 0xff, mtd->oobsize);
2583 ret = chip->write_page(mtd, chip, column, bytes, wbuf,
2585 (ops->mode == MTD_OPS_RAW));
2597 page = realpage & chip->pagemask;
2598 /* Check, if we cross a chip boundary */
2601 chip->select_chip(mtd, -1);
2602 chip->select_chip(mtd, chipnr);
2606 ops->retlen = ops->len - writelen;
2608 ops->oobretlen = ops->ooblen;
2611 chip->select_chip(mtd, -1);
2616 * panic_nand_write - [MTD Interface] NAND write with ECC
2617 * @mtd: MTD device structure
2618 * @to: offset to write to
2619 * @len: number of bytes to write
2620 * @retlen: pointer to variable to store the number of written bytes
2621 * @buf: the data to write
2623 * NAND write with ECC. Used when performing writes in interrupt context, this
2624 * may for example be called by mtdoops when writing an oops while in panic.
2626 static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2627 size_t *retlen, const uint8_t *buf)
2629 struct nand_chip *chip = mtd_to_nand(mtd);
2630 struct mtd_oob_ops ops;
2633 /* Wait for the device to get ready */
2634 panic_nand_wait(mtd, chip, 400);
2636 /* Grab the device */
2637 panic_nand_get_device(chip, mtd, FL_WRITING);
2639 memset(&ops, 0, sizeof(ops));
2641 ops.datbuf = (uint8_t *)buf;
2642 ops.mode = MTD_OPS_PLACE_OOB;
2644 ret = nand_do_write_ops(mtd, to, &ops);
2646 *retlen = ops.retlen;
2651 * nand_do_write_oob - [MTD Interface] NAND write out-of-band
2652 * @mtd: MTD device structure
2653 * @to: offset to write to
2654 * @ops: oob operation description structure
2656 * NAND write out-of-band.
2658 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
2659 struct mtd_oob_ops *ops)
2661 int chipnr, page, status, len;
2662 struct nand_chip *chip = mtd_to_nand(mtd);
2664 pr_debug("%s: to = 0x%08x, len = %i\n",
2665 __func__, (unsigned int)to, (int)ops->ooblen);
2667 len = mtd_oobavail(mtd, ops);
2669 /* Do not allow write past end of page */
2670 if ((ops->ooboffs + ops->ooblen) > len) {
2671 pr_debug("%s: attempt to write past end of page\n",
2676 if (unlikely(ops->ooboffs >= len)) {
2677 pr_debug("%s: attempt to start write outside oob\n",
2682 /* Do not allow write past end of device */
2683 if (unlikely(to >= mtd->size ||
2684 ops->ooboffs + ops->ooblen >
2685 ((mtd->size >> chip->page_shift) -
2686 (to >> chip->page_shift)) * len)) {
2687 pr_debug("%s: attempt to write beyond end of device\n",
2692 chipnr = (int)(to >> chip->chip_shift);
2695 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2696 * of my DiskOnChip 2000 test units) will clear the whole data page too
2697 * if we don't do this. I have no clue why, but I seem to have 'fixed'
2698 * it in the doc2000 driver in August 1999. dwmw2.
2700 nand_reset(chip, chipnr);
2702 chip->select_chip(mtd, chipnr);
2704 /* Shift to get page */
2705 page = (int)(to >> chip->page_shift);
2707 /* Check, if it is write protected */
2708 if (nand_check_wp(mtd)) {
2709 chip->select_chip(mtd, -1);
2713 /* Invalidate the page cache, if we write to the cached page */
2714 if (page == chip->pagebuf)
2717 nand_fill_oob(mtd, ops->oobbuf, ops->ooblen, ops);
2719 if (ops->mode == MTD_OPS_RAW)
2720 status = chip->ecc.write_oob_raw(mtd, chip, page & chip->pagemask);
2722 status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
2724 chip->select_chip(mtd, -1);
2729 ops->oobretlen = ops->ooblen;
2735 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
2736 * @mtd: MTD device structure
2737 * @to: offset to write to
2738 * @ops: oob operation description structure
2740 static int nand_write_oob(struct mtd_info *mtd, loff_t to,
2741 struct mtd_oob_ops *ops)
2743 int ret = -ENOTSUPP;
2747 /* Do not allow writes past end of device */
2748 if (ops->datbuf && (to + ops->len) > mtd->size) {
2749 pr_debug("%s: attempt to write beyond end of device\n",
2754 nand_get_device(mtd, FL_WRITING);
2756 switch (ops->mode) {
2757 case MTD_OPS_PLACE_OOB:
2758 case MTD_OPS_AUTO_OOB:
2767 ret = nand_do_write_oob(mtd, to, ops);
2769 ret = nand_do_write_ops(mtd, to, ops);
2772 nand_release_device(mtd);
2777 * single_erase - [GENERIC] NAND standard block erase command function
2778 * @mtd: MTD device structure
2779 * @page: the page address of the block which will be erased
2781 * Standard erase command for NAND chips. Returns NAND status.
2783 static int single_erase(struct mtd_info *mtd, int page)
2785 struct nand_chip *chip = mtd_to_nand(mtd);
2786 /* Send commands to erase a block */
2787 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2788 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2790 return chip->waitfunc(mtd, chip);
2794 * nand_erase - [MTD Interface] erase block(s)
2795 * @mtd: MTD device structure
2796 * @instr: erase instruction
2798 * Erase one ore more blocks.
2800 static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
2802 return nand_erase_nand(mtd, instr, 0);
2806 * nand_erase_nand - [INTERN] erase block(s)
2807 * @mtd: MTD device structure
2808 * @instr: erase instruction
2809 * @allowbbt: allow erasing the bbt area
2811 * Erase one ore more blocks.
2813 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2816 int page, status, pages_per_block, ret, chipnr;
2817 struct nand_chip *chip = mtd_to_nand(mtd);
2820 pr_debug("%s: start = 0x%012llx, len = %llu\n",
2821 __func__, (unsigned long long)instr->addr,
2822 (unsigned long long)instr->len);
2824 if (check_offs_len(mtd, instr->addr, instr->len))
2827 /* Grab the lock and see if the device is available */
2828 nand_get_device(mtd, FL_ERASING);
2830 /* Shift to get first page */
2831 page = (int)(instr->addr >> chip->page_shift);
2832 chipnr = (int)(instr->addr >> chip->chip_shift);
2834 /* Calculate pages in each block */
2835 pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
2837 /* Select the NAND device */
2838 chip->select_chip(mtd, chipnr);
2840 /* Check, if it is write protected */
2841 if (nand_check_wp(mtd)) {
2842 pr_debug("%s: device is write protected!\n",
2844 instr->state = MTD_ERASE_FAILED;
2848 /* Loop through the pages */
2851 instr->state = MTD_ERASING;
2856 /* Check if we have a bad block, we do not erase bad blocks! */
2857 if (!instr->scrub && nand_block_checkbad(mtd, ((loff_t) page) <<
2858 chip->page_shift, allowbbt)) {
2859 pr_warn("%s: attempt to erase a bad block at page 0x%08x\n",
2861 instr->state = MTD_ERASE_FAILED;
2866 * Invalidate the page cache, if we erase the block which
2867 * contains the current cached page.
2869 if (page <= chip->pagebuf && chip->pagebuf <
2870 (page + pages_per_block))
2873 status = chip->erase(mtd, page & chip->pagemask);
2875 /* See if block erase succeeded */
2876 if (status & NAND_STATUS_FAIL) {
2877 pr_debug("%s: failed erase, page 0x%08x\n",
2879 instr->state = MTD_ERASE_FAILED;
2881 ((loff_t)page << chip->page_shift);
2885 /* Increment page address and decrement length */
2886 len -= (1ULL << chip->phys_erase_shift);
2887 page += pages_per_block;
2889 /* Check, if we cross a chip boundary */
2890 if (len && !(page & chip->pagemask)) {
2892 chip->select_chip(mtd, -1);
2893 chip->select_chip(mtd, chipnr);
2896 instr->state = MTD_ERASE_DONE;
2900 ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
2902 /* Deselect and wake up anyone waiting on the device */
2903 chip->select_chip(mtd, -1);
2904 nand_release_device(mtd);
2906 /* Do call back function */
2908 mtd_erase_callback(instr);
2910 /* Return more or less happy */
2915 * nand_sync - [MTD Interface] sync
2916 * @mtd: MTD device structure
2918 * Sync is actually a wait for chip ready function.
2920 static void nand_sync(struct mtd_info *mtd)
2922 pr_debug("%s: called\n", __func__);
2924 /* Grab the lock and see if the device is available */
2925 nand_get_device(mtd, FL_SYNCING);
2926 /* Release it and go back */
2927 nand_release_device(mtd);
2931 * nand_block_isbad - [MTD Interface] Check if block at offset is bad
2932 * @mtd: MTD device structure
2933 * @offs: offset relative to mtd start
2935 static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
2937 struct nand_chip *chip = mtd_to_nand(mtd);
2938 int chipnr = (int)(offs >> chip->chip_shift);
2941 /* Select the NAND device */
2942 nand_get_device(mtd, FL_READING);
2943 chip->select_chip(mtd, chipnr);
2945 ret = nand_block_checkbad(mtd, offs, 0);
2947 chip->select_chip(mtd, -1);
2948 nand_release_device(mtd);
2954 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
2955 * @mtd: MTD device structure
2956 * @ofs: offset relative to mtd start
2958 static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
2962 ret = nand_block_isbad(mtd, ofs);
2964 /* If it was bad already, return success and do nothing */
2970 return nand_block_markbad_lowlevel(mtd, ofs);
2974 * nand_onfi_set_features- [REPLACEABLE] set features for ONFI nand
2975 * @mtd: MTD device structure
2976 * @chip: nand chip info structure
2977 * @addr: feature address.
2978 * @subfeature_param: the subfeature parameters, a four bytes array.
2980 static int nand_onfi_set_features(struct mtd_info *mtd, struct nand_chip *chip,
2981 int addr, uint8_t *subfeature_param)
2986 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
2987 if (!chip->onfi_version ||
2988 !(le16_to_cpu(chip->onfi_params.opt_cmd)
2989 & ONFI_OPT_CMD_SET_GET_FEATURES))
2993 chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES, addr, -1);
2994 for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
2995 chip->write_byte(mtd, subfeature_param[i]);
2997 status = chip->waitfunc(mtd, chip);
2998 if (status & NAND_STATUS_FAIL)
3004 * nand_onfi_get_features- [REPLACEABLE] get features for ONFI nand
3005 * @mtd: MTD device structure
3006 * @chip: nand chip info structure
3007 * @addr: feature address.
3008 * @subfeature_param: the subfeature parameters, a four bytes array.
3010 static int nand_onfi_get_features(struct mtd_info *mtd, struct nand_chip *chip,
3011 int addr, uint8_t *subfeature_param)
3015 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
3016 if (!chip->onfi_version ||
3017 !(le16_to_cpu(chip->onfi_params.opt_cmd)
3018 & ONFI_OPT_CMD_SET_GET_FEATURES))
3022 chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES, addr, -1);
3023 for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
3024 *subfeature_param++ = chip->read_byte(mtd);
3028 /* Set default functions */
3029 static void nand_set_defaults(struct nand_chip *chip, int busw)
3031 /* check for proper chip_delay setup, set 20us if not */
3032 if (!chip->chip_delay)
3033 chip->chip_delay = 20;
3035 /* check, if a user supplied command function given */
3036 if (chip->cmdfunc == NULL)
3037 chip->cmdfunc = nand_command;
3039 /* check, if a user supplied wait function given */
3040 if (chip->waitfunc == NULL)
3041 chip->waitfunc = nand_wait;
3043 if (!chip->select_chip)
3044 chip->select_chip = nand_select_chip;
3046 /* set for ONFI nand */
3047 if (!chip->onfi_set_features)
3048 chip->onfi_set_features = nand_onfi_set_features;
3049 if (!chip->onfi_get_features)
3050 chip->onfi_get_features = nand_onfi_get_features;
3052 /* If called twice, pointers that depend on busw may need to be reset */
3053 if (!chip->read_byte || chip->read_byte == nand_read_byte)
3054 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
3055 if (!chip->read_word)
3056 chip->read_word = nand_read_word;
3057 if (!chip->block_bad)
3058 chip->block_bad = nand_block_bad;
3059 if (!chip->block_markbad)
3060 chip->block_markbad = nand_default_block_markbad;
3061 if (!chip->write_buf || chip->write_buf == nand_write_buf)
3062 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
3063 if (!chip->write_byte || chip->write_byte == nand_write_byte)
3064 chip->write_byte = busw ? nand_write_byte16 : nand_write_byte;
3065 if (!chip->read_buf || chip->read_buf == nand_read_buf)
3066 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
3067 if (!chip->scan_bbt)
3068 chip->scan_bbt = nand_default_bbt;
3070 if (!chip->controller) {
3071 chip->controller = &chip->hwcontrol;
3072 spin_lock_init(&chip->controller->lock);
3073 init_waitqueue_head(&chip->controller->wq);
3076 if (!chip->buf_align)
3077 chip->buf_align = 1;
3080 /* Sanitize ONFI strings so we can safely print them */
3081 static void sanitize_string(char *s, size_t len)
3085 /* Null terminate */
3088 /* Remove non printable chars */
3089 for (i = 0; i < len - 1; i++) {
3090 if (s[i] < ' ' || s[i] > 127)
3094 /* Remove trailing spaces */
3098 static u16 onfi_crc16(u16 crc, u8 const *p, size_t len)
3103 for (i = 0; i < 8; i++)
3104 crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0);
3110 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
3111 /* Parse the Extended Parameter Page. */
3112 static int nand_flash_detect_ext_param_page(struct mtd_info *mtd,
3113 struct nand_chip *chip, struct nand_onfi_params *p)
3115 struct onfi_ext_param_page *ep;
3116 struct onfi_ext_section *s;
3117 struct onfi_ext_ecc_info *ecc;
3123 len = le16_to_cpu(p->ext_param_page_length) * 16;
3124 ep = kmalloc(len, GFP_KERNEL);
3128 /* Send our own NAND_CMD_PARAM. */
3129 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
3131 /* Use the Change Read Column command to skip the ONFI param pages. */
3132 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
3133 sizeof(*p) * p->num_of_param_pages , -1);
3135 /* Read out the Extended Parameter Page. */
3136 chip->read_buf(mtd, (uint8_t *)ep, len);
3137 if ((onfi_crc16(ONFI_CRC_BASE, ((uint8_t *)ep) + 2, len - 2)
3138 != le16_to_cpu(ep->crc))) {
3139 pr_debug("fail in the CRC.\n");
3144 * Check the signature.
3145 * Do not strictly follow the ONFI spec, maybe changed in future.
3147 if (strncmp((char *)ep->sig, "EPPS", 4)) {
3148 pr_debug("The signature is invalid.\n");
3152 /* find the ECC section. */
3153 cursor = (uint8_t *)(ep + 1);
3154 for (i = 0; i < ONFI_EXT_SECTION_MAX; i++) {
3155 s = ep->sections + i;
3156 if (s->type == ONFI_SECTION_TYPE_2)
3158 cursor += s->length * 16;
3160 if (i == ONFI_EXT_SECTION_MAX) {
3161 pr_debug("We can not find the ECC section.\n");
3165 /* get the info we want. */
3166 ecc = (struct onfi_ext_ecc_info *)cursor;
3168 if (!ecc->codeword_size) {
3169 pr_debug("Invalid codeword size\n");
3173 chip->ecc_strength_ds = ecc->ecc_bits;
3174 chip->ecc_step_ds = 1 << ecc->codeword_size;
3182 static int nand_setup_read_retry_micron(struct mtd_info *mtd, int retry_mode)
3184 struct nand_chip *chip = mtd_to_nand(mtd);
3185 uint8_t feature[ONFI_SUBFEATURE_PARAM_LEN] = {retry_mode};
3187 return chip->onfi_set_features(mtd, chip, ONFI_FEATURE_ADDR_READ_RETRY,
3192 * Configure chip properties from Micron vendor-specific ONFI table
3194 static void nand_onfi_detect_micron(struct nand_chip *chip,
3195 struct nand_onfi_params *p)
3197 struct nand_onfi_vendor_micron *micron = (void *)p->vendor;
3199 if (le16_to_cpu(p->vendor_revision) < 1)
3202 chip->read_retries = micron->read_retry_options;
3203 chip->setup_read_retry = nand_setup_read_retry_micron;
3207 * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise.
3209 static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
3212 struct nand_onfi_params *p = &chip->onfi_params;
3216 /* Try ONFI for unknown chip or LP */
3217 chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1);
3218 if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' ||
3219 chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I')
3222 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
3223 for (i = 0; i < 3; i++) {
3224 for (j = 0; j < sizeof(*p); j++)
3225 ((uint8_t *)p)[j] = chip->read_byte(mtd);
3226 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) ==
3227 le16_to_cpu(p->crc)) {
3233 pr_err("Could not find valid ONFI parameter page; aborting\n");
3238 val = le16_to_cpu(p->revision);
3240 chip->onfi_version = 23;
3241 else if (val & (1 << 4))
3242 chip->onfi_version = 22;
3243 else if (val & (1 << 3))
3244 chip->onfi_version = 21;
3245 else if (val & (1 << 2))
3246 chip->onfi_version = 20;
3247 else if (val & (1 << 1))
3248 chip->onfi_version = 10;
3250 if (!chip->onfi_version) {
3251 pr_info("unsupported ONFI version: %d\n", val);
3255 sanitize_string(p->manufacturer, sizeof(p->manufacturer));
3256 sanitize_string(p->model, sizeof(p->model));
3258 mtd->name = p->model;
3260 mtd->writesize = le32_to_cpu(p->byte_per_page);
3263 * pages_per_block and blocks_per_lun may not be a power-of-2 size
3264 * (don't ask me who thought of this...). MTD assumes that these
3265 * dimensions will be power-of-2, so just truncate the remaining area.
3267 mtd->erasesize = 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1);
3268 mtd->erasesize *= mtd->writesize;
3270 mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
3272 /* See erasesize comment */
3273 chip->chipsize = 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1);
3274 chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
3275 chip->bits_per_cell = p->bits_per_cell;
3277 if (onfi_feature(chip) & ONFI_FEATURE_16_BIT_BUS)
3278 *busw = NAND_BUSWIDTH_16;
3282 if (p->ecc_bits != 0xff) {
3283 chip->ecc_strength_ds = p->ecc_bits;
3284 chip->ecc_step_ds = 512;
3285 } else if (chip->onfi_version >= 21 &&
3286 (onfi_feature(chip) & ONFI_FEATURE_EXT_PARAM_PAGE)) {
3289 * The nand_flash_detect_ext_param_page() uses the
3290 * Change Read Column command which maybe not supported
3291 * by the chip->cmdfunc. So try to update the chip->cmdfunc
3292 * now. We do not replace user supplied command function.
3294 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
3295 chip->cmdfunc = nand_command_lp;
3297 /* The Extended Parameter Page is supported since ONFI 2.1. */
3298 if (nand_flash_detect_ext_param_page(mtd, chip, p))
3299 pr_warn("Failed to detect ONFI extended param page\n");
3301 pr_warn("Could not retrieve ONFI ECC requirements\n");
3304 if (p->jedec_id == NAND_MFR_MICRON)
3305 nand_onfi_detect_micron(chip, p);
3310 static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
3318 * Check if the NAND chip is JEDEC compliant, returns 1 if it is, 0 otherwise.
3320 static int nand_flash_detect_jedec(struct mtd_info *mtd, struct nand_chip *chip,
3323 struct nand_jedec_params *p = &chip->jedec_params;
3324 struct jedec_ecc_info *ecc;
3328 /* Try JEDEC for unknown chip or LP */
3329 chip->cmdfunc(mtd, NAND_CMD_READID, 0x40, -1);
3330 if (chip->read_byte(mtd) != 'J' || chip->read_byte(mtd) != 'E' ||
3331 chip->read_byte(mtd) != 'D' || chip->read_byte(mtd) != 'E' ||
3332 chip->read_byte(mtd) != 'C')
3335 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0x40, -1);
3336 for (i = 0; i < 3; i++) {
3337 for (j = 0; j < sizeof(*p); j++)
3338 ((uint8_t *)p)[j] = chip->read_byte(mtd);
3340 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 510) ==
3341 le16_to_cpu(p->crc))
3346 pr_err("Could not find valid JEDEC parameter page; aborting\n");
3351 val = le16_to_cpu(p->revision);
3353 chip->jedec_version = 10;
3354 else if (val & (1 << 1))
3355 chip->jedec_version = 1; /* vendor specific version */
3357 if (!chip->jedec_version) {
3358 pr_info("unsupported JEDEC version: %d\n", val);
3362 sanitize_string(p->manufacturer, sizeof(p->manufacturer));
3363 sanitize_string(p->model, sizeof(p->model));
3365 mtd->name = p->model;
3367 mtd->writesize = le32_to_cpu(p->byte_per_page);
3369 /* Please reference to the comment for nand_flash_detect_onfi. */
3370 mtd->erasesize = 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1);
3371 mtd->erasesize *= mtd->writesize;
3373 mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
3375 /* Please reference to the comment for nand_flash_detect_onfi. */
3376 chip->chipsize = 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1);
3377 chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
3378 chip->bits_per_cell = p->bits_per_cell;
3380 if (jedec_feature(chip) & JEDEC_FEATURE_16_BIT_BUS)
3381 *busw = NAND_BUSWIDTH_16;
3386 ecc = &p->ecc_info[0];
3388 if (ecc->codeword_size >= 9) {
3389 chip->ecc_strength_ds = ecc->ecc_bits;
3390 chip->ecc_step_ds = 1 << ecc->codeword_size;
3392 pr_warn("Invalid codeword size\n");
3399 * nand_id_has_period - Check if an ID string has a given wraparound period
3400 * @id_data: the ID string
3401 * @arrlen: the length of the @id_data array
3402 * @period: the period of repitition
3404 * Check if an ID string is repeated within a given sequence of bytes at
3405 * specific repetition interval period (e.g., {0x20,0x01,0x7F,0x20} has a
3406 * period of 3). This is a helper function for nand_id_len(). Returns non-zero
3407 * if the repetition has a period of @period; otherwise, returns zero.
3409 static int nand_id_has_period(u8 *id_data, int arrlen, int period)
3412 for (i = 0; i < period; i++)
3413 for (j = i + period; j < arrlen; j += period)
3414 if (id_data[i] != id_data[j])
3420 * nand_id_len - Get the length of an ID string returned by CMD_READID
3421 * @id_data: the ID string
3422 * @arrlen: the length of the @id_data array
3424 * Returns the length of the ID string, according to known wraparound/trailing
3425 * zero patterns. If no pattern exists, returns the length of the array.
3427 static int nand_id_len(u8 *id_data, int arrlen)
3429 int last_nonzero, period;
3431 /* Find last non-zero byte */
3432 for (last_nonzero = arrlen - 1; last_nonzero >= 0; last_nonzero--)
3433 if (id_data[last_nonzero])
3437 if (last_nonzero < 0)
3440 /* Calculate wraparound period */
3441 for (period = 1; period < arrlen; period++)
3442 if (nand_id_has_period(id_data, arrlen, period))
3445 /* There's a repeated pattern */
3446 if (period < arrlen)
3449 /* There are trailing zeros */
3450 if (last_nonzero < arrlen - 1)
3451 return last_nonzero + 1;
3453 /* No pattern detected */
3457 /* Extract the bits of per cell from the 3rd byte of the extended ID */
3458 static int nand_get_bits_per_cell(u8 cellinfo)
3462 bits = cellinfo & NAND_CI_CELLTYPE_MSK;
3463 bits >>= NAND_CI_CELLTYPE_SHIFT;
3468 * Many new NAND share similar device ID codes, which represent the size of the
3469 * chip. The rest of the parameters must be decoded according to generic or
3470 * manufacturer-specific "extended ID" decoding patterns.
3472 static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip,
3473 u8 id_data[8], int *busw)
3476 /* The 3rd id byte holds MLC / multichip data */
3477 chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]);
3478 /* The 4th id byte is the important one */
3481 id_len = nand_id_len(id_data, 8);
3484 * Field definitions are in the following datasheets:
3485 * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32)
3486 * New Samsung (6 byte ID): Samsung K9GAG08U0F (p.44)
3487 * Hynix MLC (6 byte ID): Hynix H27UBG8T2B (p.22)
3489 * Check for ID length, non-zero 6th byte, cell type, and Hynix/Samsung
3490 * ID to decide what to do.
3492 if (id_len == 6 && id_data[0] == NAND_MFR_SAMSUNG &&
3493 !nand_is_slc(chip) && id_data[5] != 0x00) {
3495 mtd->writesize = 2048 << (extid & 0x03);
3498 switch (((extid >> 2) & 0x04) | (extid & 0x03)) {
3518 default: /* Other cases are "reserved" (unknown) */
3519 mtd->oobsize = 1024;
3523 /* Calc blocksize */
3524 mtd->erasesize = (128 * 1024) <<
3525 (((extid >> 1) & 0x04) | (extid & 0x03));
3527 } else if (id_len == 6 && id_data[0] == NAND_MFR_HYNIX &&
3528 !nand_is_slc(chip)) {
3532 mtd->writesize = 2048 << (extid & 0x03);
3535 switch (((extid >> 2) & 0x04) | (extid & 0x03)) {
3559 /* Calc blocksize */
3560 tmp = ((extid >> 1) & 0x04) | (extid & 0x03);
3562 mtd->erasesize = (128 * 1024) << tmp;
3563 else if (tmp == 0x03)
3564 mtd->erasesize = 768 * 1024;
3566 mtd->erasesize = (64 * 1024) << tmp;
3570 mtd->writesize = 1024 << (extid & 0x03);
3573 mtd->oobsize = (8 << (extid & 0x01)) *
3574 (mtd->writesize >> 9);
3576 /* Calc blocksize. Blocksize is multiples of 64KiB */
3577 mtd->erasesize = (64 * 1024) << (extid & 0x03);
3579 /* Get buswidth information */
3580 *busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
3583 * Toshiba 24nm raw SLC (i.e., not BENAND) have 32B OOB per
3584 * 512B page. For Toshiba SLC, we decode the 5th/6th byte as
3586 * - ID byte 6, bits[2:0]: 100b -> 43nm, 101b -> 32nm,
3588 * - ID byte 5, bit[7]: 1 -> BENAND, 0 -> raw SLC
3590 if (id_len >= 6 && id_data[0] == NAND_MFR_TOSHIBA &&
3591 nand_is_slc(chip) &&
3592 (id_data[5] & 0x7) == 0x6 /* 24nm */ &&
3593 !(id_data[4] & 0x80) /* !BENAND */) {
3594 mtd->oobsize = 32 * mtd->writesize >> 9;
3601 * Old devices have chip data hardcoded in the device ID table. nand_decode_id
3602 * decodes a matching ID table entry and assigns the MTD size parameters for
3605 static void nand_decode_id(struct mtd_info *mtd, struct nand_chip *chip,
3606 struct nand_flash_dev *type, u8 id_data[8],
3609 int maf_id = id_data[0];
3611 mtd->erasesize = type->erasesize;
3612 mtd->writesize = type->pagesize;
3613 mtd->oobsize = mtd->writesize / 32;
3614 *busw = type->options & NAND_BUSWIDTH_16;
3616 /* All legacy ID NAND are small-page, SLC */
3617 chip->bits_per_cell = 1;
3620 * Check for Spansion/AMD ID + repeating 5th, 6th byte since
3621 * some Spansion chips have erasesize that conflicts with size
3622 * listed in nand_ids table.
3623 * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39)
3625 if (maf_id == NAND_MFR_AMD && id_data[4] != 0x00 && id_data[5] == 0x00
3626 && id_data[6] == 0x00 && id_data[7] == 0x00
3627 && mtd->writesize == 512) {
3628 mtd->erasesize = 128 * 1024;
3629 mtd->erasesize <<= ((id_data[3] & 0x03) << 1);
3634 * Set the bad block marker/indicator (BBM/BBI) patterns according to some
3635 * heuristic patterns using various detected parameters (e.g., manufacturer,
3636 * page size, cell-type information).
3638 static void nand_decode_bbm_options(struct mtd_info *mtd,
3639 struct nand_chip *chip, u8 id_data[8])
3641 int maf_id = id_data[0];
3643 /* Set the bad block position */
3644 if (mtd->writesize > 512 || (chip->options & NAND_BUSWIDTH_16))
3645 chip->badblockpos = NAND_LARGE_BADBLOCK_POS;
3647 chip->badblockpos = NAND_SMALL_BADBLOCK_POS;
3650 * Bad block marker is stored in the last page of each block on Samsung
3651 * and Hynix MLC devices; stored in first two pages of each block on
3652 * Micron devices with 2KiB pages and on SLC Samsung, Hynix, Toshiba,
3653 * AMD/Spansion, and Macronix. All others scan only the first page.
3655 if (!nand_is_slc(chip) &&
3656 (maf_id == NAND_MFR_SAMSUNG ||
3657 maf_id == NAND_MFR_HYNIX))
3658 chip->bbt_options |= NAND_BBT_SCANLASTPAGE;
3659 else if ((nand_is_slc(chip) &&
3660 (maf_id == NAND_MFR_SAMSUNG ||
3661 maf_id == NAND_MFR_HYNIX ||
3662 maf_id == NAND_MFR_TOSHIBA ||
3663 maf_id == NAND_MFR_AMD ||
3664 maf_id == NAND_MFR_MACRONIX)) ||
3665 (mtd->writesize == 2048 &&
3666 maf_id == NAND_MFR_MICRON))
3667 chip->bbt_options |= NAND_BBT_SCAN2NDPAGE;
3670 static inline bool is_full_id_nand(struct nand_flash_dev *type)
3672 return type->id_len;
3675 static bool find_full_id_nand(struct mtd_info *mtd, struct nand_chip *chip,
3676 struct nand_flash_dev *type, u8 *id_data, int *busw)
3678 if (!strncmp((char *)type->id, (char *)id_data, type->id_len)) {
3679 mtd->writesize = type->pagesize;
3680 mtd->erasesize = type->erasesize;
3681 mtd->oobsize = type->oobsize;
3683 chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]);
3684 chip->chipsize = (uint64_t)type->chipsize << 20;
3685 chip->options |= type->options;
3686 chip->ecc_strength_ds = NAND_ECC_STRENGTH(type);
3687 chip->ecc_step_ds = NAND_ECC_STEP(type);
3688 chip->onfi_timing_mode_default =
3689 type->onfi_timing_mode_default;
3691 *busw = type->options & NAND_BUSWIDTH_16;
3694 mtd->name = type->name;
3702 * Get the flash and manufacturer id and lookup if the type is supported.
3704 struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
3705 struct nand_chip *chip,
3706 int *maf_id, int *dev_id,
3707 struct nand_flash_dev *type)
3714 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
3717 nand_reset(chip, 0);
3719 /* Select the device */
3720 chip->select_chip(mtd, 0);
3722 /* Send the command for reading device ID */
3723 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
3725 /* Read manufacturer and device IDs */
3726 *maf_id = chip->read_byte(mtd);
3727 *dev_id = chip->read_byte(mtd);
3730 * Try again to make sure, as some systems the bus-hold or other
3731 * interface concerns can cause random data which looks like a
3732 * possibly credible NAND flash to appear. If the two results do
3733 * not match, ignore the device completely.
3736 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
3738 /* Read entire ID string */
3739 for (i = 0; i < 8; i++)
3740 id_data[i] = chip->read_byte(mtd);
3742 if (id_data[0] != *maf_id || id_data[1] != *dev_id) {
3743 pr_info("second ID read did not match %02x,%02x against %02x,%02x\n",
3744 *maf_id, *dev_id, id_data[0], id_data[1]);
3745 return ERR_PTR(-ENODEV);
3749 type = nand_flash_ids;
3751 for (; type->name != NULL; type++) {
3752 if (is_full_id_nand(type)) {
3753 if (find_full_id_nand(mtd, chip, type, id_data, &busw))
3755 } else if (*dev_id == type->dev_id) {
3760 chip->onfi_version = 0;
3761 if (!type->name || !type->pagesize) {
3762 /* Check if the chip is ONFI compliant */
3763 if (nand_flash_detect_onfi(mtd, chip, &busw))
3766 /* Check if the chip is JEDEC compliant */
3767 if (nand_flash_detect_jedec(mtd, chip, &busw))
3772 return ERR_PTR(-ENODEV);
3775 mtd->name = type->name;
3777 chip->chipsize = (uint64_t)type->chipsize << 20;
3779 if (!type->pagesize) {
3780 /* Decode parameters from extended ID */
3781 nand_decode_ext_id(mtd, chip, id_data, &busw);
3783 nand_decode_id(mtd, chip, type, id_data, &busw);
3785 /* Get chip options */
3786 chip->options |= type->options;
3789 * Check if chip is not a Samsung device. Do not clear the
3790 * options for chips which do not have an extended id.
3792 if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
3793 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
3796 /* Try to identify manufacturer */
3797 for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
3798 if (nand_manuf_ids[maf_idx].id == *maf_id)
3802 if (chip->options & NAND_BUSWIDTH_AUTO) {
3803 WARN_ON(chip->options & NAND_BUSWIDTH_16);
3804 chip->options |= busw;
3805 nand_set_defaults(chip, busw);
3806 } else if (busw != (chip->options & NAND_BUSWIDTH_16)) {
3808 * Check, if buswidth is correct. Hardware drivers should set
3811 pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
3813 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name, mtd->name);
3814 pr_warn("bus width %d instead %d bit\n",
3815 (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
3817 return ERR_PTR(-EINVAL);
3820 nand_decode_bbm_options(mtd, chip, id_data);
3822 /* Calculate the address shift from the page size */
3823 chip->page_shift = ffs(mtd->writesize) - 1;
3824 /* Convert chipsize to number of pages per chip -1 */
3825 chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
3827 chip->bbt_erase_shift = chip->phys_erase_shift =
3828 ffs(mtd->erasesize) - 1;
3829 if (chip->chipsize & 0xffffffff)
3830 chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
3832 chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32));
3833 chip->chip_shift += 32 - 1;
3836 if (chip->chip_shift - chip->page_shift > 16)
3837 chip->options |= NAND_ROW_ADDR_3;
3839 chip->badblockbits = 8;
3840 chip->erase = single_erase;
3842 /* Do not replace user supplied command function! */
3843 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
3844 chip->cmdfunc = nand_command_lp;
3846 pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
3849 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
3850 if (chip->onfi_version)
3851 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3852 chip->onfi_params.model);
3853 else if (chip->jedec_version)
3854 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3855 chip->jedec_params.model);
3857 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3860 if (chip->jedec_version)
3861 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3862 chip->jedec_params.model);
3864 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3867 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3871 pr_info("%d MiB, %s, erase size: %d KiB, page size: %d, OOB size: %d\n",
3872 (int)(chip->chipsize >> 20), nand_is_slc(chip) ? "SLC" : "MLC",
3873 mtd->erasesize >> 10, mtd->writesize, mtd->oobsize);
3876 EXPORT_SYMBOL(nand_get_flash_type);
3878 #if CONFIG_IS_ENABLED(OF_CONTROL)
3879 DECLARE_GLOBAL_DATA_PTR;
3881 static int nand_dt_init(struct mtd_info *mtd, struct nand_chip *chip, int node)
3883 int ret, ecc_mode = -1, ecc_strength, ecc_step;
3884 const void *blob = gd->fdt_blob;
3887 ret = fdtdec_get_int(blob, node, "nand-bus-width", -1);
3889 chip->options |= NAND_BUSWIDTH_16;
3891 if (fdtdec_get_bool(blob, node, "nand-on-flash-bbt"))
3892 chip->bbt_options |= NAND_BBT_USE_FLASH;
3894 str = fdt_getprop(blob, node, "nand-ecc-mode", NULL);
3896 if (!strcmp(str, "none"))
3897 ecc_mode = NAND_ECC_NONE;
3898 else if (!strcmp(str, "soft"))
3899 ecc_mode = NAND_ECC_SOFT;
3900 else if (!strcmp(str, "hw"))
3901 ecc_mode = NAND_ECC_HW;
3902 else if (!strcmp(str, "hw_syndrome"))
3903 ecc_mode = NAND_ECC_HW_SYNDROME;
3904 else if (!strcmp(str, "hw_oob_first"))
3905 ecc_mode = NAND_ECC_HW_OOB_FIRST;
3906 else if (!strcmp(str, "soft_bch"))
3907 ecc_mode = NAND_ECC_SOFT_BCH;
3911 ecc_strength = fdtdec_get_int(blob, node, "nand-ecc-strength", -1);
3912 ecc_step = fdtdec_get_int(blob, node, "nand-ecc-step-size", -1);
3914 if ((ecc_step >= 0 && !(ecc_strength >= 0)) ||
3915 (!(ecc_step >= 0) && ecc_strength >= 0)) {
3916 pr_err("must set both strength and step size in DT\n");
3921 chip->ecc.mode = ecc_mode;
3923 if (ecc_strength >= 0)
3924 chip->ecc.strength = ecc_strength;
3927 chip->ecc.size = ecc_step;
3929 if (fdt_getprop(blob, node, "nand-ecc-maximize", NULL))
3930 chip->ecc.options |= NAND_ECC_MAXIMIZE;
3935 static int nand_dt_init(struct mtd_info *mtd, struct nand_chip *chip, int node)
3939 #endif /* CONFIG_IS_ENABLED(OF_CONTROL) */
3942 * nand_scan_ident - [NAND Interface] Scan for the NAND device
3943 * @mtd: MTD device structure
3944 * @maxchips: number of chips to scan for
3945 * @table: alternative NAND ID table
3947 * This is the first phase of the normal nand_scan() function. It reads the
3948 * flash ID and sets up MTD fields accordingly.
3951 int nand_scan_ident(struct mtd_info *mtd, int maxchips,
3952 struct nand_flash_dev *table)
3954 int i, nand_maf_id, nand_dev_id;
3955 struct nand_chip *chip = mtd_to_nand(mtd);
3956 struct nand_flash_dev *type;
3959 if (chip->flash_node) {
3960 ret = nand_dt_init(mtd, chip, chip->flash_node);
3965 /* Set the default functions */
3966 nand_set_defaults(chip, chip->options & NAND_BUSWIDTH_16);
3968 /* Read the flash type */
3969 type = nand_get_flash_type(mtd, chip, &nand_maf_id,
3970 &nand_dev_id, table);
3973 if (!(chip->options & NAND_SCAN_SILENT_NODEV))
3974 pr_warn("No NAND device found\n");
3975 chip->select_chip(mtd, -1);
3976 return PTR_ERR(type);
3979 /* Initialize the ->data_interface field. */
3980 ret = nand_init_data_interface(chip);
3985 * Setup the data interface correctly on the chip and controller side.
3986 * This explicit call to nand_setup_data_interface() is only required
3987 * for the first die, because nand_reset() has been called before
3988 * ->data_interface and ->default_onfi_timing_mode were set.
3989 * For the other dies, nand_reset() will automatically switch to the
3992 ret = nand_setup_data_interface(chip, 0);
3996 chip->select_chip(mtd, -1);
3998 /* Check for a chip array */
3999 for (i = 1; i < maxchips; i++) {
4000 /* See comment in nand_get_flash_type for reset */
4001 nand_reset(chip, i);
4003 chip->select_chip(mtd, i);
4004 /* Send the command for reading device ID */
4005 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
4006 /* Read manufacturer and device IDs */
4007 if (nand_maf_id != chip->read_byte(mtd) ||
4008 nand_dev_id != chip->read_byte(mtd)) {
4009 chip->select_chip(mtd, -1);
4012 chip->select_chip(mtd, -1);
4017 pr_info("%d chips detected\n", i);
4020 /* Store the number of chips and calc total size for mtd */
4022 mtd->size = i * chip->chipsize;
4026 EXPORT_SYMBOL(nand_scan_ident);
4029 * nand_check_ecc_caps - check the sanity of preset ECC settings
4030 * @chip: nand chip info structure
4031 * @caps: ECC caps info structure
4032 * @oobavail: OOB size that the ECC engine can use
4034 * When ECC step size and strength are already set, check if they are supported
4035 * by the controller and the calculated ECC bytes fit within the chip's OOB.
4036 * On success, the calculated ECC bytes is set.
4038 int nand_check_ecc_caps(struct nand_chip *chip,
4039 const struct nand_ecc_caps *caps, int oobavail)
4041 struct mtd_info *mtd = nand_to_mtd(chip);
4042 const struct nand_ecc_step_info *stepinfo;
4043 int preset_step = chip->ecc.size;
4044 int preset_strength = chip->ecc.strength;
4045 int nsteps, ecc_bytes;
4048 if (WARN_ON(oobavail < 0))
4051 if (!preset_step || !preset_strength)
4054 nsteps = mtd->writesize / preset_step;
4056 for (i = 0; i < caps->nstepinfos; i++) {
4057 stepinfo = &caps->stepinfos[i];
4059 if (stepinfo->stepsize != preset_step)
4062 for (j = 0; j < stepinfo->nstrengths; j++) {
4063 if (stepinfo->strengths[j] != preset_strength)
4066 ecc_bytes = caps->calc_ecc_bytes(preset_step,
4068 if (WARN_ON_ONCE(ecc_bytes < 0))
4071 if (ecc_bytes * nsteps > oobavail) {
4072 pr_err("ECC (step, strength) = (%d, %d) does not fit in OOB",
4073 preset_step, preset_strength);
4077 chip->ecc.bytes = ecc_bytes;
4083 pr_err("ECC (step, strength) = (%d, %d) not supported on this controller",
4084 preset_step, preset_strength);
4088 EXPORT_SYMBOL_GPL(nand_check_ecc_caps);
4091 * nand_match_ecc_req - meet the chip's requirement with least ECC bytes
4092 * @chip: nand chip info structure
4093 * @caps: ECC engine caps info structure
4094 * @oobavail: OOB size that the ECC engine can use
4096 * If a chip's ECC requirement is provided, try to meet it with the least
4097 * number of ECC bytes (i.e. with the largest number of OOB-free bytes).
4098 * On success, the chosen ECC settings are set.
4100 int nand_match_ecc_req(struct nand_chip *chip,
4101 const struct nand_ecc_caps *caps, int oobavail)
4103 struct mtd_info *mtd = nand_to_mtd(chip);
4104 const struct nand_ecc_step_info *stepinfo;
4105 int req_step = chip->ecc_step_ds;
4106 int req_strength = chip->ecc_strength_ds;
4107 int req_corr, step_size, strength, nsteps, ecc_bytes, ecc_bytes_total;
4108 int best_step, best_strength, best_ecc_bytes;
4109 int best_ecc_bytes_total = INT_MAX;
4112 if (WARN_ON(oobavail < 0))
4115 /* No information provided by the NAND chip */
4116 if (!req_step || !req_strength)
4119 /* number of correctable bits the chip requires in a page */
4120 req_corr = mtd->writesize / req_step * req_strength;
4122 for (i = 0; i < caps->nstepinfos; i++) {
4123 stepinfo = &caps->stepinfos[i];
4124 step_size = stepinfo->stepsize;
4126 for (j = 0; j < stepinfo->nstrengths; j++) {
4127 strength = stepinfo->strengths[j];
4130 * If both step size and strength are smaller than the
4131 * chip's requirement, it is not easy to compare the
4132 * resulted reliability.
4134 if (step_size < req_step && strength < req_strength)
4137 if (mtd->writesize % step_size)
4140 nsteps = mtd->writesize / step_size;
4142 ecc_bytes = caps->calc_ecc_bytes(step_size, strength);
4143 if (WARN_ON_ONCE(ecc_bytes < 0))
4145 ecc_bytes_total = ecc_bytes * nsteps;
4147 if (ecc_bytes_total > oobavail ||
4148 strength * nsteps < req_corr)
4152 * We assume the best is to meet the chip's requrement
4153 * with the least number of ECC bytes.
4155 if (ecc_bytes_total < best_ecc_bytes_total) {
4156 best_ecc_bytes_total = ecc_bytes_total;
4157 best_step = step_size;
4158 best_strength = strength;
4159 best_ecc_bytes = ecc_bytes;
4164 if (best_ecc_bytes_total == INT_MAX)
4167 chip->ecc.size = best_step;
4168 chip->ecc.strength = best_strength;
4169 chip->ecc.bytes = best_ecc_bytes;
4173 EXPORT_SYMBOL_GPL(nand_match_ecc_req);
4176 * nand_maximize_ecc - choose the max ECC strength available
4177 * @chip: nand chip info structure
4178 * @caps: ECC engine caps info structure
4179 * @oobavail: OOB size that the ECC engine can use
4181 * Choose the max ECC strength that is supported on the controller, and can fit
4182 * within the chip's OOB. On success, the chosen ECC settings are set.
4184 int nand_maximize_ecc(struct nand_chip *chip,
4185 const struct nand_ecc_caps *caps, int oobavail)
4187 struct mtd_info *mtd = nand_to_mtd(chip);
4188 const struct nand_ecc_step_info *stepinfo;
4189 int step_size, strength, nsteps, ecc_bytes, corr;
4192 int best_strength, best_ecc_bytes;
4195 if (WARN_ON(oobavail < 0))
4198 for (i = 0; i < caps->nstepinfos; i++) {
4199 stepinfo = &caps->stepinfos[i];
4200 step_size = stepinfo->stepsize;
4202 /* If chip->ecc.size is already set, respect it */
4203 if (chip->ecc.size && step_size != chip->ecc.size)
4206 for (j = 0; j < stepinfo->nstrengths; j++) {
4207 strength = stepinfo->strengths[j];
4209 if (mtd->writesize % step_size)
4212 nsteps = mtd->writesize / step_size;
4214 ecc_bytes = caps->calc_ecc_bytes(step_size, strength);
4215 if (WARN_ON_ONCE(ecc_bytes < 0))
4218 if (ecc_bytes * nsteps > oobavail)
4221 corr = strength * nsteps;
4224 * If the number of correctable bits is the same,
4225 * bigger step_size has more reliability.
4227 if (corr > best_corr ||
4228 (corr == best_corr && step_size > best_step)) {
4230 best_step = step_size;
4231 best_strength = strength;
4232 best_ecc_bytes = ecc_bytes;
4240 chip->ecc.size = best_step;
4241 chip->ecc.strength = best_strength;
4242 chip->ecc.bytes = best_ecc_bytes;
4246 EXPORT_SYMBOL_GPL(nand_maximize_ecc);
4249 * Check if the chip configuration meet the datasheet requirements.
4251 * If our configuration corrects A bits per B bytes and the minimum
4252 * required correction level is X bits per Y bytes, then we must ensure
4253 * both of the following are true:
4255 * (1) A / B >= X / Y
4258 * Requirement (1) ensures we can correct for the required bitflip density.
4259 * Requirement (2) ensures we can correct even when all bitflips are clumped
4260 * in the same sector.
4262 static bool nand_ecc_strength_good(struct mtd_info *mtd)
4264 struct nand_chip *chip = mtd_to_nand(mtd);
4265 struct nand_ecc_ctrl *ecc = &chip->ecc;
4268 if (ecc->size == 0 || chip->ecc_step_ds == 0)
4269 /* Not enough information */
4273 * We get the number of corrected bits per page to compare
4274 * the correction density.
4276 corr = (mtd->writesize * ecc->strength) / ecc->size;
4277 ds_corr = (mtd->writesize * chip->ecc_strength_ds) / chip->ecc_step_ds;
4279 return corr >= ds_corr && ecc->strength >= chip->ecc_strength_ds;
4282 static bool invalid_ecc_page_accessors(struct nand_chip *chip)
4284 struct nand_ecc_ctrl *ecc = &chip->ecc;
4286 if (nand_standard_page_accessors(ecc))
4290 * NAND_ECC_CUSTOM_PAGE_ACCESS flag is set, make sure the NAND
4291 * controller driver implements all the page accessors because
4292 * default helpers are not suitable when the core does not
4293 * send the READ0/PAGEPROG commands.
4295 return (!ecc->read_page || !ecc->write_page ||
4296 !ecc->read_page_raw || !ecc->write_page_raw ||
4297 (NAND_HAS_SUBPAGE_READ(chip) && !ecc->read_subpage) ||
4298 (NAND_HAS_SUBPAGE_WRITE(chip) && !ecc->write_subpage &&
4299 ecc->hwctl && ecc->calculate));
4303 * nand_scan_tail - [NAND Interface] Scan for the NAND device
4304 * @mtd: MTD device structure
4306 * This is the second phase of the normal nand_scan() function. It fills out
4307 * all the uninitialized function pointers with the defaults and scans for a
4308 * bad block table if appropriate.
4310 int nand_scan_tail(struct mtd_info *mtd)
4313 struct nand_chip *chip = mtd_to_nand(mtd);
4314 struct nand_ecc_ctrl *ecc = &chip->ecc;
4315 struct nand_buffers *nbuf;
4317 /* New bad blocks should be marked in OOB, flash-based BBT, or both */
4318 BUG_ON((chip->bbt_options & NAND_BBT_NO_OOB_BBM) &&
4319 !(chip->bbt_options & NAND_BBT_USE_FLASH));
4321 if (invalid_ecc_page_accessors(chip)) {
4322 pr_err("Invalid ECC page accessors setup\n");
4326 if (!(chip->options & NAND_OWN_BUFFERS)) {
4327 nbuf = kzalloc(sizeof(struct nand_buffers), GFP_KERNEL);
4328 chip->buffers = nbuf;
4334 /* Set the internal oob buffer location, just after the page data */
4335 chip->oob_poi = chip->buffers->databuf + mtd->writesize;
4338 * If no default placement scheme is given, select an appropriate one.
4340 if (!ecc->layout && (ecc->mode != NAND_ECC_SOFT_BCH)) {
4341 switch (mtd->oobsize) {
4343 ecc->layout = &nand_oob_8;
4346 ecc->layout = &nand_oob_16;
4349 ecc->layout = &nand_oob_64;
4352 ecc->layout = &nand_oob_128;
4355 pr_warn("No oob scheme defined for oobsize %d\n",
4361 if (!chip->write_page)
4362 chip->write_page = nand_write_page;
4365 * Check ECC mode, default to software if 3byte/512byte hardware ECC is
4366 * selected and we have 256 byte pagesize fallback to software ECC
4369 switch (ecc->mode) {
4370 case NAND_ECC_HW_OOB_FIRST:
4371 /* Similar to NAND_ECC_HW, but a separate read_page handle */
4372 if (!ecc->calculate || !ecc->correct || !ecc->hwctl) {
4373 pr_warn("No ECC functions supplied; hardware ECC not possible\n");
4376 if (!ecc->read_page)
4377 ecc->read_page = nand_read_page_hwecc_oob_first;
4380 /* Use standard hwecc read page function? */
4381 if (!ecc->read_page)
4382 ecc->read_page = nand_read_page_hwecc;
4383 if (!ecc->write_page)
4384 ecc->write_page = nand_write_page_hwecc;
4385 if (!ecc->read_page_raw)
4386 ecc->read_page_raw = nand_read_page_raw;
4387 if (!ecc->write_page_raw)
4388 ecc->write_page_raw = nand_write_page_raw;
4390 ecc->read_oob = nand_read_oob_std;
4391 if (!ecc->write_oob)
4392 ecc->write_oob = nand_write_oob_std;
4393 if (!ecc->read_subpage)
4394 ecc->read_subpage = nand_read_subpage;
4395 if (!ecc->write_subpage && ecc->hwctl && ecc->calculate)
4396 ecc->write_subpage = nand_write_subpage_hwecc;
4398 case NAND_ECC_HW_SYNDROME:
4399 if ((!ecc->calculate || !ecc->correct || !ecc->hwctl) &&
4401 ecc->read_page == nand_read_page_hwecc ||
4403 ecc->write_page == nand_write_page_hwecc)) {
4404 pr_warn("No ECC functions supplied; hardware ECC not possible\n");
4407 /* Use standard syndrome read/write page function? */
4408 if (!ecc->read_page)
4409 ecc->read_page = nand_read_page_syndrome;
4410 if (!ecc->write_page)
4411 ecc->write_page = nand_write_page_syndrome;
4412 if (!ecc->read_page_raw)
4413 ecc->read_page_raw = nand_read_page_raw_syndrome;
4414 if (!ecc->write_page_raw)
4415 ecc->write_page_raw = nand_write_page_raw_syndrome;
4417 ecc->read_oob = nand_read_oob_syndrome;
4418 if (!ecc->write_oob)
4419 ecc->write_oob = nand_write_oob_syndrome;
4421 if (mtd->writesize >= ecc->size) {
4422 if (!ecc->strength) {
4423 pr_warn("Driver must set ecc.strength when using hardware ECC\n");
4428 pr_warn("%d byte HW ECC not possible on %d byte page size, fallback to SW ECC\n",
4429 ecc->size, mtd->writesize);
4430 ecc->mode = NAND_ECC_SOFT;
4433 ecc->calculate = nand_calculate_ecc;
4434 ecc->correct = nand_correct_data;
4435 ecc->read_page = nand_read_page_swecc;
4436 ecc->read_subpage = nand_read_subpage;
4437 ecc->write_page = nand_write_page_swecc;
4438 ecc->read_page_raw = nand_read_page_raw;
4439 ecc->write_page_raw = nand_write_page_raw;
4440 ecc->read_oob = nand_read_oob_std;
4441 ecc->write_oob = nand_write_oob_std;
4448 case NAND_ECC_SOFT_BCH:
4449 if (!mtd_nand_has_bch()) {
4450 pr_warn("CONFIG_MTD_NAND_ECC_BCH not enabled\n");
4453 ecc->calculate = nand_bch_calculate_ecc;
4454 ecc->correct = nand_bch_correct_data;
4455 ecc->read_page = nand_read_page_swecc;
4456 ecc->read_subpage = nand_read_subpage;
4457 ecc->write_page = nand_write_page_swecc;
4458 ecc->read_page_raw = nand_read_page_raw;
4459 ecc->write_page_raw = nand_write_page_raw;
4460 ecc->read_oob = nand_read_oob_std;
4461 ecc->write_oob = nand_write_oob_std;
4463 * Board driver should supply ecc.size and ecc.strength values
4464 * to select how many bits are correctable. Otherwise, default
4465 * to 4 bits for large page devices.
4467 if (!ecc->size && (mtd->oobsize >= 64)) {
4472 /* See nand_bch_init() for details. */
4474 ecc->priv = nand_bch_init(mtd);
4476 pr_warn("BCH ECC initialization failed!\n");
4482 pr_warn("NAND_ECC_NONE selected by board driver. This is not recommended!\n");
4483 ecc->read_page = nand_read_page_raw;
4484 ecc->write_page = nand_write_page_raw;
4485 ecc->read_oob = nand_read_oob_std;
4486 ecc->read_page_raw = nand_read_page_raw;
4487 ecc->write_page_raw = nand_write_page_raw;
4488 ecc->write_oob = nand_write_oob_std;
4489 ecc->size = mtd->writesize;
4495 pr_warn("Invalid NAND_ECC_MODE %d\n", ecc->mode);
4499 /* For many systems, the standard OOB write also works for raw */
4500 if (!ecc->read_oob_raw)
4501 ecc->read_oob_raw = ecc->read_oob;
4502 if (!ecc->write_oob_raw)
4503 ecc->write_oob_raw = ecc->write_oob;
4506 * The number of bytes available for a client to place data into
4507 * the out of band area.
4511 for (i = 0; ecc->layout->oobfree[i].length; i++)
4512 mtd->oobavail += ecc->layout->oobfree[i].length;
4515 /* ECC sanity check: warn if it's too weak */
4516 if (!nand_ecc_strength_good(mtd))
4517 pr_warn("WARNING: %s: the ECC used on your system is too weak compared to the one required by the NAND chip\n",
4521 * Set the number of read / write steps for one page depending on ECC
4524 ecc->steps = mtd->writesize / ecc->size;
4525 if (ecc->steps * ecc->size != mtd->writesize) {
4526 pr_warn("Invalid ECC parameters\n");
4529 ecc->total = ecc->steps * ecc->bytes;
4531 /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */
4532 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && nand_is_slc(chip)) {
4533 switch (ecc->steps) {
4535 mtd->subpage_sft = 1;
4540 mtd->subpage_sft = 2;
4544 chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
4546 /* Initialize state */
4547 chip->state = FL_READY;
4549 /* Invalidate the pagebuffer reference */
4552 /* Large page NAND with SOFT_ECC should support subpage reads */
4553 switch (ecc->mode) {
4555 case NAND_ECC_SOFT_BCH:
4556 if (chip->page_shift > 9)
4557 chip->options |= NAND_SUBPAGE_READ;
4564 /* Fill in remaining MTD driver data */
4565 mtd->type = nand_is_slc(chip) ? MTD_NANDFLASH : MTD_MLCNANDFLASH;
4566 mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM :
4568 mtd->_erase = nand_erase;
4569 mtd->_panic_write = panic_nand_write;
4570 mtd->_read_oob = nand_read_oob;
4571 mtd->_write_oob = nand_write_oob;
4572 mtd->_sync = nand_sync;
4574 mtd->_unlock = NULL;
4575 mtd->_block_isreserved = nand_block_isreserved;
4576 mtd->_block_isbad = nand_block_isbad;
4577 mtd->_block_markbad = nand_block_markbad;
4578 mtd->writebufsize = mtd->writesize;
4580 /* propagate ecc info to mtd_info */
4581 mtd->ecclayout = ecc->layout;
4582 mtd->ecc_strength = ecc->strength;
4583 mtd->ecc_step_size = ecc->size;
4585 * Initialize bitflip_threshold to its default prior scan_bbt() call.
4586 * scan_bbt() might invoke mtd_read(), thus bitflip_threshold must be
4589 if (!mtd->bitflip_threshold)
4590 mtd->bitflip_threshold = DIV_ROUND_UP(mtd->ecc_strength * 3, 4);
4594 EXPORT_SYMBOL(nand_scan_tail);
4597 * nand_scan - [NAND Interface] Scan for the NAND device
4598 * @mtd: MTD device structure
4599 * @maxchips: number of chips to scan for
4601 * This fills out all the uninitialized function pointers with the defaults.
4602 * The flash ID is read and the mtd/chip structures are filled with the
4603 * appropriate values.
4605 int nand_scan(struct mtd_info *mtd, int maxchips)
4609 ret = nand_scan_ident(mtd, maxchips, NULL);
4611 ret = nand_scan_tail(mtd);
4614 EXPORT_SYMBOL(nand_scan);
4616 MODULE_LICENSE("GPL");
4617 MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>");
4618 MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
4619 MODULE_DESCRIPTION("Generic NAND flash driver code");