1 // SPDX-License-Identifier: GPL-2.0+
3 * Freescale i.MX28 NAND flash driver
5 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
6 * on behalf of DENX Software Engineering GmbH
8 * Based on code from LTIB:
9 * Freescale GPMI NFC NAND Flash Driver
11 * Copyright (C) 2010 Freescale Semiconductor, Inc.
12 * Copyright (C) 2008 Embedded Alley Solutions, Inc.
13 * Copyright 2017-2019 NXP
19 #include <asm/cache.h>
20 #include <linux/mtd/rawnand.h>
21 #include <linux/sizes.h>
22 #include <linux/types.h>
24 #include <linux/errno.h>
26 #include <asm/arch/clock.h>
27 #include <asm/arch/imx-regs.h>
28 #include <asm/mach-imx/regs-bch.h>
29 #include <asm/mach-imx/regs-gpmi.h>
30 #include <asm/arch/sys_proto.h>
33 #define MXS_NAND_DMA_DESCRIPTOR_COUNT 4
35 #if defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_IMX8) || \
37 #define MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT 2
39 #define MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT 0
41 #define MXS_NAND_METADATA_SIZE 10
42 #define MXS_NAND_BITS_PER_ECC_LEVEL 13
44 #if !defined(CONFIG_SYS_CACHELINE_SIZE) || CONFIG_SYS_CACHELINE_SIZE < 32
45 #define MXS_NAND_COMMAND_BUFFER_SIZE 32
47 #define MXS_NAND_COMMAND_BUFFER_SIZE CONFIG_SYS_CACHELINE_SIZE
50 #define MXS_NAND_BCH_TIMEOUT 10000
52 struct nand_ecclayout fake_ecc_layout;
55 * Cache management functions
57 #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
58 static void mxs_nand_flush_data_buf(struct mxs_nand_info *info)
60 uint32_t addr = (uintptr_t)info->data_buf;
62 flush_dcache_range(addr, addr + info->data_buf_size);
65 static void mxs_nand_inval_data_buf(struct mxs_nand_info *info)
67 uint32_t addr = (uintptr_t)info->data_buf;
69 invalidate_dcache_range(addr, addr + info->data_buf_size);
72 static void mxs_nand_flush_cmd_buf(struct mxs_nand_info *info)
74 uint32_t addr = (uintptr_t)info->cmd_buf;
76 flush_dcache_range(addr, addr + MXS_NAND_COMMAND_BUFFER_SIZE);
79 static inline void mxs_nand_flush_data_buf(struct mxs_nand_info *info) {}
80 static inline void mxs_nand_inval_data_buf(struct mxs_nand_info *info) {}
81 static inline void mxs_nand_flush_cmd_buf(struct mxs_nand_info *info) {}
84 static struct mxs_dma_desc *mxs_nand_get_dma_desc(struct mxs_nand_info *info)
86 struct mxs_dma_desc *desc;
88 if (info->desc_index >= MXS_NAND_DMA_DESCRIPTOR_COUNT) {
89 printf("MXS NAND: Too many DMA descriptors requested\n");
93 desc = info->desc[info->desc_index];
99 static void mxs_nand_return_dma_descs(struct mxs_nand_info *info)
102 struct mxs_dma_desc *desc;
104 for (i = 0; i < info->desc_index; i++) {
105 desc = info->desc[i];
106 memset(desc, 0, sizeof(struct mxs_dma_desc));
107 desc->address = (dma_addr_t)desc;
110 info->desc_index = 0;
113 static uint32_t mxs_nand_aux_status_offset(void)
115 return (MXS_NAND_METADATA_SIZE + 0x3) & ~0x3;
118 static inline bool mxs_nand_bbm_in_data_chunk(struct bch_geometry *geo, struct mtd_info *mtd,
119 unsigned int *chunk_num)
123 if (geo->ecc_chunk0_size != geo->ecc_chunkn_size) {
124 dev_err(this->dev, "The size of chunk0 must equal to chunkn\n");
128 i = (mtd->writesize * 8 - MXS_NAND_METADATA_SIZE * 8) /
129 (geo->gf_len * geo->ecc_strength +
130 geo->ecc_chunkn_size * 8);
132 j = (mtd->writesize * 8 - MXS_NAND_METADATA_SIZE * 8) -
133 (geo->gf_len * geo->ecc_strength +
134 geo->ecc_chunkn_size * 8) * i;
136 if (j < geo->ecc_chunkn_size * 8) {
138 dev_dbg(this->dev, "Set ecc to %d and bbm in chunk %d\n",
139 geo->ecc_strength, *chunk_num);
146 static inline int mxs_nand_calc_ecc_layout_by_info(struct bch_geometry *geo,
147 struct mtd_info *mtd,
148 unsigned int ecc_strength,
149 unsigned int ecc_step)
151 struct nand_chip *chip = mtd_to_nand(mtd);
152 struct mxs_nand_info *nand_info = nand_get_controller_data(chip);
153 unsigned int block_mark_bit_offset;
166 geo->ecc_chunk0_size = ecc_step;
167 geo->ecc_chunkn_size = ecc_step;
168 geo->ecc_strength = round_up(ecc_strength, 2);
170 /* Keep the C >= O */
171 if (geo->ecc_chunkn_size < mtd->oobsize)
174 if (geo->ecc_strength > nand_info->max_ecc_strength_supported)
177 geo->ecc_chunk_count = mtd->writesize / geo->ecc_chunkn_size;
180 block_mark_bit_offset = mtd->writesize * 8 -
181 (geo->ecc_strength * geo->gf_len * (geo->ecc_chunk_count - 1)
182 + MXS_NAND_METADATA_SIZE * 8);
184 geo->block_mark_byte_offset = block_mark_bit_offset / 8;
185 geo->block_mark_bit_offset = block_mark_bit_offset % 8;
190 static inline int mxs_nand_legacy_calc_ecc_layout(struct bch_geometry *geo,
191 struct mtd_info *mtd)
193 struct nand_chip *chip = mtd_to_nand(mtd);
194 struct mxs_nand_info *nand_info = nand_get_controller_data(chip);
195 unsigned int block_mark_bit_offset;
197 /* The default for the length of Galois Field. */
200 /* The default for chunk size. */
201 geo->ecc_chunk0_size = 512;
202 geo->ecc_chunkn_size = 512;
204 if (geo->ecc_chunkn_size < mtd->oobsize) {
206 geo->ecc_chunk0_size *= 2;
207 geo->ecc_chunkn_size *= 2;
210 geo->ecc_chunk_count = mtd->writesize / geo->ecc_chunkn_size;
213 * Determine the ECC layout with the formula:
214 * ECC bits per chunk = (total page spare data bits) /
215 * (bits per ECC level) / (chunks per page)
217 * total page spare data bits =
218 * (page oob size - meta data size) * (bits per byte)
220 geo->ecc_strength = ((mtd->oobsize - MXS_NAND_METADATA_SIZE) * 8)
221 / (geo->gf_len * geo->ecc_chunk_count);
223 geo->ecc_strength = min(round_down(geo->ecc_strength, 2),
224 nand_info->max_ecc_strength_supported);
226 block_mark_bit_offset = mtd->writesize * 8 -
227 (geo->ecc_strength * geo->gf_len * (geo->ecc_chunk_count - 1)
228 + MXS_NAND_METADATA_SIZE * 8);
230 geo->block_mark_byte_offset = block_mark_bit_offset / 8;
231 geo->block_mark_bit_offset = block_mark_bit_offset % 8;
236 static inline int mxs_nand_calc_ecc_for_large_oob(struct bch_geometry *geo,
237 struct mtd_info *mtd)
239 struct nand_chip *chip = mtd_to_nand(mtd);
240 struct mxs_nand_info *nand_info = nand_get_controller_data(chip);
241 unsigned int block_mark_bit_offset;
242 unsigned int max_ecc;
243 unsigned int bbm_chunk;
246 /* sanity check for the minimum ecc nand required */
247 if (!(chip->ecc_strength_ds > 0 && chip->ecc_step_ds > 0))
249 geo->ecc_strength = chip->ecc_strength_ds;
251 /* calculate the maximum ecc platform can support*/
253 geo->ecc_chunk0_size = 1024;
254 geo->ecc_chunkn_size = 1024;
255 geo->ecc_chunk_count = mtd->writesize / geo->ecc_chunkn_size;
256 max_ecc = ((mtd->oobsize - MXS_NAND_METADATA_SIZE) * 8)
257 / (geo->gf_len * geo->ecc_chunk_count);
258 max_ecc = min(round_down(max_ecc, 2),
259 nand_info->max_ecc_strength_supported);
262 /* search a supported ecc strength that makes bbm */
263 /* located in data chunk */
264 geo->ecc_strength = chip->ecc_strength_ds;
265 while (!(geo->ecc_strength > max_ecc)) {
266 if (mxs_nand_bbm_in_data_chunk(geo, mtd, &bbm_chunk))
268 geo->ecc_strength += 2;
271 /* if none of them works, keep using the minimum ecc */
272 /* nand required but changing ecc page layout */
273 if (geo->ecc_strength > max_ecc) {
274 geo->ecc_strength = chip->ecc_strength_ds;
275 /* add extra ecc for meta data */
276 geo->ecc_chunk0_size = 0;
277 geo->ecc_chunk_count = (mtd->writesize / geo->ecc_chunkn_size) + 1;
278 geo->ecc_for_meta = 1;
279 /* check if oob can afford this extra ecc chunk */
280 if (mtd->oobsize * 8 < MXS_NAND_METADATA_SIZE * 8 +
281 geo->gf_len * geo->ecc_strength
282 * geo->ecc_chunk_count) {
283 printf("unsupported NAND chip with new layout\n");
287 /* calculate in which chunk bbm located */
288 bbm_chunk = (mtd->writesize * 8 - MXS_NAND_METADATA_SIZE * 8 -
289 geo->gf_len * geo->ecc_strength) /
290 (geo->gf_len * geo->ecc_strength +
291 geo->ecc_chunkn_size * 8) + 1;
294 /* calculate the number of ecc chunk behind the bbm */
295 i = (mtd->writesize / geo->ecc_chunkn_size) - bbm_chunk + 1;
297 block_mark_bit_offset = mtd->writesize * 8 -
298 (geo->ecc_strength * geo->gf_len * (geo->ecc_chunk_count - i)
299 + MXS_NAND_METADATA_SIZE * 8);
301 geo->block_mark_byte_offset = block_mark_bit_offset / 8;
302 geo->block_mark_bit_offset = block_mark_bit_offset % 8;
308 * Wait for BCH complete IRQ and clear the IRQ
310 static int mxs_nand_wait_for_bch_complete(struct mxs_nand_info *nand_info)
312 int timeout = MXS_NAND_BCH_TIMEOUT;
315 ret = mxs_wait_mask_set(&nand_info->bch_regs->hw_bch_ctrl_reg,
316 BCH_CTRL_COMPLETE_IRQ, timeout);
318 writel(BCH_CTRL_COMPLETE_IRQ, &nand_info->bch_regs->hw_bch_ctrl_clr);
324 * This is the function that we install in the cmd_ctrl function pointer of the
325 * owning struct nand_chip. The only functions in the reference implementation
326 * that use these functions pointers are cmdfunc and select_chip.
328 * In this driver, we implement our own select_chip, so this function will only
329 * be called by the reference implementation's cmdfunc. For this reason, we can
330 * ignore the chip enable bit and concentrate only on sending bytes to the NAND
333 static void mxs_nand_cmd_ctrl(struct mtd_info *mtd, int data, unsigned int ctrl)
335 struct nand_chip *nand = mtd_to_nand(mtd);
336 struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
337 struct mxs_dma_desc *d;
338 uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
342 * If this condition is true, something is _VERY_ wrong in MTD
345 if (nand_info->cmd_queue_len == MXS_NAND_COMMAND_BUFFER_SIZE) {
346 printf("MXS NAND: Command queue too long\n");
351 * Every operation begins with a command byte and a series of zero or
352 * more address bytes. These are distinguished by either the Address
353 * Latch Enable (ALE) or Command Latch Enable (CLE) signals being
354 * asserted. When MTD is ready to execute the command, it will
355 * deasert both latch enables.
357 * Rather than run a separate DMA operation for every single byte, we
358 * queue them up and run a single DMA operation for the entire series
359 * of command and data bytes.
361 if (ctrl & (NAND_ALE | NAND_CLE)) {
362 if (data != NAND_CMD_NONE)
363 nand_info->cmd_buf[nand_info->cmd_queue_len++] = data;
368 * If control arrives here, MTD has deasserted both the ALE and CLE,
369 * which means it's ready to run an operation. Check if we have any
372 if (nand_info->cmd_queue_len == 0)
375 /* Compile the DMA descriptor -- a descriptor that sends command. */
376 d = mxs_nand_get_dma_desc(nand_info);
378 MXS_DMA_DESC_COMMAND_DMA_READ | MXS_DMA_DESC_IRQ |
379 MXS_DMA_DESC_CHAIN | MXS_DMA_DESC_DEC_SEM |
380 MXS_DMA_DESC_WAIT4END | (3 << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
381 (nand_info->cmd_queue_len << MXS_DMA_DESC_BYTES_OFFSET);
383 d->cmd.address = (dma_addr_t)nand_info->cmd_buf;
385 d->cmd.pio_words[0] =
386 GPMI_CTRL0_COMMAND_MODE_WRITE |
387 GPMI_CTRL0_WORD_LENGTH |
388 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
389 GPMI_CTRL0_ADDRESS_NAND_CLE |
390 GPMI_CTRL0_ADDRESS_INCREMENT |
391 nand_info->cmd_queue_len;
393 mxs_dma_desc_append(channel, d);
396 mxs_nand_flush_cmd_buf(nand_info);
398 /* Execute the DMA chain. */
399 ret = mxs_dma_go(channel);
401 printf("MXS NAND: Error sending command\n");
403 mxs_nand_return_dma_descs(nand_info);
405 /* Reset the command queue. */
406 nand_info->cmd_queue_len = 0;
410 * Test if the NAND flash is ready.
412 static int mxs_nand_device_ready(struct mtd_info *mtd)
414 struct nand_chip *chip = mtd_to_nand(mtd);
415 struct mxs_nand_info *nand_info = nand_get_controller_data(chip);
418 tmp = readl(&nand_info->gpmi_regs->hw_gpmi_stat);
419 tmp >>= (GPMI_STAT_READY_BUSY_OFFSET + nand_info->cur_chip);
425 * Select the NAND chip.
427 static void mxs_nand_select_chip(struct mtd_info *mtd, int chip)
429 struct nand_chip *nand = mtd_to_nand(mtd);
430 struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
432 nand_info->cur_chip = chip;
436 * Handle block mark swapping.
438 * Note that, when this function is called, it doesn't know whether it's
439 * swapping the block mark, or swapping it *back* -- but it doesn't matter
440 * because the the operation is the same.
442 static void mxs_nand_swap_block_mark(struct bch_geometry *geo,
443 uint8_t *data_buf, uint8_t *oob_buf)
445 uint32_t bit_offset = geo->block_mark_bit_offset;
446 uint32_t buf_offset = geo->block_mark_byte_offset;
452 * Get the byte from the data area that overlays the block mark. Since
453 * the ECC engine applies its own view to the bits in the page, the
454 * physical block mark won't (in general) appear on a byte boundary in
457 src = data_buf[buf_offset] >> bit_offset;
458 src |= data_buf[buf_offset + 1] << (8 - bit_offset);
464 data_buf[buf_offset] &= ~(0xff << bit_offset);
465 data_buf[buf_offset + 1] &= 0xff << bit_offset;
467 data_buf[buf_offset] |= dst << bit_offset;
468 data_buf[buf_offset + 1] |= dst >> (8 - bit_offset);
472 * Read data from NAND.
474 static void mxs_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int length)
476 struct nand_chip *nand = mtd_to_nand(mtd);
477 struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
478 struct mxs_dma_desc *d;
479 uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
482 if (length > NAND_MAX_PAGESIZE) {
483 printf("MXS NAND: DMA buffer too big\n");
488 printf("MXS NAND: DMA buffer is NULL\n");
492 /* Compile the DMA descriptor - a descriptor that reads data. */
493 d = mxs_nand_get_dma_desc(nand_info);
495 MXS_DMA_DESC_COMMAND_DMA_WRITE | MXS_DMA_DESC_IRQ |
496 MXS_DMA_DESC_DEC_SEM | MXS_DMA_DESC_WAIT4END |
497 (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
498 (length << MXS_DMA_DESC_BYTES_OFFSET);
500 d->cmd.address = (dma_addr_t)nand_info->data_buf;
502 d->cmd.pio_words[0] =
503 GPMI_CTRL0_COMMAND_MODE_READ |
504 GPMI_CTRL0_WORD_LENGTH |
505 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
506 GPMI_CTRL0_ADDRESS_NAND_DATA |
509 mxs_dma_desc_append(channel, d);
512 * A DMA descriptor that waits for the command to end and the chip to
515 * I think we actually should *not* be waiting for the chip to become
516 * ready because, after all, we don't care. I think the original code
517 * did that and no one has re-thought it yet.
519 d = mxs_nand_get_dma_desc(nand_info);
521 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_IRQ |
522 MXS_DMA_DESC_NAND_WAIT_4_READY | MXS_DMA_DESC_DEC_SEM |
523 MXS_DMA_DESC_WAIT4END | (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
527 d->cmd.pio_words[0] =
528 GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY |
529 GPMI_CTRL0_WORD_LENGTH |
530 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
531 GPMI_CTRL0_ADDRESS_NAND_DATA;
533 mxs_dma_desc_append(channel, d);
535 /* Invalidate caches */
536 mxs_nand_inval_data_buf(nand_info);
538 /* Execute the DMA chain. */
539 ret = mxs_dma_go(channel);
541 printf("MXS NAND: DMA read error\n");
545 /* Invalidate caches */
546 mxs_nand_inval_data_buf(nand_info);
548 memcpy(buf, nand_info->data_buf, length);
551 mxs_nand_return_dma_descs(nand_info);
555 * Write data to NAND.
557 static void mxs_nand_write_buf(struct mtd_info *mtd, const uint8_t *buf,
560 struct nand_chip *nand = mtd_to_nand(mtd);
561 struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
562 struct mxs_dma_desc *d;
563 uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
566 if (length > NAND_MAX_PAGESIZE) {
567 printf("MXS NAND: DMA buffer too big\n");
572 printf("MXS NAND: DMA buffer is NULL\n");
576 memcpy(nand_info->data_buf, buf, length);
578 /* Compile the DMA descriptor - a descriptor that writes data. */
579 d = mxs_nand_get_dma_desc(nand_info);
581 MXS_DMA_DESC_COMMAND_DMA_READ | MXS_DMA_DESC_IRQ |
582 MXS_DMA_DESC_DEC_SEM | MXS_DMA_DESC_WAIT4END |
583 (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
584 (length << MXS_DMA_DESC_BYTES_OFFSET);
586 d->cmd.address = (dma_addr_t)nand_info->data_buf;
588 d->cmd.pio_words[0] =
589 GPMI_CTRL0_COMMAND_MODE_WRITE |
590 GPMI_CTRL0_WORD_LENGTH |
591 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
592 GPMI_CTRL0_ADDRESS_NAND_DATA |
595 mxs_dma_desc_append(channel, d);
598 mxs_nand_flush_data_buf(nand_info);
600 /* Execute the DMA chain. */
601 ret = mxs_dma_go(channel);
603 printf("MXS NAND: DMA write error\n");
605 mxs_nand_return_dma_descs(nand_info);
609 * Read a single byte from NAND.
611 static uint8_t mxs_nand_read_byte(struct mtd_info *mtd)
614 mxs_nand_read_buf(mtd, &buf, 1);
618 static bool mxs_nand_erased_page(struct mtd_info *mtd, struct nand_chip *nand,
619 u8 *buf, int chunk, int page)
621 struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
622 struct bch_geometry *geo = &nand_info->bch_geometry;
623 unsigned int flip_bits = 0, flip_bits_noecc = 0;
624 unsigned int threshold;
625 unsigned int base = geo->ecc_chunkn_size * chunk;
626 u32 *dma_buf = (u32 *)buf;
629 threshold = geo->gf_len / 2;
630 if (threshold > geo->ecc_strength)
631 threshold = geo->ecc_strength;
633 for (i = 0; i < geo->ecc_chunkn_size; i++) {
634 flip_bits += hweight8(~buf[base + i]);
635 if (flip_bits > threshold)
639 nand->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
640 nand->read_buf(mtd, buf, mtd->writesize);
642 for (i = 0; i < mtd->writesize / 4; i++) {
643 flip_bits_noecc += hweight32(~dma_buf[i]);
644 if (flip_bits_noecc > threshold)
648 mtd->ecc_stats.corrected += flip_bits;
650 memset(buf, 0xff, mtd->writesize);
652 printf("The page(%d) is an erased page(%d,%d,%d,%d).\n", page, chunk, threshold, flip_bits, flip_bits_noecc);
658 * Read a page from NAND.
660 static int mxs_nand_ecc_read_page(struct mtd_info *mtd, struct nand_chip *nand,
661 uint8_t *buf, int oob_required,
664 struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
665 struct bch_geometry *geo = &nand_info->bch_geometry;
666 struct mxs_bch_regs *bch_regs = nand_info->bch_regs;
667 struct mxs_dma_desc *d;
668 uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
669 uint32_t corrected = 0, failed = 0;
674 /* Compile the DMA descriptor - wait for ready. */
675 d = mxs_nand_get_dma_desc(nand_info);
677 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN |
678 MXS_DMA_DESC_NAND_WAIT_4_READY | MXS_DMA_DESC_WAIT4END |
679 (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
683 d->cmd.pio_words[0] =
684 GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY |
685 GPMI_CTRL0_WORD_LENGTH |
686 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
687 GPMI_CTRL0_ADDRESS_NAND_DATA;
689 mxs_dma_desc_append(channel, d);
691 /* Compile the DMA descriptor - enable the BCH block and read. */
692 d = mxs_nand_get_dma_desc(nand_info);
694 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN |
695 MXS_DMA_DESC_WAIT4END | (6 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
699 d->cmd.pio_words[0] =
700 GPMI_CTRL0_COMMAND_MODE_READ |
701 GPMI_CTRL0_WORD_LENGTH |
702 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
703 GPMI_CTRL0_ADDRESS_NAND_DATA |
704 (mtd->writesize + mtd->oobsize);
705 d->cmd.pio_words[1] = 0;
706 d->cmd.pio_words[2] =
707 GPMI_ECCCTRL_ENABLE_ECC |
708 GPMI_ECCCTRL_ECC_CMD_DECODE |
709 GPMI_ECCCTRL_BUFFER_MASK_BCH_PAGE;
710 d->cmd.pio_words[3] = mtd->writesize + mtd->oobsize;
711 d->cmd.pio_words[4] = (dma_addr_t)nand_info->data_buf;
712 d->cmd.pio_words[5] = (dma_addr_t)nand_info->oob_buf;
714 if (nand_info->en_randomizer) {
715 d->cmd.pio_words[2] |= GPMI_ECCCTRL_RANDOMIZER_ENABLE |
716 GPMI_ECCCTRL_RANDOMIZER_TYPE2;
717 d->cmd.pio_words[3] |= (page % 256) << 16;
720 mxs_dma_desc_append(channel, d);
722 /* Compile the DMA descriptor - disable the BCH block. */
723 d = mxs_nand_get_dma_desc(nand_info);
725 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN |
726 MXS_DMA_DESC_NAND_WAIT_4_READY | MXS_DMA_DESC_WAIT4END |
727 (3 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
731 d->cmd.pio_words[0] =
732 GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY |
733 GPMI_CTRL0_WORD_LENGTH |
734 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
735 GPMI_CTRL0_ADDRESS_NAND_DATA |
736 (mtd->writesize + mtd->oobsize);
737 d->cmd.pio_words[1] = 0;
738 d->cmd.pio_words[2] = 0;
740 mxs_dma_desc_append(channel, d);
742 /* Compile the DMA descriptor - deassert the NAND lock and interrupt. */
743 d = mxs_nand_get_dma_desc(nand_info);
745 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_IRQ |
746 MXS_DMA_DESC_DEC_SEM;
750 mxs_dma_desc_append(channel, d);
752 /* Invalidate caches */
753 mxs_nand_inval_data_buf(nand_info);
755 /* Execute the DMA chain. */
756 ret = mxs_dma_go(channel);
758 printf("MXS NAND: DMA read error\n");
762 ret = mxs_nand_wait_for_bch_complete(nand_info);
764 printf("MXS NAND: BCH read timeout\n");
768 mxs_nand_return_dma_descs(nand_info);
770 /* Invalidate caches */
771 mxs_nand_inval_data_buf(nand_info);
773 /* Read DMA completed, now do the mark swapping. */
774 mxs_nand_swap_block_mark(geo, nand_info->data_buf, nand_info->oob_buf);
776 /* Loop over status bytes, accumulating ECC status. */
777 status = nand_info->oob_buf + mxs_nand_aux_status_offset();
778 for (i = 0; i < geo->ecc_chunk_count; i++) {
779 if (status[i] == 0x00)
782 if (status[i] == 0xff) {
783 if (!nand_info->en_randomizer &&
784 (is_mx6dqp() || is_mx7() || is_mx6ul() ||
785 is_imx8() || is_imx8m()))
786 if (readl(&bch_regs->hw_bch_debug1))
791 if (status[i] == 0xfe) {
792 if (mxs_nand_erased_page(mtd, nand,
793 nand_info->data_buf, i, page))
799 corrected += status[i];
802 /* Propagate ECC status to the owning MTD. */
803 mtd->ecc_stats.failed += failed;
804 mtd->ecc_stats.corrected += corrected;
807 * It's time to deliver the OOB bytes. See mxs_nand_ecc_read_oob() for
808 * details about our policy for delivering the OOB.
810 * We fill the caller's buffer with set bits, and then copy the block
811 * mark to the caller's buffer. Note that, if block mark swapping was
812 * necessary, it has already been done, so we can rely on the first
813 * byte of the auxiliary buffer to contain the block mark.
815 memset(nand->oob_poi, 0xff, mtd->oobsize);
817 nand->oob_poi[0] = nand_info->oob_buf[0];
819 memcpy(buf, nand_info->data_buf, mtd->writesize);
822 memset(buf, 0xff, mtd->writesize);
824 mxs_nand_return_dma_descs(nand_info);
830 * Write a page to NAND.
832 static int mxs_nand_ecc_write_page(struct mtd_info *mtd,
833 struct nand_chip *nand, const uint8_t *buf,
834 int oob_required, int page)
836 struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
837 struct bch_geometry *geo = &nand_info->bch_geometry;
838 struct mxs_dma_desc *d;
839 uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
842 memcpy(nand_info->data_buf, buf, mtd->writesize);
843 memcpy(nand_info->oob_buf, nand->oob_poi, mtd->oobsize);
845 /* Handle block mark swapping. */
846 mxs_nand_swap_block_mark(geo, nand_info->data_buf, nand_info->oob_buf);
848 /* Compile the DMA descriptor - write data. */
849 d = mxs_nand_get_dma_desc(nand_info);
851 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_IRQ |
852 MXS_DMA_DESC_DEC_SEM | MXS_DMA_DESC_WAIT4END |
853 (6 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
857 d->cmd.pio_words[0] =
858 GPMI_CTRL0_COMMAND_MODE_WRITE |
859 GPMI_CTRL0_WORD_LENGTH |
860 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
861 GPMI_CTRL0_ADDRESS_NAND_DATA;
862 d->cmd.pio_words[1] = 0;
863 d->cmd.pio_words[2] =
864 GPMI_ECCCTRL_ENABLE_ECC |
865 GPMI_ECCCTRL_ECC_CMD_ENCODE |
866 GPMI_ECCCTRL_BUFFER_MASK_BCH_PAGE;
867 d->cmd.pio_words[3] = (mtd->writesize + mtd->oobsize);
868 d->cmd.pio_words[4] = (dma_addr_t)nand_info->data_buf;
869 d->cmd.pio_words[5] = (dma_addr_t)nand_info->oob_buf;
871 if (nand_info->en_randomizer) {
872 d->cmd.pio_words[2] |= GPMI_ECCCTRL_RANDOMIZER_ENABLE |
873 GPMI_ECCCTRL_RANDOMIZER_TYPE2;
875 * Write NAND page number needed to be randomized
876 * to GPMI_ECCCOUNT register.
878 * The value is between 0-255. For additional details
879 * check 9.6.6.4 of i.MX7D Applications Processor reference
881 d->cmd.pio_words[3] |= (page % 256) << 16;
884 mxs_dma_desc_append(channel, d);
887 mxs_nand_flush_data_buf(nand_info);
889 /* Execute the DMA chain. */
890 ret = mxs_dma_go(channel);
892 printf("MXS NAND: DMA write error\n");
896 ret = mxs_nand_wait_for_bch_complete(nand_info);
898 printf("MXS NAND: BCH write timeout\n");
903 mxs_nand_return_dma_descs(nand_info);
908 * Read OOB from NAND.
910 * This function is a veneer that replaces the function originally installed by
911 * the NAND Flash MTD code.
913 static int mxs_nand_hook_read_oob(struct mtd_info *mtd, loff_t from,
914 struct mtd_oob_ops *ops)
916 struct nand_chip *chip = mtd_to_nand(mtd);
917 struct mxs_nand_info *nand_info = nand_get_controller_data(chip);
920 if (ops->mode == MTD_OPS_RAW)
921 nand_info->raw_oob_mode = 1;
923 nand_info->raw_oob_mode = 0;
925 ret = nand_info->hooked_read_oob(mtd, from, ops);
927 nand_info->raw_oob_mode = 0;
935 * This function is a veneer that replaces the function originally installed by
936 * the NAND Flash MTD code.
938 static int mxs_nand_hook_write_oob(struct mtd_info *mtd, loff_t to,
939 struct mtd_oob_ops *ops)
941 struct nand_chip *chip = mtd_to_nand(mtd);
942 struct mxs_nand_info *nand_info = nand_get_controller_data(chip);
945 if (ops->mode == MTD_OPS_RAW)
946 nand_info->raw_oob_mode = 1;
948 nand_info->raw_oob_mode = 0;
950 ret = nand_info->hooked_write_oob(mtd, to, ops);
952 nand_info->raw_oob_mode = 0;
958 * Mark a block bad in NAND.
960 * This function is a veneer that replaces the function originally installed by
961 * the NAND Flash MTD code.
963 static int mxs_nand_hook_block_markbad(struct mtd_info *mtd, loff_t ofs)
965 struct nand_chip *chip = mtd_to_nand(mtd);
966 struct mxs_nand_info *nand_info = nand_get_controller_data(chip);
969 nand_info->marking_block_bad = 1;
971 ret = nand_info->hooked_block_markbad(mtd, ofs);
973 nand_info->marking_block_bad = 0;
979 * There are several places in this driver where we have to handle the OOB and
980 * block marks. This is the function where things are the most complicated, so
981 * this is where we try to explain it all. All the other places refer back to
984 * These are the rules, in order of decreasing importance:
986 * 1) Nothing the caller does can be allowed to imperil the block mark, so all
987 * write operations take measures to protect it.
989 * 2) In read operations, the first byte of the OOB we return must reflect the
990 * true state of the block mark, no matter where that block mark appears in
993 * 3) ECC-based read operations return an OOB full of set bits (since we never
994 * allow ECC-based writes to the OOB, it doesn't matter what ECC-based reads
997 * 4) "Raw" read operations return a direct view of the physical bytes in the
998 * page, using the conventional definition of which bytes are data and which
999 * are OOB. This gives the caller a way to see the actual, physical bytes
1000 * in the page, without the distortions applied by our ECC engine.
1002 * What we do for this specific read operation depends on whether we're doing
1003 * "raw" read, or an ECC-based read.
1005 * It turns out that knowing whether we want an "ECC-based" or "raw" read is not
1006 * easy. When reading a page, for example, the NAND Flash MTD code calls our
1007 * ecc.read_page or ecc.read_page_raw function. Thus, the fact that MTD wants an
1008 * ECC-based or raw view of the page is implicit in which function it calls
1009 * (there is a similar pair of ECC-based/raw functions for writing).
1011 * Since MTD assumes the OOB is not covered by ECC, there is no pair of
1012 * ECC-based/raw functions for reading or or writing the OOB. The fact that the
1013 * caller wants an ECC-based or raw view of the page is not propagated down to
1016 * Since our OOB *is* covered by ECC, we need this information. So, we hook the
1017 * ecc.read_oob and ecc.write_oob function pointers in the owning
1018 * struct mtd_info with our own functions. These hook functions set the
1019 * raw_oob_mode field so that, when control finally arrives here, we'll know
1022 static int mxs_nand_ecc_read_oob(struct mtd_info *mtd, struct nand_chip *nand,
1025 struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
1028 * First, fill in the OOB buffer. If we're doing a raw read, we need to
1029 * get the bytes from the physical page. If we're not doing a raw read,
1030 * we need to fill the buffer with set bits.
1032 if (nand_info->raw_oob_mode) {
1034 * If control arrives here, we're doing a "raw" read. Send the
1035 * command to read the conventional OOB and read it.
1037 nand->cmdfunc(mtd, NAND_CMD_READ0, mtd->writesize, page);
1038 nand->read_buf(mtd, nand->oob_poi, mtd->oobsize);
1041 * If control arrives here, we're not doing a "raw" read. Fill
1042 * the OOB buffer with set bits and correct the block mark.
1044 memset(nand->oob_poi, 0xff, mtd->oobsize);
1046 nand->cmdfunc(mtd, NAND_CMD_READ0, mtd->writesize, page);
1047 mxs_nand_read_buf(mtd, nand->oob_poi, 1);
1055 * Write OOB data to NAND.
1057 static int mxs_nand_ecc_write_oob(struct mtd_info *mtd, struct nand_chip *nand,
1060 struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
1061 uint8_t block_mark = 0;
1064 * There are fundamental incompatibilities between the i.MX GPMI NFC and
1065 * the NAND Flash MTD model that make it essentially impossible to write
1066 * the out-of-band bytes.
1068 * We permit *ONE* exception. If the *intent* of writing the OOB is to
1069 * mark a block bad, we can do that.
1072 if (!nand_info->marking_block_bad) {
1073 printf("NXS NAND: Writing OOB isn't supported\n");
1077 /* Write the block mark. */
1078 nand->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1079 nand->write_buf(mtd, &block_mark, 1);
1080 nand->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1082 /* Check if it worked. */
1083 if (nand->waitfunc(mtd, nand) & NAND_STATUS_FAIL)
1090 * Claims all blocks are good.
1092 * In principle, this function is *only* called when the NAND Flash MTD system
1093 * isn't allowed to keep an in-memory bad block table, so it is forced to ask
1094 * the driver for bad block information.
1096 * In fact, we permit the NAND Flash MTD system to have an in-memory BBT, so
1097 * this function is *only* called when we take it away.
1099 * Thus, this function is only called when we want *all* blocks to look good,
1100 * so it *always* return success.
1102 static int mxs_nand_block_bad(struct mtd_info *mtd, loff_t ofs)
1107 static int mxs_nand_set_geometry(struct mtd_info *mtd, struct bch_geometry *geo)
1109 struct nand_chip *chip = mtd_to_nand(mtd);
1110 struct nand_chip *nand = mtd_to_nand(mtd);
1111 struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
1113 if (chip->ecc_strength_ds > nand_info->max_ecc_strength_supported) {
1114 printf("unsupported NAND chip, minimum ecc required %d\n"
1115 , chip->ecc_strength_ds);
1119 if ((!(chip->ecc_strength_ds > 0 && chip->ecc_step_ds > 0) &&
1120 mtd->oobsize < 1024) || nand_info->legacy_bch_geometry) {
1121 dev_warn(this->dev, "use legacy bch geometry\n");
1122 return mxs_nand_legacy_calc_ecc_layout(geo, mtd);
1125 if (mtd->oobsize > 1024 || chip->ecc_step_ds < mtd->oobsize)
1126 return mxs_nand_calc_ecc_for_large_oob(geo, mtd);
1128 return mxs_nand_calc_ecc_layout_by_info(geo, mtd,
1129 chip->ecc_strength_ds, chip->ecc_step_ds);
1135 * At this point, the physical NAND Flash chips have been identified and
1136 * counted, so we know the physical geometry. This enables us to make some
1137 * important configuration decisions.
1139 * The return value of this function propagates directly back to this driver's
1140 * board_nand_init(). Anything other than zero will cause this driver to
1141 * tear everything down and declare failure.
1143 int mxs_nand_setup_ecc(struct mtd_info *mtd)
1145 struct nand_chip *nand = mtd_to_nand(mtd);
1146 struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
1147 struct bch_geometry *geo = &nand_info->bch_geometry;
1148 struct mxs_bch_regs *bch_regs = nand_info->bch_regs;
1152 nand_info->en_randomizer = 0;
1153 nand_info->oobsize = mtd->oobsize;
1154 nand_info->writesize = mtd->writesize;
1156 ret = mxs_nand_set_geometry(mtd, geo);
1160 /* Configure BCH and set NFC geometry */
1161 mxs_reset_block(&bch_regs->hw_bch_ctrl_reg);
1163 /* Configure layout 0 */
1164 tmp = (geo->ecc_chunk_count - 1) << BCH_FLASHLAYOUT0_NBLOCKS_OFFSET;
1165 tmp |= MXS_NAND_METADATA_SIZE << BCH_FLASHLAYOUT0_META_SIZE_OFFSET;
1166 tmp |= (geo->ecc_strength >> 1) << BCH_FLASHLAYOUT0_ECC0_OFFSET;
1167 tmp |= geo->ecc_chunk0_size >> MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT;
1168 tmp |= (geo->gf_len == 14 ? 1 : 0) <<
1169 BCH_FLASHLAYOUT0_GF13_0_GF14_1_OFFSET;
1170 writel(tmp, &bch_regs->hw_bch_flash0layout0);
1171 nand_info->bch_flash0layout0 = tmp;
1173 tmp = (mtd->writesize + mtd->oobsize)
1174 << BCH_FLASHLAYOUT1_PAGE_SIZE_OFFSET;
1175 tmp |= (geo->ecc_strength >> 1) << BCH_FLASHLAYOUT1_ECCN_OFFSET;
1176 tmp |= geo->ecc_chunkn_size >> MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT;
1177 tmp |= (geo->gf_len == 14 ? 1 : 0) <<
1178 BCH_FLASHLAYOUT1_GF13_0_GF14_1_OFFSET;
1179 writel(tmp, &bch_regs->hw_bch_flash0layout1);
1180 nand_info->bch_flash0layout1 = tmp;
1182 /* Set erase threshold to ecc strength for mx6ul, mx6qp and mx7 */
1183 if (is_mx6dqp() || is_mx7() ||
1184 is_mx6ul() || is_imx8() || is_imx8m())
1185 writel(BCH_MODE_ERASE_THRESHOLD(geo->ecc_strength),
1186 &bch_regs->hw_bch_mode);
1188 /* Set *all* chip selects to use layout 0 */
1189 writel(0, &bch_regs->hw_bch_layoutselect);
1191 /* Enable BCH complete interrupt */
1192 writel(BCH_CTRL_COMPLETE_IRQ_EN, &bch_regs->hw_bch_ctrl_set);
1194 /* Hook some operations at the MTD level. */
1195 if (mtd->_read_oob != mxs_nand_hook_read_oob) {
1196 nand_info->hooked_read_oob = mtd->_read_oob;
1197 mtd->_read_oob = mxs_nand_hook_read_oob;
1200 if (mtd->_write_oob != mxs_nand_hook_write_oob) {
1201 nand_info->hooked_write_oob = mtd->_write_oob;
1202 mtd->_write_oob = mxs_nand_hook_write_oob;
1205 if (mtd->_block_markbad != mxs_nand_hook_block_markbad) {
1206 nand_info->hooked_block_markbad = mtd->_block_markbad;
1207 mtd->_block_markbad = mxs_nand_hook_block_markbad;
1214 * Allocate DMA buffers
1216 int mxs_nand_alloc_buffers(struct mxs_nand_info *nand_info)
1219 const int size = NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE;
1221 nand_info->data_buf_size = roundup(size, MXS_DMA_ALIGNMENT);
1224 buf = memalign(MXS_DMA_ALIGNMENT, nand_info->data_buf_size);
1226 printf("MXS NAND: Error allocating DMA buffers\n");
1230 memset(buf, 0, nand_info->data_buf_size);
1232 nand_info->data_buf = buf;
1233 nand_info->oob_buf = buf + NAND_MAX_PAGESIZE;
1234 /* Command buffers */
1235 nand_info->cmd_buf = memalign(MXS_DMA_ALIGNMENT,
1236 MXS_NAND_COMMAND_BUFFER_SIZE);
1237 if (!nand_info->cmd_buf) {
1239 printf("MXS NAND: Error allocating command buffers\n");
1242 memset(nand_info->cmd_buf, 0, MXS_NAND_COMMAND_BUFFER_SIZE);
1243 nand_info->cmd_queue_len = 0;
1249 * Initializes the NFC hardware.
1251 static int mxs_nand_init_dma(struct mxs_nand_info *info)
1253 int i = 0, j, ret = 0;
1255 info->desc = malloc(sizeof(struct mxs_dma_desc *) *
1256 MXS_NAND_DMA_DESCRIPTOR_COUNT);
1262 /* Allocate the DMA descriptors. */
1263 for (i = 0; i < MXS_NAND_DMA_DESCRIPTOR_COUNT; i++) {
1264 info->desc[i] = mxs_dma_desc_alloc();
1265 if (!info->desc[i]) {
1271 /* Init the DMA controller. */
1273 for (j = MXS_DMA_CHANNEL_AHB_APBH_GPMI0;
1274 j <= MXS_DMA_CHANNEL_AHB_APBH_GPMI7; j++) {
1275 ret = mxs_dma_init_channel(j);
1280 /* Reset the GPMI block. */
1281 mxs_reset_block(&info->gpmi_regs->hw_gpmi_ctrl0_reg);
1282 mxs_reset_block(&info->bch_regs->hw_bch_ctrl_reg);
1285 * Choose NAND mode, set IRQ polarity, disable write protection and
1288 clrsetbits_le32(&info->gpmi_regs->hw_gpmi_ctrl1,
1289 GPMI_CTRL1_GPMI_MODE,
1290 GPMI_CTRL1_ATA_IRQRDY_POLARITY | GPMI_CTRL1_DEV_RESET |
1291 GPMI_CTRL1_BCH_MODE);
1296 for (--j; j >= MXS_DMA_CHANNEL_AHB_APBH_GPMI0; j--)
1299 for (--i; i >= 0; i--)
1300 mxs_dma_desc_free(info->desc[i]);
1304 printf("MXS NAND: Unable to allocate DMA descriptors\n");
1308 int mxs_nand_init_spl(struct nand_chip *nand)
1310 struct mxs_nand_info *nand_info;
1313 nand_info = malloc(sizeof(struct mxs_nand_info));
1315 printf("MXS NAND: Failed to allocate private data\n");
1318 memset(nand_info, 0, sizeof(struct mxs_nand_info));
1320 nand_info->gpmi_regs = (struct mxs_gpmi_regs *)MXS_GPMI_BASE;
1321 nand_info->bch_regs = (struct mxs_bch_regs *)MXS_BCH_BASE;
1323 if (is_mx6sx() || is_mx7() || is_imx8() || is_imx8m())
1324 nand_info->max_ecc_strength_supported = 62;
1326 nand_info->max_ecc_strength_supported = 40;
1328 err = mxs_nand_alloc_buffers(nand_info);
1332 err = mxs_nand_init_dma(nand_info);
1336 nand_set_controller_data(nand, nand_info);
1338 nand->options |= NAND_NO_SUBPAGE_WRITE;
1340 nand->cmd_ctrl = mxs_nand_cmd_ctrl;
1341 nand->dev_ready = mxs_nand_device_ready;
1342 nand->select_chip = mxs_nand_select_chip;
1344 nand->read_byte = mxs_nand_read_byte;
1345 nand->read_buf = mxs_nand_read_buf;
1347 nand->ecc.read_page = mxs_nand_ecc_read_page;
1349 nand->ecc.mode = NAND_ECC_HW;
1354 int mxs_nand_init_ctrl(struct mxs_nand_info *nand_info)
1356 struct mtd_info *mtd;
1357 struct nand_chip *nand;
1360 nand = &nand_info->chip;
1361 mtd = nand_to_mtd(nand);
1362 err = mxs_nand_alloc_buffers(nand_info);
1366 err = mxs_nand_init_dma(nand_info);
1368 goto err_free_buffers;
1370 memset(&fake_ecc_layout, 0, sizeof(fake_ecc_layout));
1372 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
1373 nand->bbt_options |= NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB;
1376 nand_set_controller_data(nand, nand_info);
1377 nand->options |= NAND_NO_SUBPAGE_WRITE;
1380 nand->flash_node = dev_of_offset(nand_info->dev);
1382 nand->cmd_ctrl = mxs_nand_cmd_ctrl;
1384 nand->dev_ready = mxs_nand_device_ready;
1385 nand->select_chip = mxs_nand_select_chip;
1386 nand->block_bad = mxs_nand_block_bad;
1388 nand->read_byte = mxs_nand_read_byte;
1390 nand->read_buf = mxs_nand_read_buf;
1391 nand->write_buf = mxs_nand_write_buf;
1393 /* first scan to find the device and get the page size */
1394 if (nand_scan_ident(mtd, CONFIG_SYS_MAX_NAND_DEVICE, NULL))
1395 goto err_free_buffers;
1397 if (mxs_nand_setup_ecc(mtd))
1398 goto err_free_buffers;
1400 nand->ecc.read_page = mxs_nand_ecc_read_page;
1401 nand->ecc.write_page = mxs_nand_ecc_write_page;
1402 nand->ecc.read_oob = mxs_nand_ecc_read_oob;
1403 nand->ecc.write_oob = mxs_nand_ecc_write_oob;
1405 nand->ecc.layout = &fake_ecc_layout;
1406 nand->ecc.mode = NAND_ECC_HW;
1407 nand->ecc.size = nand_info->bch_geometry.ecc_chunkn_size;
1408 nand->ecc.strength = nand_info->bch_geometry.ecc_strength;
1410 /* second phase scan */
1411 err = nand_scan_tail(mtd);
1413 goto err_free_buffers;
1415 err = nand_register(0, mtd);
1417 goto err_free_buffers;
1422 free(nand_info->data_buf);
1423 free(nand_info->cmd_buf);
1428 #ifndef CONFIG_NAND_MXS_DT
1429 void board_nand_init(void)
1431 struct mxs_nand_info *nand_info;
1433 nand_info = malloc(sizeof(struct mxs_nand_info));
1435 printf("MXS NAND: Failed to allocate private data\n");
1438 memset(nand_info, 0, sizeof(struct mxs_nand_info));
1440 nand_info->gpmi_regs = (struct mxs_gpmi_regs *)MXS_GPMI_BASE;
1441 nand_info->bch_regs = (struct mxs_bch_regs *)MXS_BCH_BASE;
1443 /* Refer to Chapter 17 for i.MX6DQ, Chapter 18 for i.MX6SX */
1444 if (is_mx6sx() || is_mx7())
1445 nand_info->max_ecc_strength_supported = 62;
1447 nand_info->max_ecc_strength_supported = 40;
1449 #ifdef CONFIG_NAND_MXS_USE_MINIMUM_ECC
1450 nand_info->use_minimum_ecc = true;
1453 if (mxs_nand_init_ctrl(nand_info) < 0)
1464 * Read NAND layout for FCB block generation.
1466 void mxs_nand_get_layout(struct mtd_info *mtd, struct mxs_nand_layout *l)
1468 struct mxs_bch_regs *bch_regs = (struct mxs_bch_regs *)MXS_BCH_BASE;
1471 tmp = readl(&bch_regs->hw_bch_flash0layout0);
1472 l->nblocks = (tmp & BCH_FLASHLAYOUT0_NBLOCKS_MASK) >>
1473 BCH_FLASHLAYOUT0_NBLOCKS_OFFSET;
1474 l->meta_size = (tmp & BCH_FLASHLAYOUT0_META_SIZE_MASK) >>
1475 BCH_FLASHLAYOUT0_META_SIZE_OFFSET;
1477 tmp = readl(&bch_regs->hw_bch_flash0layout1);
1478 l->data0_size = 4 * ((tmp & BCH_FLASHLAYOUT0_DATA0_SIZE_MASK) >>
1479 BCH_FLASHLAYOUT0_DATA0_SIZE_OFFSET);
1480 l->ecc0 = (tmp & BCH_FLASHLAYOUT0_ECC0_MASK) >>
1481 BCH_FLASHLAYOUT0_ECC0_OFFSET;
1482 l->datan_size = 4 * ((tmp & BCH_FLASHLAYOUT1_DATAN_SIZE_MASK) >>
1483 BCH_FLASHLAYOUT1_DATAN_SIZE_OFFSET);
1484 l->eccn = (tmp & BCH_FLASHLAYOUT1_ECCN_MASK) >>
1485 BCH_FLASHLAYOUT1_ECCN_OFFSET;
1486 l->gf_len = (tmp & BCH_FLASHLAYOUT1_GF13_0_GF14_1_MASK) >>
1487 BCH_FLASHLAYOUT1_GF13_0_GF14_1_OFFSET;
1491 * Set BCH to specific layout used by ROM bootloader to read FCB.
1493 void mxs_nand_mode_fcb_62bit(struct mtd_info *mtd)
1496 struct mxs_bch_regs *bch_regs = (struct mxs_bch_regs *)MXS_BCH_BASE;
1497 struct nand_chip *nand = mtd_to_nand(mtd);
1498 struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
1500 nand_info->en_randomizer = 1;
1502 mtd->writesize = 1024;
1503 mtd->oobsize = 1862 - 1024;
1506 tmp = 7 << BCH_FLASHLAYOUT0_NBLOCKS_OFFSET;
1507 /* 32 bytes for metadata */
1508 tmp |= 32 << BCH_FLASHLAYOUT0_META_SIZE_OFFSET;
1509 /* using ECC62 level to be performed */
1510 tmp |= 0x1F << BCH_FLASHLAYOUT0_ECC0_OFFSET;
1511 /* 0x20 * 4 bytes of the data0 block */
1512 tmp |= 0x20 << BCH_FLASHLAYOUT0_DATA0_SIZE_OFFSET;
1513 tmp |= 0 << BCH_FLASHLAYOUT0_GF13_0_GF14_1_OFFSET;
1514 writel(tmp, &bch_regs->hw_bch_flash0layout0);
1516 /* 1024 for data + 838 for OOB */
1517 tmp = 1862 << BCH_FLASHLAYOUT1_PAGE_SIZE_OFFSET;
1518 /* using ECC62 level to be performed */
1519 tmp |= 0x1F << BCH_FLASHLAYOUT1_ECCN_OFFSET;
1520 /* 0x20 * 4 bytes of the data0 block */
1521 tmp |= 0x20 << BCH_FLASHLAYOUT1_DATAN_SIZE_OFFSET;
1522 tmp |= 0 << BCH_FLASHLAYOUT1_GF13_0_GF14_1_OFFSET;
1523 writel(tmp, &bch_regs->hw_bch_flash0layout1);
1527 * Set BCH to specific layout used by ROM bootloader to read FCB.
1529 void mxs_nand_mode_fcb_40bit(struct mtd_info *mtd)
1532 struct mxs_bch_regs *bch_regs = (struct mxs_bch_regs *)MXS_BCH_BASE;
1533 struct nand_chip *nand = mtd_to_nand(mtd);
1534 struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
1536 /* no randomizer in this setting*/
1537 nand_info->en_randomizer = 0;
1539 mtd->writesize = 1024;
1540 mtd->oobsize = 1576 - 1024;
1543 tmp = 7 << BCH_FLASHLAYOUT0_NBLOCKS_OFFSET;
1544 /* 32 bytes for metadata */
1545 tmp |= 32 << BCH_FLASHLAYOUT0_META_SIZE_OFFSET;
1546 /* using ECC40 level to be performed */
1547 tmp |= 0x14 << BCH_FLASHLAYOUT0_ECC0_OFFSET;
1548 /* 0x20 * 4 bytes of the data0 block */
1549 tmp |= 0x20 << BCH_FLASHLAYOUT0_DATA0_SIZE_OFFSET;
1550 tmp |= 0 << BCH_FLASHLAYOUT0_GF13_0_GF14_1_OFFSET;
1551 writel(tmp, &bch_regs->hw_bch_flash0layout0);
1553 /* 1024 for data + 552 for OOB */
1554 tmp = 1576 << BCH_FLASHLAYOUT1_PAGE_SIZE_OFFSET;
1555 /* using ECC40 level to be performed */
1556 tmp |= 0x14 << BCH_FLASHLAYOUT1_ECCN_OFFSET;
1557 /* 0x20 * 4 bytes of the data0 block */
1558 tmp |= 0x20 << BCH_FLASHLAYOUT1_DATAN_SIZE_OFFSET;
1559 tmp |= 0 << BCH_FLASHLAYOUT1_GF13_0_GF14_1_OFFSET;
1560 writel(tmp, &bch_regs->hw_bch_flash0layout1);
1564 * Restore BCH to normal settings.
1566 void mxs_nand_mode_normal(struct mtd_info *mtd)
1568 struct mxs_bch_regs *bch_regs = (struct mxs_bch_regs *)MXS_BCH_BASE;
1569 struct nand_chip *nand = mtd_to_nand(mtd);
1570 struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
1572 nand_info->en_randomizer = 0;
1574 mtd->writesize = nand_info->writesize;
1575 mtd->oobsize = nand_info->oobsize;
1577 writel(nand_info->bch_flash0layout0, &bch_regs->hw_bch_flash0layout0);
1578 writel(nand_info->bch_flash0layout1, &bch_regs->hw_bch_flash0layout1);
1581 uint32_t mxs_nand_mark_byte_offset(struct mtd_info *mtd)
1583 struct nand_chip *chip = mtd_to_nand(mtd);
1584 struct mxs_nand_info *nand_info = nand_get_controller_data(chip);
1585 struct bch_geometry *geo = &nand_info->bch_geometry;
1587 return geo->block_mark_byte_offset;
1590 uint32_t mxs_nand_mark_bit_offset(struct mtd_info *mtd)
1592 struct nand_chip *chip = mtd_to_nand(mtd);
1593 struct mxs_nand_info *nand_info = nand_get_controller_data(chip);
1594 struct bch_geometry *geo = &nand_info->bch_geometry;
1596 return geo->block_mark_bit_offset;