drivers/mtd/nand/raw/kirkwood_nand.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2009
   4  * Marvell Semiconductor <www.marvell.com>
   5  * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
   6  */
   7
   8 #include <common.h>
   9 #include <asm/io.h>
  10 #include <asm/arch/soc.h>
  11 #include <asm/arch/mpp.h>
  12 #include <nand.h>
  13
  14 /* NAND Flash Soc registers */
  15 struct kwnandf_registers {
  16         u32 rd_params;  /* 0x10418 */
  17         u32 wr_param;   /* 0x1041c */
  18         u8  pad[0x10470 - 0x1041c - 4];
  19         u32 ctrl;       /* 0x10470 */
  20 };
  21
  22 static struct kwnandf_registers *nf_reg =
  23         (struct kwnandf_registers *)KW_NANDF_BASE;
  24
  25 static u32 nand_mpp_backup[9] = { 0 };
  26
  27 /*
  28  * hardware specific access to control-lines/bits
  29  */
  30 #define NAND_ACTCEBOOT_BIT              0x02
  31
  32 static void kw_nand_hwcontrol(struct mtd_info *mtd, int cmd,
  33                               unsigned int ctrl)
  34 {
  35         struct nand_chip *nc = mtd_to_nand(mtd);
  36         u32 offs;
  37
  38         if (cmd == NAND_CMD_NONE)
  39                 return;
  40
  41         if (ctrl & NAND_CLE)
  42                 offs = (1 << 0);        /* Commands with A[1:0] == 01 */
  43         else if (ctrl & NAND_ALE)
  44                 offs = (1 << 1);        /* Addresses with A[1:0] == 10 */
  45         else
  46                 return;
  47
  48         writeb(cmd, nc->IO_ADDR_W + offs);
  49 }
  50
  51 void kw_nand_select_chip(struct mtd_info *mtd, int chip)
  52 {
  53         u32 data;
  54         static const u32 nand_config[] = {
  55                 MPP0_NF_IO2,
  56                 MPP1_NF_IO3,
  57                 MPP2_NF_IO4,
  58                 MPP3_NF_IO5,
  59                 MPP4_NF_IO6,
  60                 MPP5_NF_IO7,
  61                 MPP18_NF_IO0,
  62                 MPP19_NF_IO1,
  63                 0
  64         };
  65
  66         if (chip >= 0)
  67                 kirkwood_mpp_conf(nand_config, nand_mpp_backup);
  68         else
  69                 kirkwood_mpp_conf(nand_mpp_backup, NULL);
  70
  71         data = readl(&nf_reg->ctrl);
  72         data |= NAND_ACTCEBOOT_BIT;
  73         writel(data, &nf_reg->ctrl);
  74 }
  75
  76 int board_nand_init(struct nand_chip *nand)
  77 {
  78         nand->options = NAND_COPYBACK | NAND_CACHEPRG | NAND_NO_PADDING;
  79 #if defined(CONFIG_SYS_NAND_NO_SUBPAGE_WRITE)
  80         nand->options |= NAND_NO_SUBPAGE_WRITE;
  81 #endif
  82 #if defined(CONFIG_NAND_ECC_BCH)
  83         nand->ecc.mode = NAND_ECC_SOFT_BCH;
  84 #else
  85         nand->ecc.mode = NAND_ECC_SOFT;
  86 #endif
  87         nand->cmd_ctrl = kw_nand_hwcontrol;
  88         nand->chip_delay = 40;
  89         nand->select_chip = kw_nand_select_chip;
  90         return 0;
  91 }