drivers/mtd/nand/raw/ingenic/ingenic_nand_drv.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Ingenic JZ47xx NAND driver
   4  *
   5  * Copyright (c) 2015 Imagination Technologies
   6  * Author: Alex Smith <alex.smith@imgtec.com>
   7  */
   8
   9 #include <linux/delay.h>
  10 #include <linux/init.h>
  11 #include <linux/io.h>
  12 #include <linux/list.h>
  13 #include <linux/module.h>
  14 #include <linux/of.h>
  15 #include <linux/of_address.h>
  16 #include <linux/of_device.h>
  17 #include <linux/gpio/consumer.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/slab.h>
  20 #include <linux/mtd/mtd.h>
  21 #include <linux/mtd/rawnand.h>
  22 #include <linux/mtd/partitions.h>
  23
  24 #include <linux/jz4780-nemc.h>
  25
  26 #include "ingenic_ecc.h"
  27
  28 #define DRV_NAME        "ingenic-nand"
  29
  30 /* Command delay when there is no R/B pin. */
  31 #define RB_DELAY_US     100
  32
  33 struct jz_soc_info {
  34         unsigned long data_offset;
  35         unsigned long addr_offset;
  36         unsigned long cmd_offset;
  37         const struct mtd_ooblayout_ops *oob_layout;
  38 };
  39
  40 struct ingenic_nand_cs {
  41         unsigned int bank;
  42         void __iomem *base;
  43 };
  44
  45 struct ingenic_nfc {
  46         struct device *dev;
  47         struct ingenic_ecc *ecc;
  48         const struct jz_soc_info *soc_info;
  49         struct nand_controller controller;
  50         unsigned int num_banks;
  51         struct list_head chips;
  52         int selected;
  53         struct ingenic_nand_cs cs[];
  54 };
  55
  56 struct ingenic_nand {
  57         struct nand_chip chip;
  58         struct list_head chip_list;
  59
  60         struct gpio_desc *busy_gpio;
  61         struct gpio_desc *wp_gpio;
  62         unsigned int reading: 1;
  63 };
  64
  65 static inline struct ingenic_nand *to_ingenic_nand(struct mtd_info *mtd)
  66 {
  67         return container_of(mtd_to_nand(mtd), struct ingenic_nand, chip);
  68 }
  69
  70 static inline struct ingenic_nfc *to_ingenic_nfc(struct nand_controller *ctrl)
  71 {
  72         return container_of(ctrl, struct ingenic_nfc, controller);
  73 }
  74
  75 static int qi_lb60_ooblayout_ecc(struct mtd_info *mtd, int section,
  76                                  struct mtd_oob_region *oobregion)
  77 {
  78         struct nand_chip *chip = mtd_to_nand(mtd);
  79         struct nand_ecc_ctrl *ecc = &chip->ecc;
  80
  81         if (section || !ecc->total)
  82                 return -ERANGE;
  83
  84         oobregion->length = ecc->total;
  85         oobregion->offset = 12;
  86
  87         return 0;
  88 }
  89
  90 static int qi_lb60_ooblayout_free(struct mtd_info *mtd, int section,
  91                                   struct mtd_oob_region *oobregion)
  92 {
  93         struct nand_chip *chip = mtd_to_nand(mtd);
  94         struct nand_ecc_ctrl *ecc = &chip->ecc;
  95
  96         if (section)
  97                 return -ERANGE;
  98
  99         oobregion->length = mtd->oobsize - ecc->total - 12;
 100         oobregion->offset = 12 + ecc->total;
 101
 102         return 0;
 103 }
 104
 105 const struct mtd_ooblayout_ops qi_lb60_ooblayout_ops = {
 106         .ecc = qi_lb60_ooblayout_ecc,
 107         .free = qi_lb60_ooblayout_free,
 108 };
 109
 110 static int jz4725b_ooblayout_ecc(struct mtd_info *mtd, int section,
 111                                  struct mtd_oob_region *oobregion)
 112 {
 113         struct nand_chip *chip = mtd_to_nand(mtd);
 114         struct nand_ecc_ctrl *ecc = &chip->ecc;
 115
 116         if (section || !ecc->total)
 117                 return -ERANGE;
 118
 119         oobregion->length = ecc->total;
 120         oobregion->offset = 3;
 121
 122         return 0;
 123 }
 124
 125 static int jz4725b_ooblayout_free(struct mtd_info *mtd, int section,
 126                                   struct mtd_oob_region *oobregion)
 127 {
 128         struct nand_chip *chip = mtd_to_nand(mtd);
 129         struct nand_ecc_ctrl *ecc = &chip->ecc;
 130
 131         if (section)
 132                 return -ERANGE;
 133
 134         oobregion->length = mtd->oobsize - ecc->total - 3;
 135         oobregion->offset = 3 + ecc->total;
 136
 137         return 0;
 138 }
 139
 140 static const struct mtd_ooblayout_ops jz4725b_ooblayout_ops = {
 141         .ecc = jz4725b_ooblayout_ecc,
 142         .free = jz4725b_ooblayout_free,
 143 };
 144
 145 static void ingenic_nand_select_chip(struct nand_chip *chip, int chipnr)
 146 {
 147         struct ingenic_nand *nand = to_ingenic_nand(nand_to_mtd(chip));
 148         struct ingenic_nfc *nfc = to_ingenic_nfc(nand->chip.controller);
 149         struct ingenic_nand_cs *cs;
 150
 151         /* Ensure the currently selected chip is deasserted. */
 152         if (chipnr == -1 && nfc->selected >= 0) {
 153                 cs = &nfc->cs[nfc->selected];
 154                 jz4780_nemc_assert(nfc->dev, cs->bank, false);
 155         }
 156
 157         nfc->selected = chipnr;
 158 }
 159
 160 static void ingenic_nand_cmd_ctrl(struct nand_chip *chip, int cmd,
 161                                   unsigned int ctrl)
 162 {
 163         struct ingenic_nand *nand = to_ingenic_nand(nand_to_mtd(chip));
 164         struct ingenic_nfc *nfc = to_ingenic_nfc(nand->chip.controller);
 165         struct ingenic_nand_cs *cs;
 166
 167         if (WARN_ON(nfc->selected < 0))
 168                 return;
 169
 170         cs = &nfc->cs[nfc->selected];
 171
 172         jz4780_nemc_assert(nfc->dev, cs->bank, ctrl & NAND_NCE);
 173
 174         if (cmd == NAND_CMD_NONE)
 175                 return;
 176
 177         if (ctrl & NAND_ALE)
 178                 writeb(cmd, cs->base + nfc->soc_info->addr_offset);
 179         else if (ctrl & NAND_CLE)
 180                 writeb(cmd, cs->base + nfc->soc_info->cmd_offset);
 181 }
 182
 183 static int ingenic_nand_dev_ready(struct nand_chip *chip)
 184 {
 185         struct ingenic_nand *nand = to_ingenic_nand(nand_to_mtd(chip));
 186
 187         return !gpiod_get_value_cansleep(nand->busy_gpio);
 188 }
 189
 190 static void ingenic_nand_ecc_hwctl(struct nand_chip *chip, int mode)
 191 {
 192         struct ingenic_nand *nand = to_ingenic_nand(nand_to_mtd(chip));
 193
 194         nand->reading = (mode == NAND_ECC_READ);
 195 }
 196
 197 static int ingenic_nand_ecc_calculate(struct nand_chip *chip, const u8 *dat,
 198                                       u8 *ecc_code)
 199 {
 200         struct ingenic_nand *nand = to_ingenic_nand(nand_to_mtd(chip));
 201         struct ingenic_nfc *nfc = to_ingenic_nfc(nand->chip.controller);
 202         struct ingenic_ecc_params params;
 203
 204         /*
 205          * Don't need to generate the ECC when reading, the ECC engine does it
 206          * for us as part of decoding/correction.
 207          */
 208         if (nand->reading)
 209                 return 0;
 210
 211         params.size = nand->chip.ecc.size;
 212         params.bytes = nand->chip.ecc.bytes;
 213         params.strength = nand->chip.ecc.strength;
 214
 215         return ingenic_ecc_calculate(nfc->ecc, &params, dat, ecc_code);
 216 }
 217
 218 static int ingenic_nand_ecc_correct(struct nand_chip *chip, u8 *dat,
 219                                     u8 *read_ecc, u8 *calc_ecc)
 220 {
 221         struct ingenic_nand *nand = to_ingenic_nand(nand_to_mtd(chip));
 222         struct ingenic_nfc *nfc = to_ingenic_nfc(nand->chip.controller);
 223         struct ingenic_ecc_params params;
 224
 225         params.size = nand->chip.ecc.size;
 226         params.bytes = nand->chip.ecc.bytes;
 227         params.strength = nand->chip.ecc.strength;
 228
 229         return ingenic_ecc_correct(nfc->ecc, &params, dat, read_ecc);
 230 }
 231
 232 static int ingenic_nand_attach_chip(struct nand_chip *chip)
 233 {
 234         struct mtd_info *mtd = nand_to_mtd(chip);
 235         struct ingenic_nfc *nfc = to_ingenic_nfc(chip->controller);
 236         int eccbytes;
 237
 238         if (chip->ecc.strength == 4) {
 239                 /* JZ4740 uses 9 bytes of ECC to correct maximum 4 errors */
 240                 chip->ecc.bytes = 9;
 241         } else {
 242                 chip->ecc.bytes = fls((1 + 8) * chip->ecc.size) *
 243                                   (chip->ecc.strength / 8);
 244         }
 245
 246         switch (chip->ecc.mode) {
 247         case NAND_ECC_HW:
 248                 if (!nfc->ecc) {
 249                         dev_err(nfc->dev, "HW ECC selected, but ECC controller not found\n");
 250                         return -ENODEV;
 251                 }
 252
 253                 chip->ecc.hwctl = ingenic_nand_ecc_hwctl;
 254                 chip->ecc.calculate = ingenic_nand_ecc_calculate;
 255                 chip->ecc.correct = ingenic_nand_ecc_correct;
 256                 /* fall through */
 257         case NAND_ECC_SOFT:
 258                 dev_info(nfc->dev, "using %s (strength %d, size %d, bytes %d)\n",
 259                          (nfc->ecc) ? "hardware ECC" : "software ECC",
 260                          chip->ecc.strength, chip->ecc.size, chip->ecc.bytes);
 261                 break;
 262         case NAND_ECC_NONE:
 263                 dev_info(nfc->dev, "not using ECC\n");
 264                 break;
 265         default:
 266                 dev_err(nfc->dev, "ECC mode %d not supported\n",
 267                         chip->ecc.mode);
 268                 return -EINVAL;
 269         }
 270
 271         /* The NAND core will generate the ECC layout for SW ECC */
 272         if (chip->ecc.mode != NAND_ECC_HW)
 273                 return 0;
 274
 275         /* Generate ECC layout. ECC codes are right aligned in the OOB area. */
 276         eccbytes = mtd->writesize / chip->ecc.size * chip->ecc.bytes;
 277
 278         if (eccbytes > mtd->oobsize - 2) {
 279                 dev_err(nfc->dev,
 280                         "invalid ECC config: required %d ECC bytes, but only %d are available",
 281                         eccbytes, mtd->oobsize - 2);
 282                 return -EINVAL;
 283         }
 284
 285         /*
 286          * The generic layout for BBT markers will most likely overlap with our
 287          * ECC bytes in the OOB, so move the BBT markers outside the OOB area.
 288          */
 289         if (chip->bbt_options & NAND_BBT_USE_FLASH)
 290                 chip->bbt_options |= NAND_BBT_NO_OOB;
 291
 292         /* For legacy reasons we use a different layout on the qi,lb60 board. */
 293         if (of_machine_is_compatible("qi,lb60"))
 294                 mtd_set_ooblayout(mtd, &qi_lb60_ooblayout_ops);
 295         else
 296                 mtd_set_ooblayout(mtd, nfc->soc_info->oob_layout);
 297
 298         return 0;
 299 }
 300
 301 static const struct nand_controller_ops ingenic_nand_controller_ops = {
 302         .attach_chip = ingenic_nand_attach_chip,
 303 };
 304
 305 static int ingenic_nand_init_chip(struct platform_device *pdev,
 306                                   struct ingenic_nfc *nfc,
 307                                   struct device_node *np,
 308                                   unsigned int chipnr)
 309 {
 310         struct device *dev = &pdev->dev;
 311         struct ingenic_nand *nand;
 312         struct ingenic_nand_cs *cs;
 313         struct resource *res;
 314         struct nand_chip *chip;
 315         struct mtd_info *mtd;
 316         const __be32 *reg;
 317         int ret = 0;
 318
 319         cs = &nfc->cs[chipnr];
 320
 321         reg = of_get_property(np, "reg", NULL);
 322         if (!reg)
 323                 return -EINVAL;
 324
 325         cs->bank = be32_to_cpu(*reg);
 326
 327         jz4780_nemc_set_type(nfc->dev, cs->bank, JZ4780_NEMC_BANK_NAND);
 328
 329         res = platform_get_resource(pdev, IORESOURCE_MEM, chipnr);
 330         cs->base = devm_ioremap_resource(dev, res);
 331         if (IS_ERR(cs->base))
 332                 return PTR_ERR(cs->base);
 333
 334         nand = devm_kzalloc(dev, sizeof(*nand), GFP_KERNEL);
 335         if (!nand)
 336                 return -ENOMEM;
 337
 338         nand->busy_gpio = devm_gpiod_get_optional(dev, "rb", GPIOD_IN);
 339
 340         if (IS_ERR(nand->busy_gpio)) {
 341                 ret = PTR_ERR(nand->busy_gpio);
 342                 dev_err(dev, "failed to request busy GPIO: %d\n", ret);
 343                 return ret;
 344         } else if (nand->busy_gpio) {
 345                 nand->chip.legacy.dev_ready = ingenic_nand_dev_ready;
 346         }
 347
 348         nand->wp_gpio = devm_gpiod_get_optional(dev, "wp", GPIOD_OUT_LOW);
 349
 350         if (IS_ERR(nand->wp_gpio)) {
 351                 ret = PTR_ERR(nand->wp_gpio);
 352                 dev_err(dev, "failed to request WP GPIO: %d\n", ret);
 353                 return ret;
 354         }
 355
 356         chip = &nand->chip;
 357         mtd = nand_to_mtd(chip);
 358         mtd->name = devm_kasprintf(dev, GFP_KERNEL, "%s.%d", dev_name(dev),
 359                                    cs->bank);
 360         if (!mtd->name)
 361                 return -ENOMEM;
 362         mtd->dev.parent = dev;
 363
 364         chip->legacy.IO_ADDR_R = cs->base + nfc->soc_info->data_offset;
 365         chip->legacy.IO_ADDR_W = cs->base + nfc->soc_info->data_offset;
 366         chip->legacy.chip_delay = RB_DELAY_US;
 367         chip->options = NAND_NO_SUBPAGE_WRITE;
 368         chip->legacy.select_chip = ingenic_nand_select_chip;
 369         chip->legacy.cmd_ctrl = ingenic_nand_cmd_ctrl;
 370         chip->ecc.mode = NAND_ECC_HW;
 371         chip->controller = &nfc->controller;
 372         nand_set_flash_node(chip, np);
 373
 374         chip->controller->ops = &ingenic_nand_controller_ops;
 375         ret = nand_scan(chip, 1);
 376         if (ret)
 377                 return ret;
 378
 379         ret = mtd_device_register(mtd, NULL, 0);
 380         if (ret) {
 381                 nand_release(chip);
 382                 return ret;
 383         }
 384
 385         list_add_tail(&nand->chip_list, &nfc->chips);
 386
 387         return 0;
 388 }
 389
 390 static void ingenic_nand_cleanup_chips(struct ingenic_nfc *nfc)
 391 {
 392         struct ingenic_nand *chip;
 393
 394         while (!list_empty(&nfc->chips)) {
 395                 chip = list_first_entry(&nfc->chips,
 396                                         struct ingenic_nand, chip_list);
 397                 nand_release(&chip->chip);
 398                 list_del(&chip->chip_list);
 399         }
 400 }
 401
 402 static int ingenic_nand_init_chips(struct ingenic_nfc *nfc,
 403                                    struct platform_device *pdev)
 404 {
 405         struct device *dev = &pdev->dev;
 406         struct device_node *np;
 407         int i = 0;
 408         int ret;
 409         int num_chips = of_get_child_count(dev->of_node);
 410
 411         if (num_chips > nfc->num_banks) {
 412                 dev_err(dev, "found %d chips but only %d banks\n",
 413                         num_chips, nfc->num_banks);
 414                 return -EINVAL;
 415         }
 416
 417         for_each_child_of_node(dev->of_node, np) {
 418                 ret = ingenic_nand_init_chip(pdev, nfc, np, i);
 419                 if (ret) {
 420                         ingenic_nand_cleanup_chips(nfc);
 421                         return ret;
 422                 }
 423
 424                 i++;
 425         }
 426
 427         return 0;
 428 }
 429
 430 static int ingenic_nand_probe(struct platform_device *pdev)
 431 {
 432         struct device *dev = &pdev->dev;
 433         unsigned int num_banks;
 434         struct ingenic_nfc *nfc;
 435         int ret;
 436
 437         num_banks = jz4780_nemc_num_banks(dev);
 438         if (num_banks == 0) {
 439                 dev_err(dev, "no banks found\n");
 440                 return -ENODEV;
 441         }
 442
 443         nfc = devm_kzalloc(dev, struct_size(nfc, cs, num_banks), GFP_KERNEL);
 444         if (!nfc)
 445                 return -ENOMEM;
 446
 447         nfc->soc_info = device_get_match_data(dev);
 448         if (!nfc->soc_info)
 449                 return -EINVAL;
 450
 451         /*
 452          * Check for ECC HW before we call nand_scan_ident, to prevent us from
 453          * having to call it again if the ECC driver returns -EPROBE_DEFER.
 454          */
 455         nfc->ecc = of_ingenic_ecc_get(dev->of_node);
 456         if (IS_ERR(nfc->ecc))
 457                 return PTR_ERR(nfc->ecc);
 458
 459         nfc->dev = dev;
 460         nfc->num_banks = num_banks;
 461
 462         nand_controller_init(&nfc->controller);
 463         INIT_LIST_HEAD(&nfc->chips);
 464
 465         ret = ingenic_nand_init_chips(nfc, pdev);
 466         if (ret) {
 467                 if (nfc->ecc)
 468                         ingenic_ecc_release(nfc->ecc);
 469                 return ret;
 470         }
 471
 472         platform_set_drvdata(pdev, nfc);
 473         return 0;
 474 }
 475
 476 static int ingenic_nand_remove(struct platform_device *pdev)
 477 {
 478         struct ingenic_nfc *nfc = platform_get_drvdata(pdev);
 479
 480         if (nfc->ecc)
 481                 ingenic_ecc_release(nfc->ecc);
 482
 483         ingenic_nand_cleanup_chips(nfc);
 484
 485         return 0;
 486 }
 487
 488 static const struct jz_soc_info jz4740_soc_info = {
 489         .data_offset = 0x00000000,
 490         .cmd_offset = 0x00008000,
 491         .addr_offset = 0x00010000,
 492         .oob_layout = &nand_ooblayout_lp_ops,
 493 };
 494
 495 static const struct jz_soc_info jz4725b_soc_info = {
 496         .data_offset = 0x00000000,
 497         .cmd_offset = 0x00008000,
 498         .addr_offset = 0x00010000,
 499         .oob_layout = &jz4725b_ooblayout_ops,
 500 };
 501
 502 static const struct jz_soc_info jz4780_soc_info = {
 503         .data_offset = 0x00000000,
 504         .cmd_offset = 0x00400000,
 505         .addr_offset = 0x00800000,
 506         .oob_layout = &nand_ooblayout_lp_ops,
 507 };
 508
 509 static const struct of_device_id ingenic_nand_dt_match[] = {
 510         { .compatible = "ingenic,jz4740-nand", .data = &jz4740_soc_info },
 511         { .compatible = "ingenic,jz4725b-nand", .data = &jz4725b_soc_info },
 512         { .compatible = "ingenic,jz4780-nand", .data = &jz4780_soc_info },
 513         {},
 514 };
 515 MODULE_DEVICE_TABLE(of, ingenic_nand_dt_match);
 516
 517 static struct platform_driver ingenic_nand_driver = {
 518         .probe          = ingenic_nand_probe,
 519         .remove         = ingenic_nand_remove,
 520         .driver = {
 521                 .name   = DRV_NAME,
 522                 .of_match_table = of_match_ptr(ingenic_nand_dt_match),
 523         },
 524 };
 525 module_platform_driver(ingenic_nand_driver);
 526
 527 MODULE_AUTHOR("Alex Smith <alex@alex-smith.me.uk>");
 528 MODULE_AUTHOR("Harvey Hunt <harveyhuntnexus@gmail.com>");
 529 MODULE_DESCRIPTION("Ingenic JZ47xx NAND driver");
 530 MODULE_LICENSE("GPL v2");